1 /** 2 ***************************************************************************** 3 * @file cmem7_ddr.h 4 * 5 * @brief CMEM7 AES header file 6 * 7 * 8 * @version V1.0 9 * @date 3. September 2013 10 * 11 * @note 12 * 13 ***************************************************************************** 14 * @attention 15 * 16 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 17 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 18 * TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 19 * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 20 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 21 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 22 * 23 * <h2><center>© COPYRIGHT 2013 Capital-micro </center></h2> 24 ***************************************************************************** 25 */ 26 27 #ifndef __CMEM7_DDR_H 28 #define __CMEM7_DDR_H 29 30 #ifdef __cplusplus 31 extern "C" { 32 #endif 33 34 #include "cmem7.h" 35 #include "cmem7_conf.h" 36 /** @defgroup _MEM_TYPE 37 * @{ 38 */ 39 enum _MEM_TYPE 40 { 41 MEM_DDR2=1, 42 MEM_DDR3 43 } ; 44 /** 45 * @} 46 */ 47 48 /** @defgroup _BUS_WIDTH 49 * @{ 50 */ 51 enum _BUS_WIDTH 52 { 53 BUS_WIDTH_8, 54 BUS_WIDTH_16, 55 BUS_WIDTH_MAX 56 }; 57 /** 58 * @} 59 */ 60 /** @defgroup _CHIP_TYPE 61 * @{ 62 */ 63 enum _CHIP_TYPE 64 { 65 _32Mbx8, 66 _64Mbx8, 67 _128Mbx8, 68 _256Mbx8, 69 _512Mbx8, 70 _16Mbx16, 71 _32Mbx16, 72 _64Mbx16, 73 _128Mbx16, 74 _256Mbx16, 75 _512Mbx16, 76 CHIP_TYPE_MAX 77 }; 78 /** 79 * @} 80 */ 81 82 /** @defgroup _CHIP_NUM 83 * @{ 84 */ 85 enum _CHIP_NUM 86 { 87 CHIP_NUM_x1, 88 CHIP_NUM_x2, 89 CHIP_NUM_MAX 90 }; 91 /** 92 * @} 93 */ 94 95 /** @defgroup MEM_CHIP_INFO 96 * @{ 97 */ 98 typedef struct { 99 uint8_t mem_type; /*!< ddr type @ref _MEM_TYPE*/ 100 uint8_t Bus_width; /*!< ddr qs bus width @ref _BUS_WIDTH*/ 101 uint8_t Chip_type; /*!< chip type @ref _CHIP_TYPE*/ 102 uint8_t Chip_num; /*!< chip number @ref _CHIP_NUM*/ 103 uint8_t Chip_bank; /*!< chip bank number*/ 104 } MEM_CHIP_INFO; 105 /** 106 * @} 107 */ 108 109 110 /** @defgroup DDR2MEM 111 * @{ 112 */ 113 typedef struct { 114 uint32_t tCK; /*!< Period of clock(ps), not data period */ 115 uint32_t tCL; /*!< tCL */ 116 uint32_t tRCD; /*!< tRCD */ 117 uint32_t tRP; /*!< tRP */ 118 uint32_t tRC; /*!< tRC */ 119 uint32_t tRAS; /*!< tRAS */ 120 uint32_t tWR; /*!< tWR */ 121 uint32_t tRRD; /*!< tRRD */ 122 uint32_t tWTR; /*!< tWTR */ 123 uint32_t tRTP; /*!< tRTP */ 124 uint32_t tFAW; /*!< tFAW */ 125 } DDR2MEM; /*!< DDR2时序定义 */ 126 /** 127 * @} 128 */ 129 130 /** @defgroup DDR3MEM 131 * @{ 132 */ 133 typedef struct { 134 uint32_t tCK; /*!< Period of clock(ps), not data period */ 135 uint32_t tCL; /*!< tCL */ 136 uint32_t tWCL; /*!< tWCL */ 137 uint32_t tRCD; /*!< tRCD */ 138 uint32_t tRAS; /*!< tRAS */ 139 uint32_t tRP; /*!< tRP */ 140 uint32_t tRC; /*!< tRC */ 141 uint32_t tRRD; /*!< tRRD */ 142 uint32_t tFAW; /*!< tFAW */ 143 uint32_t tWR; /*!< tWR */ 144 uint32_t tRTP; /*!< tRTP */ 145 uint32_t tZQoper; /*!< tZQCL */ 146 uint32_t tZQCS; /*!< tZQCS */ 147 } DDR3MEM; /*!< DDR3时序定义 */ 148 /** 149 * @} 150 */ 151 152 /** @defgroup DDR2PREDEF 153 * @{ 154 */ 155 extern const DDR2MEM DDR2PREDEF[]; /*!< Pre-defined DDR2 Timing in library */ 156 #define DDR2_400C 0 /*!< sg5E: DDR2-400C CL=4, tCK=5000ps */ 157 158 /** 159 * @} 160 */ 161 162 /** @defgroup DDR3PREDEF 163 * @{ 164 */ 165 extern const DDR3MEM DDR3PREDEF[]; /*!< Pre-defined DDR3 Timing in library */ 166 #define DDR3_400 0 167 #define DDR3_667 1 168 169 /** 170 * @} 171 */ 172 173 /** 174 * @brief DDR Timing Configuration 175 * @param[in] chip information ,A pointer to struct @ref MEM_CHIP_INFO 176 * @param[in] ddr A pointer to struct @ref DDR2MEM or @ref DDR3MEM that specified DDR Timing. Some typital DDR2/3 Timings are defined in arrays @ref DDR2PREDEF and @ref DDR3PREDEF. 177 * @retval void 178 */ 179 BOOL DDR_Init(const MEM_CHIP_INFO *chip_info, const void *ddr); 180 #ifdef __cplusplus 181 } 182 #endif 183 184 #endif /* __CMEM7_DDR_H */ 185 186