1 /**
2 *****************************************************************************
3 * @file cmem7_ddr.c
4 *
5 * @brief CMEM7 DDR source file
6 *
7 *
8 * @version V1.0
9 * @date 3. September 2013
10 *
11 * @note
12 *
13 *****************************************************************************
14 * @attention
15 *
16 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
17 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
18 * TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
19 * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
20 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
21 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
22 *
23 * <h2><center>© COPYRIGHT 2013 Capital-micro </center></h2>
24 *****************************************************************************
25 */
26
27 #include "cmem7_ddr.h"
28
29 #define MAX(a, b) ((a >= b) ? (a) : (b))
30 #define CAL_DDR3_CL(cl) ((cl>11)?(((cl-12)<<MR_CL_OFFSET)|0x4):((cl-4)<<MR_CL_OFFSET))
31
32 #define CHIP_MIN_CAPACITY 32
33 #define CHIP_CAPACITY_32MB CHIP_MIN_CAPACITY
34 #define CHIP_CAPACITY_64MB (CHIP_CAPACITY_32MB*2)
35 #define CHIP_CAPACITY_128MB (CHIP_CAPACITY_64MB*2)
36 #define CHIP_CAPACITY_256MB (CHIP_CAPACITY_128MB*2)
37 #define CHIP_CAPACITY_512MB (CHIP_CAPACITY_256MB*2)
38 #define CHIP_CAPACITY_1024MB (CHIP_CAPACITY_512MB*2)
39
40 /** @defgroup DDR time
41 * @{
42 */
43 #define POWER_UP_NOP 200*1000 /*ns*//*JEDEC Standard No. 79-2E page 17 */
44 #define PRE_ALL_NOP 400 /*ns*/
45 #define POWER_UP_MIN_CK 200
46 #define DDR2_TMRD 2 /*JEDEC Standard No. 79-2E page 80 */
47 #define DDR3_TMRD 4 /*JEDEC Standard No. 79-2E page 80 */
48 #define DDR3_TMOD_CK 12 /*JEDEC Standard No. 79-3E page 171 table 68 */
49 #define DDR3_TMOD 15 /*ns*/ /*JEDEC Standard No. 79-3E page 171 table 68 */
50 #define DDR3_TZQINIT_CK 512 /*JEDEC Standard No. 79-3E page 171 table 68 */
51 #define DDR3_TZQINIT 640 /*ns*/ /*JEDEC Standard No. 79-3E page 171 table 68 */
52 #define DDR3_TDLLK_CK 512 /*JEDEC Standard No. 79-3E page 171 table 68 */
53 #define RSTH_NOP 500*1000 /*ns*//*JEDEC Standard No. 79-3E page 20 */
54 #define DDR_TREF 7800 /*ns*/
55 /**
56 * @}
57 */
58 #ifndef NULL
59 #define NULL 0
60 #endif
61
62 /** @defgroup DDRC_SW_PROC_CMD
63 * @{
64 */
65 #define SW_CMD_NO_PARM 0
66 #define SW_CMD_DES 0x0 /*des 5'b00000 [31:29]=3'b000 [28:0] DES time cke hold*/
67 #define SW_CMD_NOP 0x20000000 /*nop 5'b00100 [31:29]=3'b001 [28:0] NOP time cke hold*/
68 #define SW_CMD_DESCKE 0x40000000 /*descke 5'b01000 [31:29]=3'b010 [28:0] DES time change cke high*/
69 #define SW_CMD_NOPCKE 0x60000000 /*nopcke 5'b01100 [31:29]=3'b011 [28:0] NOP time change cke high*/
70 #define SW_CMD_PREA 0x80000000 /*nopcke 5'b10000 [31:27]=5'b10000 */
71
72 #define SW_CMD_MR 0x88000000 /*JEDEC Standard No. 79-2E page 19 */
73 #define SW_CMD_EMR1 0x88010000 /*JEDEC Standard No. 79-2E page 19 */
74 #define SW_CMD_EMR2 0x88020000
75 #define SW_CMD_EMR3 0x88030000
76 #define SW_CMD_EMR1_TEST 0x88010004
77 #define SW_CMD_REF 0x90000000 /*REF 5'b10010 [31:27]=5'b10010 */
78
79 #define SW_CMD_RSTH 0xb0000000 /*RSTH 5'b10110 [31:27]=5'b10110 */
80 #define SW_CMD_ZQCL 0xb8000000 /*ZQCL 5'b10111 [31:27]=5'b10111 */
81
82 #define SW_CMD_DLL_EN 0x880103C4
83 #define SW_CMD_DLL_RST 0x88000953
84 /**
85 * @}
86 */
87 /** @defgroup DDR2 mode register
88 * @{
89 */
90 /*JEDEC Standard */
91 #define MR_BURST_LEN_4 0x2
92 #define MR_BURST_LEN_8 0x3
93 #define MR_BT_SEQ 0x0
94 #define MR_BT_INT 0x08
95 #define MR_CL_OFFSET 4
96 #define MR_TM_NORMAL 0
97 #define MR_TM_TEST 0x80
98 #define MR_DLL_NO 0
99 #define MR_DLL_YES 0x100
100 #define MR_WR_OFFSET 9
101 #define MR_PPD_FAST 0x1000
102 #define MR2_CWL_OFFSET 3
103 #define MR1_RZQ_4 0x4
104 /**
105 * @}
106 */
107 const uint8_t DDR2_MODE[BUS_WIDTH_MAX][CHIP_NUM_MAX][CHIP_TYPE_MAX]=
108 {
109 {
110 {0x20,0x23,0x28,0x2a,0x30,0x21,0x22,0x29,0x2b,0x31,0xff},/*chip x1*/
111 {0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff}/*chip x2*/
112 },/*bus width x8*/
113
114 {
115 {0xff,0xff,0xff,0xff,0xff,0x25,0x26,0x2d,0x2f,0x33,0xff},/*chip x1*/
116 {0x24,0x27,0x2c,0x2e,0x32,0xff,0xff,0xff,0xff,0xff,0xff}/*chip x2*/
117 }/*bus width x16*/
118 };
119 const uint8_t DDR3_MODE[BUS_WIDTH_MAX][CHIP_NUM_MAX][CHIP_TYPE_MAX]=
120 {
121 {
122 {0xff,0x00,0x01,0x02,0x03,0xff,0x04,0x05,0x06,0x07,0x10},/*chip x1*/
123 {0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff}/*chip x2*/
124 },/*bus width x8*/
125
126 {
127 {0xff,0xff,0xff,0xff,0xff,0xff,0x0c,0x0d,0x0e,0x0f,0x11},/*chip x1*/
128 {0xff,0x08,0x09,0x0a,0x0b,0xff,0xff,0xff,0xff,0xff,0xff}/*chip x2*/
129 }/*bus width x16*/
130 };
131 const DDR2MEM DDR2PREDEF[] = {
132 {
133 // #define DDR2_400C 4 // sg5E //DDR2-400C CL=4, tCK=5000 ps (dev-brd using)
134 /*tCK*/ 5000,
135 /*tCL*/ 6,//4,
136 /*RCD*/4, /*RP*/4, /*RC*/13, /*RAS*/9, /*WR*/3, /*RRD*/2, /*WTR*/11, /*RTP*/4,
137 /*FAW*/10,
138 },
139
140 {
141 // #define DDR2_800D 0 // sg25E //DDR2-800D CL=5, tCK=2500 ps
142 /*tCK*/ 2500,
143 /*tCL*/ 5, /*RCD*/5, /*RP*/5, /*RC*/24, //from sim model
144 /*RAS*/18, /*WR*/6, /*RRD*/4, /*WTR*/11, /*RTP*/5,
145 /*FAW*/30, //from sim model
146 }, {
147 // #define DDR2_667C 1 // sg3E //DDR2-667C CL=4, tCK=3000 ps
148 /*tCK*/ 3000,
149 /*tCL*/ 4, /*RCD*/4, /*RP*/4, /*RC*/19, /*RAS*/15, /*WR*/5, /*RRD*/4, /*WTR*/10, /*RTP*/5,
150 /*FAW*/17,
151 }, {
152 // #define DDR2_667D 2 // sg3 //DDR2-667D CL=5, tCK=3000 ps
153 /*tCK*/ 3000,
154 /*tCL*/ 5, /*RCD*/5, /*RP*/5, /*RC*/20, /*RAS*/15, /*WR*/5, /*RRD*/4, /*WTR*/3, /*RTP*/3,
155 /*FAW*/17,
156 }, {
157 // #define DDR2_533C 3 // sg37E //DDR2-533C CL=4, tCK=3750 ps
158 /*tCK*/ 3750,
159 /*tCL*/ 4, /*RCD*/4, /*RP*/4, /*RC*/16, /*RAS*/12, /*WR*/4, /*RRD*/3, /*WTR*/9, /*RTP*/4,
160 /*FAW*/14,
161 },
162 };
163
164 const DDR3MEM DDR3PREDEF[] = {
165 {
166 // #define DDR3_400 14 // Base on DDR3-800D (5-5-5) tCK=5ns
167 /*tCK*/ 2500,
168 /*tCL*//*9*/ 5, /*WCL*/7/*cwl should be 5 ,but phy has 2 cycles delay.So,wcl should plus the 2 cycles delay.*/ , /*RCD*//*9*/5, /*RAS*//*24*/8, /*RP*//*9*/5, /*RC*//*33*/10, /*RRD*/ 100,
169 /*FAW*//*30*/10, /*WR*/5/*10*/, /*RTP*/4, /*ZQCL*/256, /*ZQCS*/64,
170 } ,
171
172 {
173 // #define DDR3_667 15 // Base on DDR3-800D (5-5-5) tCK=5ns
174 /*tCK*/ 3000,
175 /*tCL*//*9*/ 5, /*WCL*/7 /*cwl should be 5 ,but phy has 2 cycles delay.So,wcl should plus the 2 cycles delay.*/ , /*RCD*//*9*/5, /*RAS*//*24*/30, /*RP*//*9*/5, /*RC*//*33*/60, /*RRD*/16,
176 /*FAW*//*30*/17, /*WR*/5/*10*/, /*RTP*/4, /*ZQCL*/256, /*ZQCS*/64,
177 },
178
179 {
180 // #define DDR3_2133N 0 // sg093 //DDR3-2133N (14-14-14) tCK=0.938ns
181 /*tCK*/ 938,
182 /*tCL*/ 14, /*WCL*/10, /*RCD*/14, /*RAS*/36, /*RP*/14, /*RC*/50, /*RRD*/7,
183 /*FAW*/38, /*WR*/16, /*RTP*/10, /*ZQCL*/342, /*ZQCS*/86,
184 }, {
185 // #define DDR3_2133M 1 // sg093E //DDR3-2133M (13-13-13) tCK=0.938ns
186 /*tCK*/ 938,
187 /*tCL*/ 13, /*WCL*/10, /*RCD*/13, /*RAS*/36, /*RP*/13, /*RC*/49, /*RRD*/7,
188 /*FAW*/38, /*WR*/16, /*RTP*/10, /*ZQCL*/342, /*ZQCS*/86,
189 }, {
190 // #define DDR3_2133L 2 // sg093F //DDR3-2133L (12-12-12) tCK=0.938ns
191 /*tCK*/ 938,
192 /*tCL*/ 12, /*WCL*/10, /*RCD*/12, /*RAS*/36, /*RP*/12, /*RC*/48, /*RRD*/7,
193 /*FAW*/38, /*WR*/16, /*RTP*/10, /*ZQCL*/342, /*ZQCS*/86,
194 }, {
195 // #define DDR3_1866L 3 // sg107E //DDR3-1866L (12-12-12) tCK=1.07ns
196 /*tCK*/ 1070,
197 /*tCL*/ 12, /*WCL*/9, /*RCD*/12, /*RAS*/32, /*RP*/12, /*RC*/44, /*RRD*/6,
198 /*FAW*/33, /*WR*/14, /*RTP*/9, /*ZQCL*/300, /*ZQCS*/75,
199 }, {
200 // #define DDR3_1866K 4 // sg107F //DDR3-1866K (11-11-11) tCK=1.07ns
201 /*tCK*/ 1070,
202 /*tCL*/ 11, /*WCL*/9, /*RCD*/11, /*RAS*/32, /*RP*/11, /*RC*/43, /*RRD*/6,
203 /*FAW*/33, /*WR*/14, /*RTP*/9, /*ZQCL*/300, /*ZQCS*/75,
204 }, {
205 // #define DDR3_1600J 5 // sg125E //DDR3-1600J (10-10-10) tCK=1.25ns
206 /*tCK*/ 1250,
207 /*tCL*/ 10, /*WCL*/8, /*RCD*/10, /*RAS*/28, /*RP*/10, /*RC*/38, /*RRD*/6,
208 /*FAW*/32, /*WR*/12, /*RTP*/8, /*ZQCL*/256, /*ZQCS*/64,
209 }, {
210 // #define DDR3_1600K 6 // sg125 //DDR3-1600K (11-11-11) tCK=1.25ns
211 /*tCK*/ 1250,
212 /*tCL*/ 11, /*WCL*/8, /*RCD*/11, /*RAS*/28, /*RP*/11, /*RC*/37, /*RRD*/6,
213 /*FAW*/32, /*WR*/12, /*RTP*/8, /*ZQCL*/256, /*ZQCS*/64,
214 }, {
215 // #define DDR3_1333H 7 // sg15E //DDR3-1333H (9-9-9) tCK=1.5ns
216 /*tCK*/ 1500,
217 /*tCL*/ 9, /*WCL*/7, /*RCD*/9, /*RAS*/24, /*RP*/9, /*RC*/33, /*RRD*/5,
218 /*FAW*/30, /*WR*/10, /*RTP*/5, /*ZQCL*/256, /*ZQCS*/64,
219 }, {
220 // #define DDR3_1333J 8 // sg15 //DDR3-1333J (10-10-10) tCK=1.5ns
221 /*tCK*/ 1500,
222 /*tCL*/ 10, /*WCL*/7, /*RCD*/10, /*RAS*/24, /*RP*/10, /*RC*/34, /*RRD*/5,
223 /*FAW*/30, /*WR*/10, /*RTP*/7, /*ZQCL*/256, /*ZQCS*/64,
224 }, {
225 // #define DDR3_1066F 9 // sg187E //DDR3-1066F (7-7-7) tCK=1.875ns
226 /*tCK*/ 1875,
227 /*tCL*/ 7, /*WCL*/6, /*RCD*/7, /*RAS*/20, /*RP*/7, /*RC*/27, /*RRD*/6,
228 /*FAW*/27, /*WR*/8, /*RTP*/6, /*ZQCL*/256, /*ZQCS*/64,
229 }, {
230 // #define DDR3_1066G 10 // sg187 //DDR3-1066G (8-8-8) tCK=1.875ns
231 /*tCK*/ 1875,
232 /*tCL*/ 8, /*WCL*/6, /*RCD*/8, /*RAS*/20, /*RP*/8, /*RC*/28, /*RRD*/6,
233 /*FAW*/27, /*WR*/8, /*RTP*/6, /*ZQCL*/256, /*ZQCS*/64,
234 }, {
235 // #define DDR3_800D 11 // sg25E //DDR3-800D (5-5-5) tCK=2.5ns
236 /*tCK*/ 2500,
237 /*tCL*/ 5, /*WCL*/5, /*RCD*/5, /*RAS*/15, /*RP*/5, /*RC*/20, /*RRD*/4,
238 /*FAW*/17, /*WR*/5, /*RTP*/3, /*ZQCL*/256, /*ZQCS*/64,
239 }, {
240 // #define DDR3_800E 12 // sg25 //DDR3-800E (6-6-6) tCK=2.5ns
241 /*tCK*/ 2500,
242 /*tCL*/ 6, /*WCL*/5, /*RCD*/6, /*RAS*/15, /*RP*/6, /*RC*/21, /*RRD*/4,
243 /*FAW*/20, /*WR*/6, /*RTP*/6, /*ZQCL*/256, /*ZQCS*/64,
244 },
245 {
246 // #define DDR3_266MPW 13 // sg25 //DDR3-800E (5-5-5) tCK=2.5ns
247 // /*tCL*/ 5, /*WCL*/7, /*RCD*/5, /*RAS*/9/*37.5/4*/, /*RP*/5, /*RC*/13, /*RRD*/4,
248 // /*FAW 50/4*/15, /*WR6*/5, /*RTP*/4, /*ZQCL*/256, /*ZQCS*/64,
249 // #define DDR3_250MPW 13 // sg25 //DDR3-800E (5-5-5) tCK=2.5ns
250 /*tCK*/ 2500,
251 /*tCL*/ 5, /*WCL*/7, /*RCD*/5, /*RAS*/9/*37.5/4*/, /*RP*/5, /*RC*/13, /*RRD*/4,
252 /*FAW 50/4*/15, /*WR6*/5, /*RTP*/4, /*ZQCL*/256, /*ZQCS*/64,
253
254 },
255 };
Get_DDR_Capacity(const MEM_CHIP_INFO * chip_info)256 uint32_t Get_DDR_Capacity(const MEM_CHIP_INFO *chip_info)
257 {
258 uint32_t n=0;
259 uint32_t capacity=0;
260
261 assert_param(chip_info);
262 n=(chip_info->Chip_type<_16Mbx16)?(chip_info->Chip_type):(chip_info->Chip_type-_16Mbx16);
263 capacity=(chip_info->Chip_type<_16Mbx16)?(CHIP_MIN_CAPACITY*(1<<n)*(chip_info->Chip_num+1)):(CHIP_MIN_CAPACITY*(1<<n)*(chip_info->Bus_width+1)/(BUS_WIDTH_16+1));
264 return capacity;
265
266
267 }
Calc_DDR_RFC(const MEM_CHIP_INFO * chip_info)268 uint32_t Calc_DDR_RFC(const MEM_CHIP_INFO *chip_info)
269 {
270 uint32_t capacity=0;
271 uint32_t tRFC=0;
272 assert_param(chip_info);
273
274
275 capacity=Get_DDR_Capacity(chip_info);
276 if (chip_info->mem_type==MEM_DDR2) {
277
278 switch(capacity){
279 case CHIP_CAPACITY_32MB:tRFC=75;break;
280 case CHIP_CAPACITY_64MB:tRFC=105;break;
281 case CHIP_CAPACITY_128MB:tRFC=128;break;
282 case CHIP_CAPACITY_256MB:tRFC=195;break;
283 case CHIP_CAPACITY_512MB:tRFC=328;break;
284 }
285 }
286 else{
287 switch(capacity){
288 case CHIP_CAPACITY_64MB:tRFC=90;break;
289 case CHIP_CAPACITY_128MB:tRFC=110;break;
290 case CHIP_CAPACITY_256MB:tRFC=160;break;
291 case CHIP_CAPACITY_512MB:tRFC=300;break;
292 case CHIP_CAPACITY_1024MB:tRFC=350;break;
293 }
294 }
295
296 return tRFC;
297
298
299 }
DDR_Cmd(const uint32_t cmd,const uint32_t param)300 static void DDR_Cmd(const uint32_t cmd ,const uint32_t param)
301 {
302 DDRC->CMD =((cmd)|(param));
303
304 }
DDR_Latency(const uint32_t cycle)305 static void DDR_Latency(const uint32_t cycle )
306 {
307 DDR_Cmd(SW_CMD_NOP,cycle);
308 }
DDR2_conf(const MEM_CHIP_INFO * chip_info,const void * ddr)309 static void DDR2_conf(const MEM_CHIP_INFO *chip_info ,const void *ddr)
310 {
311 uint32_t period=0;
312 const DDR2MEM *ptr = (const DDR2MEM *)ddr;
313 uint32_t tRFC=0;
314
315 assert_param(ddr);
316 tRFC=Calc_DDR_RFC(chip_info);
317 period = (1000 / (SYSTEM_CLOCK_FREQ / 1000000));
318 CFG_CTRL->DONE_b.CMD = 0x1;
319
320 DDRC->MODE_b.LANE = 1;
321 DDRC->MODE_b.B16 = 1;
322 DDRC->REF_b.TIME =( DDR_TREF/period);
323 DDRC->RP_b.RPA = 1;
324 DDRC->RFC_b.DI = (tRFC/period);
325 DDRC->PHUNG_b.MODE = 1;
326 DDRC->RD_SEL_b.PHY_SEL = 5;
327
328 DDRC->DQSEN0_b.DL = 2;
329 DDRC->DQSEN1_b.DL = 2;
330 DDRC->DQSEN2_b.DL = 2;
331 DDRC->DQSEN3_b.DL = 2;
332 DDRC->INTCTL_b.DONE = 1;
333 DDRC->INTCTL_b.ERR = 0;
334 DDRC->RDQ_b.L3 = DDRC->RDQ_b.L2 = DDRC->RDQ_b.L1 = DDRC->RDQ_b.L0 = 0x32;
335 DDRC->ITMDLY_b.I0 = DDRC->ITMDLY_b.IS0 = DDRC->ITMDLY_b.I1 = DDRC->ITMDLY_b.IS1 =
336 DDRC->ITMDLY_b.I2 = DDRC->ITMDLY_b.IS2 = DDRC->ITMDLY_b.I3 = DDRC->ITMDLY_b.IS3 = 3;
337
338
339 DDR_Latency((POWER_UP_NOP/period));
340 DDR_Cmd(SW_CMD_NOPCKE,(PRE_ALL_NOP/period));
341 DDR_Cmd(SW_CMD_PREA,NULL);
342 DDR_Latency(ptr->tRP);/*tRP*/
343 DDR_Cmd(SW_CMD_EMR2,NULL);
344 DDR_Latency(DDR2_TMRD);
345 DDR_Cmd(SW_CMD_EMR3,NULL);
346 DDR_Latency(DDR2_TMRD);
347 DDR_Cmd(SW_CMD_DLL_EN,NULL);
348 DDR_Latency(DDR2_TMRD);
349 DDR_Cmd(SW_CMD_DLL_RST,NULL);
350 DDR_Latency(DDR2_TMRD);
351 DDR_Cmd(SW_CMD_PREA,NULL);
352 DDR_Latency(ptr->tRP);
353 DDR_Cmd(SW_CMD_REF,NULL);
354 DDR_Latency((tRFC/period));/*tRFC*/
355 DDR_Cmd(SW_CMD_REF,NULL);
356 DDR_Latency((tRFC/period));
357 DDR_Cmd(SW_CMD_MR,(((ptr->tWR-1)<<MR_WR_OFFSET)|(ptr->tCL<<MR_CL_OFFSET)|MR_BURST_LEN_8));
358 DDR_Latency(POWER_UP_MIN_CK);
359 DDR_Cmd(SW_CMD_EMR1_TEST,NULL);
360 DDR_Latency(DDR2_TMRD);
361 }
362
DDR3_conf(const MEM_CHIP_INFO * chip_info,const void * ddr)363 static void DDR3_conf(const MEM_CHIP_INFO *chip_info ,const void *ddr)
364 {
365
366 uint32_t period = 0;
367 uint32_t tRFC = 0;
368 const DDR3MEM *ptr = (const DDR3MEM *)ddr;
369
370 tRFC = Calc_DDR_RFC(chip_info);
371 period = (1000 / (SYSTEM_CLOCK_FREQ / 1000000));
372
373 DDRC->MODE_b.LANE = 0x1;
374 DDRC->QUE_b.DEPTH=1;
375 DDRC->REF_b.TIME = (DDR_TREF / period);////// //2Gb periodic refresh interval 7.8us 7.8us/5ns
376 DDRC->REF_b.TRIG = 1;
377 DDRC->REF_b.THRD = 8;
378 DDRC->ZQCSR_b.EN = 1;
379 DDRC->ZQCSI = 128 * 1000000 / period;
380 DDRC->RP_b.RPA = 1;
381 DDRC->RFC_b.DI = (tRFC / period);
382
383 if (ptr->tCK == 2500) { // 200MHz
384 DDRC->RD_SEL_b.PHY_SEL = 5;
385 } else if (ptr->tCK == 3000) { // 333MHz
386 DDRC->RD_SEL_b.PHY_SEL = 6;
387 }
388
389 DDRC->PHUNG_b.MODE = 1;
390 DDRC->DQSEN0_b.DL = 2;
391 DDRC->DQSEN1_b.DL = 2;
392 DDRC->DQSEN2_b.DL = 2;
393 DDRC->DQSEN3_b.DL = 2;
394
395 // config MR#
396 DDR_Latency((POWER_UP_NOP/period));//200us nop
397 DDR_Cmd(SW_CMD_RSTH,NULL);// RESET H
398 DDR_Latency((RSTH_NOP/period));// 500us nop
399 DDR_Cmd(SW_CMD_NOPCKE,((tRFC+10)/period));// cke high 170/tck tck txpr max(5nck, trfc(min) + 10ns) 2Gb refresh time 160ns
400 DDR_Cmd(SW_CMD_EMR2,((ptr->tWCL-5)<<MR2_CWL_OFFSET)); //MR2
401 DDR_Latency(DDR3_TMRD);// tmrd 4nck
402 DDR_Cmd(SW_CMD_EMR3,NULL);// MR3
403 DDR_Latency(DDR3_TMRD); // tmrd
404 DDR_Cmd(SW_CMD_EMR1,MR1_RZQ_4); // MR1
405 DDR_Latency(DDR3_TMRD); // tmrd
406 DDR_Cmd(SW_CMD_MR,(MR_PPD_FAST|MR_DLL_YES|((ptr->tWR-1)<<MR_WR_OFFSET)|(CAL_DDR3_CL(ptr->tCL))));
407 // MR0
408 // A1 , A0 2'b0 fixed 8
409 // A2 CL 0
410 // A3 nibble sequential 0 Interleave 1
411 // A6,A5,A4 CL 101 CL =9
412 // A7 normal mode 0
413 // A8 DLL reset 1
414 // A11,A10,A9 wr=(twr/ck)=(15/3)=5 =001
415 // A12 DLL control for precharge PD fast exit 1
416 // MR0 =0xb50
417 DDR_Latency(MAX(DDR3_TMOD_CK,(DDR3_TMOD/period)));// tmod max (12nck,15ns)
418 DDR_Cmd(SW_CMD_ZQCL,NULL);// ZQCL starting ZQ calibration
419 DDR_Latency(MAX(DDR3_TZQINIT_CK,(DDR3_TZQINIT/period))); // tdllk 512nck (should be 500nck)
420 DDR_Latency(DDR3_TDLLK_CK); // tZQinit max(512nck,640ns)
421
422 }
423
DDR_Init(const MEM_CHIP_INFO * chip_info,const void * ddr)424 BOOL DDR_Init(const MEM_CHIP_INFO *chip_info, const void *ddr)
425 {
426 uint32_t tCL, tWR, tWCL, tWTR, tCK,mode;
427
428 assert_param(chip_info);
429 assert_param(ddr);
430 if((chip_info->Bus_width<BUS_WIDTH_MAX)
431 &&(chip_info->Chip_num<CHIP_NUM_MAX)
432 &&(chip_info->Chip_type< CHIP_TYPE_MAX))
433 {
434 if(chip_info->mem_type==MEM_DDR2)
435 {
436 mode=DDR2_MODE[chip_info->Bus_width][chip_info->Chip_num][chip_info->Chip_type];
437 }
438 else
439 {
440 mode=DDR3_MODE[chip_info->Bus_width][chip_info->Chip_num][chip_info->Chip_type];
441 }
442 if(mode==0xff)
443 {
444 return FALSE;
445 }
446
447
448 }
449 else
450 {
451 return FALSE;
452 }
453
454
455 PDPROT->LOCK_b.EN = 0;
456 do {
457 CFG_CTRL->PDLLSTR_b.C2R1D = 0; // rst dll_c2r1
458 udelay(10);
459 CFG_CTRL->PDLLSTR_b.C2R1D = 1; // releset rst
460 udelay(10);
461 } while ((PDLOCK->GCLK & 0x40) != 0x40);
462 PDPROT->LOCK_b.EN = 1;
463
464 DDRC->MODE_b.MODE = mode;
465
466 if (chip_info->mem_type==MEM_DDR2) {
467 const DDR2MEM *ptr = (const DDR2MEM *)ddr;
468 DDRC->RL_b.VAL = ptr->tCL;
469 DDRC->RCD_b.DI = ptr->tRCD;
470 DDRC->RP_b.DI = ptr->tRP;
471 DDRC->RC_b.DI = ptr->tRC;
472 DDRC->RAS_b.DI = ptr->tRAS;
473 tWR = ptr->tWR;
474 tWTR = ptr->tWTR;
475 DDRC->RRD_b.DI = ptr->tRRD;
476 DDRC->RTP_b.DI = ptr->tRTP;
477 DDRC->FAW_b.DI = ptr->tFAW;
478 DDR2_conf(chip_info,ptr);
479 } else {
480 const DDR3MEM *ptr = (const DDR3MEM *)ddr;
481 DDRC->RL_b.VAL = ptr->tCL;
482 tWCL = ptr->tWCL;
483 DDRC->RCD_b.DI = ptr->tRCD;
484 DDRC->RAS_b.DI = ptr->tRAS;
485 DDRC->RP_b.DI = ptr->tRP;
486 DDRC->RC_b.DI = ptr->tRC;
487 DDRC->RRD_b.DI = ptr->tRRD;
488 DDRC->FAW_b.DI = ptr->tFAW;
489 tWR = ptr->tWR;
490 tCK = ptr->tCK;
491 DDRC->RTP_b.DI = ptr->tRTP;
492 DDRC->ZQCL_b.DI = ptr->tZQoper;
493 DDRC->ZQCS_b.DI = ptr->tZQCS;
494 DDR3_conf(chip_info,ptr);
495 }
496
497 tCL = DDRC->RL_b.VAL;
498
499 DDRC->WTR_b.DI = (DDRC->MODE_b.MODE & 0x20) ?
500 (tWCL + tWTR + (DDRC->BURST_b.LEN ? 2 : 4)) :
501 ((tCK * 4) > 7500) ? 18 : (tCK * 4 + 7500 - 1) / 7500; //4
502
503 DDRC->CCD_b.DI = (DDRC->MODE_b.MODE & 0x20) ? (DDRC->BURST_b.LEN ? 2 : 4) : 4;
504 DDRC->RTW_b.DI = (DDRC->MODE_b.MODE & 0x20) ? (DDRC->BURST_b.LEN ? 4 : 6) : (tCL + DDRC->CCD_b.DI - tWCL + (DDRC->BURST_b.LEN ? 0 : 2));
505 DDRC->WTP_b.DI = (DDRC->MODE_b.MODE & 0x20) ? (tCL + tWR + (DDRC->BURST_b.LEN ? 1 : 3)) : (tWCL + tWR + (DDRC->BURST_b.LEN ? 2 : 4));
506 DDRC->WL_b.VAL = (DDRC->MODE_b.MODE & 0x20) ? (MAX(tCL, 3) - 3) : (tWCL - 2);
507 DDRC->ODTH_b.DL = (DDRC->MODE_b.MODE & 0x20) ? (MAX(tCL, 4) - 4) : 0;
508 if (tCK == 2500) { // 200MHz
509 DDRC->ODTL_b.DL = (DDRC->MODE_b.MODE & 0x20) ? (DDRC->BURST_b.LEN ? (tCL - 1) : (tCL + 1)) : (DDRC->BURST_b.LEN ? 4 : 6);
510 } else if (tCK == 3000) { // 333MHz
511 DDRC->ODTL_b.DL = 0x1f;
512 }
513
514
515 // DEBUG INFO HERE
516 DDRC->CTRL_b.STR = 1;
517
518 while (0 == DDRC->STA_b.EMPTY);
519 while(0 == DDRC->INTRAW_b.DONE);
520 DDRC->CTRL_b.STR = DDRC->CTRL_b.TO = 0;
521
522 return TRUE;
523 }
524