1 /* 2 * Copyright (c) 2006-2024 RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2024-09-23 LZerro first version 9 */ 10 11 #ifndef __DRV_ETH_H__ 12 #define __DRV_ETH_H__ 13 14 #include <rtthread.h> 15 #include <rthw.h> 16 #include <rtdevice.h> 17 #include <board.h> 18 #include "eth_config.h" 19 20 /* The PHY basic control register */ 21 #define PHY_BASIC_CONTROL_REG 0x00U 22 #define PHY_RESET_MASK (1<<15) 23 #define PHY_AUTO_NEGOTIATION_MASK (1<<12) 24 25 /* The PHY basic status register */ 26 #define PHY_BASIC_STATUS_REG 0x01U 27 #define PHY_LINKED_STATUS_MASK (1<<2) 28 #define PHY_AUTONEGO_COMPLETE_MASK (1<<5) 29 30 /* The PHY ID one register */ 31 #define PHY_ID1_REG 0x02U 32 /* The PHY ID two register */ 33 #define PHY_ID2_REG 0x03U 34 /* The PHY auto-negotiate advertise register */ 35 #define PHY_AUTONEG_ADVERTISE_REG 0x04U 36 37 /** PHY duplex mode */ 38 typedef enum 39 { 40 CY_ECM_DUPLEX_HALF, /**< Half duplex */ 41 CY_ECM_DUPLEX_FULL, /**< Full duplex */ 42 CY_ECM_DUPLEX_AUTO /**< Both half/full duplex */ 43 } cy_ecm_duplex_t; 44 45 /** PHY speed */ 46 typedef enum 47 { 48 CY_ECM_PHY_SPEED_10M, /**< 10 Mbps */ 49 CY_ECM_PHY_SPEED_100M, /**< 100 Mbps */ 50 CY_ECM_PHY_SPEED_1000M, /**< 1000 Mbps */ 51 CY_ECM_PHY_SPEED_AUTO /**< All 10/100/1000 Mbps */ 52 } cy_ecm_phy_speed_t; 53 54 /** Standard interface type */ 55 typedef enum 56 { 57 CY_ECM_SPEED_TYPE_MII, /**< Media-Independent Interface (MII) */ 58 CY_ECM_SPEED_TYPE_GMII, /**< Gigabit Media-Independent Interface (GMII) */ 59 CY_ECM_SPEED_TYPE_RGMII, /**< Reduced Gigabit Media-Independent Interface (RGMII) */ 60 CY_ECM_SPEED_TYPE_RMII /**< Reduced Media-Independent Interface (RMII) */ 61 } cy_ecm_speed_type_t; 62 63 typedef struct 64 { 65 cy_ecm_speed_type_t interface_speed_type; /**< Standard interface to be used for data transfer */ 66 cy_ecm_phy_speed_t phy_speed; /**< Physical transfer speed */ 67 cy_ecm_duplex_t mode; /**< Transfer mode */ 68 } cy_ecm_phy_config_t; 69 70 extern int eth_index_internal; 71 72 73 #define ETH_INTERFACE_TYPE ETH1 74 75 /* After hardware initialization, max wait time to get the physical link up */ 76 #define MAX_WAIT_ETHERNET_PHY_STATUS (10000) 77 78 #define REGISTER_ADDRESS_PHY_REG_BMCR PHYREG_00_BMCR /* BMCR register (0x0000) to read the speed and duplex mode */ 79 #define REGISTER_PHY_REG_DUPLEX_MASK PHYBMCR_FULL_DUPLEX_Msk /* Bit 8 of BMCR register to read the duplex mode */ 80 #define REGISTER_PHY_REG_SPEED_MASK (0x2040) /* Bit 6, 13: BMCR register to read the speed */ 81 #define REGISTER_PHY_REG_SPEED_MASK_10M (0x0000) /* Bit 6, 13: Both are set to 0 for 10M speed */ 82 #define REGISTER_PHY_REG_SPEED_MASK_100M (0x2000) /* Bit 6, 13: Set to 0 and 1 respectively for 100M speed */ 83 #define REGISTER_PHY_REG_SPEED_MASK_1000M (0x0040) /* Bit 6, 13: Set to 1 and 0 respectively for 1000M speed */ 84 85 #endif /* __DRV_ETH_H__ */ 86 87 88 89 90 91 92 93