1#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
2; The first line specifies a preprocessor command that the linker invokes
3; to pass a scatter file through a C preprocessor.
4
5;*******************************************************************************
6;* \file cy8c6xxa_cm4_dual.sct
7;* \version 2.91
8;*
9;* Linker file for the ARMCC.
10;*
11;* The main purpose of the linker script is to describe how the sections in the
12;* input files should be mapped into the output file, and to control the memory
13;* layout of the output file.
14;*
15;* \note The entry point location is fixed and starts at 0x10000000. The valid
16;* application image should be placed there.
17;*
18;* \note The linker files included with the PDL template projects must be
19;* generic and handle all common use cases. Your project may not use every
20;* section defined in the linker files. In that case you may see the warnings
21;* during the build process: L6314W (no section matches pattern) and/or L6329W
22;* (pattern only matches removed unused sections). In your project, you can
23;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
24;* the linker, simply comment out or remove the relevant code in the linker
25;* file.
26;*
27;*******************************************************************************
28;* \copyright
29;* Copyright 2016-2021 Cypress Semiconductor Corporation
30;* SPDX-License-Identifier: Apache-2.0
31;*
32;* Licensed under the Apache License, Version 2.0 (the "License");
33;* you may not use this file except in compliance with the License.
34;* You may obtain a copy of the License at
35;*
36;*     http://www.apache.org/licenses/LICENSE-2.0
37;*
38;* Unless required by applicable law or agreed to in writing, software
39;* distributed under the License is distributed on an "AS IS" BASIS,
40;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
41;* See the License for the specific language governing permissions and
42;* limitations under the License.
43;******************************************************************************/
44
45; The defines below describe the location and size of blocks of memory in the target.
46; Use these defines to specify the memory regions available for allocation.
47
48; The following defines control RAM and flash memory allocation for the CM4 core.
49; You can change the memory allocation by editing RAM and Flash defines.
50; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
51; Using this memory region for other purposes will lead to unexpected behavior.
52; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
53; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'.
54; RAM
55#define RAM_START               0x08002000
56#define RAM_SIZE                0x000FD800
57; Flash
58#define FLASH_START             0x10000000
59#define FLASH_SIZE              0x00200000
60
61; The size of the stack section at the end of CM4 SRAM
62#define STACK_SIZE              0x00001000
63
64; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
65; More about CM0+ prebuilt images, see here:
66; https://github.com/cypresssemiconductorco/psoc6cm0p
67; The size of the Cortex-M0+ application flash image
68#define FLASH_CM0P_SIZE         0x2000
69
70; The following defines describe a 32K flash region used for EEPROM emulation.
71; This region can also be used as the general purpose flash.
72; You can assign sections to this memory region for only one of the cores.
73; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
74; Therefore, repurposing this memory region will prevent such middleware from operation.
75#define EM_EEPROM_START         0x14000000
76#define EM_EEPROM_SIZE          0x8000
77
78; The following defines describe device specific memory regions and must not be changed.
79; Supervisory flash: User data
80#define SFLASH_USER_DATA_START  0x16000800
81#define SFLASH_USER_DATA_SIZE   0x00000800
82
83; Supervisory flash: Normal Access Restrictions (NAR)
84#define SFLASH_NAR_START        0x16001A00
85#define SFLASH_NAR_SIZE         0x00000200
86
87; Supervisory flash: Public Key
88#define SFLASH_PUBLIC_KEY_START 0x16005A00
89#define SFLASH_PUBLIC_KEY_SIZE  0x00000C00
90
91; Supervisory flash: Table of Content # 2
92#define SFLASH_TOC_2_START      0x16007C00
93#define SFLASH_TOC_2_SIZE       0x00000200
94
95; Supervisory flash: Table of Content # 2 Copy
96#define SFLASH_RTOC_2_START     0x16007E00
97#define SFLASH_RTOC_2_SIZE      0x00000200
98
99; External memory
100#define XIP_START               0x18000000
101#define XIP_SIZE                0x08000000
102
103; eFuse
104#define EFUSE_START             0x90700000
105#define EFUSE_SIZE              0x100000
106
107
108; Cortex-M0+ application flash image area
109LR_IROM FLASH_START FLASH_CM0P_SIZE
110{
111    .cy_m0p_image +0 FLASH_CM0P_SIZE
112    {
113        * (.cy_m0p_image)
114    }
115}
116
117; Cortex-M4 application flash area
118LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE)
119{
120    ER_FLASH_VECTORS +0
121    {
122        * (RESET, +FIRST)
123    }
124
125    ER_FLASH_CODE +0 FIXED
126    {
127        * (InRoot$$Sections)
128        * (+RO)
129    }
130
131    ER_RAM_VECTORS RAM_START UNINIT
132    {
133        * (RESET_RAM, +FIRST)
134    }
135
136    RW_RAM_DATA +0
137    {
138        * (.cy_ramfunc)
139        * (+RW, +ZI)
140    }
141
142    ; Place variables in the section that should not be initialized during the
143    ; device startup.
144    RW_IRAM1 +0 UNINIT
145    {
146        * (.noinit)
147    }
148
149    ; Application heap area (HEAP)
150    ARM_LIB_HEAP  +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
151    {
152    }
153
154    ; Stack region growing down
155    ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
156    {
157    }
158
159    ; Used for the digital signature of the secure application and the
160    ; Bootloader SDK application. The size of the section depends on the required
161    ; data size.
162    .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
163    {
164        * (.cy_app_signature)
165    }
166}
167
168
169; Emulated EEPROM Flash area
170LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
171{
172    .cy_em_eeprom +0
173    {
174        * (.cy_em_eeprom)
175    }
176}
177
178; Supervisory flash: User data
179LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
180{
181    .cy_sflash_user_data +0
182    {
183        * (.cy_sflash_user_data)
184    }
185}
186
187; Supervisory flash: Normal Access Restrictions (NAR)
188LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
189{
190    .cy_sflash_nar +0
191    {
192        * (.cy_sflash_nar)
193    }
194}
195
196; Supervisory flash: Public Key
197LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
198{
199    .cy_sflash_public_key +0
200    {
201        * (.cy_sflash_public_key)
202    }
203}
204
205; Supervisory flash: Table of Content # 2
206LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
207{
208    .cy_toc_part2 +0
209    {
210        * (.cy_toc_part2)
211    }
212}
213
214; Supervisory flash: Table of Content # 2 Copy
215LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
216{
217    .cy_rtoc_part2 +0
218    {
219        * (.cy_rtoc_part2)
220    }
221}
222
223
224; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
225LR_EROM XIP_START XIP_SIZE
226{
227    cy_xip +0
228    {
229        * (.cy_xip)
230    }
231}
232
233
234; eFuse
235LR_EFUSE EFUSE_START EFUSE_SIZE
236{
237    .cy_efuse +0
238    {
239        * (.cy_efuse)
240    }
241}
242
243
244; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
245CYMETA 0x90500000
246{
247    .cymeta +0 { * (.cymeta) }
248}
249
250/* The following symbols used by the cymcuelftool. */
251/* Flash */
252#define __cy_memory_0_start 0x10000000
253#define __cy_memory_0_length  0x00200000
254#define __cy_memory_0_row_size 0x200
255
256/* Emulated EEPROM Flash area */
257#define __cy_memory_1_start    0x14000000
258#define __cy_memory_1_length   0x8000
259#define __cy_memory_1_row_size 0x200
260
261/* Supervisory Flash */
262#define __cy_memory_2_start    0x16000000
263#define __cy_memory_2_length   0x8000
264#define __cy_memory_2_row_size 0x200
265
266/* XIP */
267#define __cy_memory_3_start    0x18000000
268#define __cy_memory_3_length   0x08000000
269#define __cy_memory_3_row_size 0x200
270
271/* eFuse */
272#define __cy_memory_4_start    0x90700000
273#define __cy_memory_4_length   0x100000
274#define __cy_memory_4_row_size 1
275
276
277/* [] END OF FILE */
278