1# CY8CKIT-062S2-43012 BSP Release Notes
2The CY8CKIT-062S2-43012 PSoC™ 6S2 Wi-Fi BT Pioneer Kit is a low-cost hardware platform that enables design and debug of PSoC™ 6 MCUs. It comes with a Murata 1LV Module (CYW43012 Wi-Fi + Bluetooth Combo Chip), industry-leading CAPSENSE™ for touch buttons and slider, on-board debugger/programmer with KitProg3, microSD card interface, 512-Mb Quad-SPI NOR flash, PDM-PCM microphone interface.
3
4NOTE: BSPs are versioned by family. This means that version 1.2.0 of any BSP in a family (eg: PSoC™ 6) will have the same software maturity level. However, not all updates are necessarily applicable for each BSP in the family so not all version numbers will exist for each board. Additionally, new BSPs may not start at version 1.0.0. In the event of adding a common feature across all BSPs, the libraries are assigned the same version number. For example if BSP_A is at v1.3.0 and BSP_B is at v1.2.0, the event will trigger a version update to v1.4.0 for both BSP_A and BSP_B. This allows the common feature to be tracked in a consistent way.
5
6### What's Included?
7The CY8CKIT-062S2-43012 library includes the following:
8* BSP specific makefile to configure the build process for the board
9* cybsp.c/h files to initialize the board and any system peripherals
10* cybsp_types.h file describing basic board setup
11* CM4 Linker script & startup code for GCC, IAR, and ARM toolchains
12* CM0+ Linker script & startup code for GCC, IAR, and ARM toolchains
13* Configurator design files (and generated code) to setup board specific peripherals
14* .lib file references for all dependent libraries
15* API documentation
16
17### What Changed?
18#### v4.1.0
19* Add macro `CYBSP_USER_BTN_DRIVE` indicating the drive mode that should be used for user buttons
20* PSoC 64 boards: Fix cybsp_init not recognizing that a prebuilt CM0+ image is in use when using TFM.
21#### v4.0.0
22Note: This revision is only compatible with ModusToolbox Tools 3.0 and newer.
23* Removed default dependency on CAPSENSE™ middleware. The library manager can be used to add this dependency if desired.
24* Updated recipe-make, core-make, and PDL to new major versions
25* Regenerated code with Configurators from ModusToolbox™ v3.0.0
26* Renamed top level board makefile to bsp.mk
27* Removed version.xml file in favor of new props.json
28#### v3.1.0
29* Added optional macro CYBSP_CUSTOM_SYSCLK_PM_CALLBACK to allow overriding default clock power management behavior.
30* Enable AIROC™ BLE stack for MCUs with an integrated BLE radio
31#### v3.0.0
32* Updated to HAL dependency to v2.0.0
33* Updated CAPSENSE™ dependency to v3.0.0
34* Regenerated code with Configurators from ModusToolbox™ v2.4.0
35#### v2.3.0
36* Add new connectivity components for easier board customization
37* Simplify BT configuration settings for boards that support it
38* Minor branding updates
39#### v2.2.0
40* Updated PSoC™ 64 linker sections to match secure policy settings
41* Minor documentation updates
42#### v2.1.0
43* Added component CAT1 to all boards
44* Added new components for connectivity chips
45* Added BT configuration settings for boards that support it
46* Minor documentation updates
47#### v2.0.1
48* Minor update to better handle when to include the SCL library in the build
49#### v2.0.0
50* Updated design files and GeneratedSource with ModusToolbox™ 2.2 release
51* Migrated pin definitions into design.modus file
52* Updated clock frequencies to 100 MHz (fast) / 50 MHz (slow)
53* Updated MPNs on some boards to non-obsolete parts
54* Switched psoc6pdl dependency to new mtb-pdl
55* Switched psoc6hal dependency to new mtb-hal
56* Switched psoc6make dependency to new core-make & recipe-make-cat1a
57NOTE: This version requires ModusToolbox™ tools 2.2 or later. This version is not backwards compatible with 1.X versions. Additional manual steps must be taken to successfully update a design using a 1.x version of the BSP to this version.
58#### v1.3.0
59* Minor update for documentation & branding
60* Updated design files to use latest personality files
61* Initialize VDDA voltage if set in configurator
62NOTE: This requires psoc6hal 1.3.0 or later
63#### v1.2.1
64* Added 43012/4343W/43438 component to appropriate BSPs
65* Added multi-image policy for secure (064) BSPs
66#### v1.2.0
67* Standardize version numbering for all boards in a family
68* Moved UDB SDIO implementation into its own library udb-sdio-whd library
69* Added call to setup HAL SysPM driver (requires HAL 1.2.0 or later)
70* Updated documentation
71NOTE: This requires psoc6hal 1.2.0 or later
72#### v1.1.0
73* Updated linker scripts and startup code for the CM0+ and CM4 cores. The files are now in core specific directories.
74* Minor updates to avoid potential warnings on some toolchains
75#### v1.0.1
76* Added pin references for the board's J2 Header (for appropriate boards)
77#### v1.0.0
78* Initial release
79
80### Supported Software and Tools
81This version of the CY8CKIT-062S2-43012 BSP was validated for compatibility with the following Software and Tools:
82
83| Software and Tools                        | Version |
84| :---                                      | :----:  |
85| ModusToolbox™ Software Environment        | 3.0.0   |
86| GCC Compiler                              | 10.3.1  |
87| IAR Compiler                              | 9.30.1  |
88| ARM Compiler                              | 6.16    |
89
90Minimum required ModusToolbox™ Software Environment: v3.0.0
91
92### More information
93* [CY8CKIT-062S2-43012 BSP API Reference Manual][api]
94* [CY8CKIT-062S2-43012 Documentation](http://www.cypress.com/CY8CKIT-062S2-43012)
95* [Cypress Semiconductor, an Infineon Technologies Company](http://www.cypress.com)
96* [Infineon GitHub](https://github.com/infineon)
97* [ModusToolbox™](https://www.cypress.com/products/modustoolbox-software-environment)
98
99[api]: https://infineon.github.io/TARGET_CY8CKIT-062S2-43012/html/modules.html
100
101---
102© Cypress Semiconductor Corporation (an Infineon company) or an affiliate of Cypress Semiconductor Corporation, 2019-2022.