1/***************************************************************************//**
2* \file cy8c6xx4_cm4_dual.ld
3* \version 2.91
4*
5* Linker file for the GNU C compiler.
6*
7* The main purpose of the linker script is to describe how the sections in the
8* input files should be mapped into the output file, and to control the memory
9* layout of the output file.
10*
11* \note The entry point location is fixed and starts at 0x10000000. The valid
12* application image should be placed there.
13*
14* \note The linker files included with the PDL template projects must be generic
15* and handle all common use cases. Your project may not use every section
16* defined in the linker files. In that case you may see warnings during the
17* build process. In your project, you can simply comment out or remove the
18* relevant code in the linker file.
19*
20********************************************************************************
21* \copyright
22* Copyright 2016-2021 Cypress Semiconductor Corporation
23* SPDX-License-Identifier: Apache-2.0
24*
25* Licensed under the Apache License, Version 2.0 (the "License");
26* you may not use this file except in compliance with the License.
27* You may obtain a copy of the License at
28*
29*     http://www.apache.org/licenses/LICENSE-2.0
30*
31* Unless required by applicable law or agreed to in writing, software
32* distributed under the License is distributed on an "AS IS" BASIS,
33* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
34* See the License for the specific language governing permissions and
35* limitations under the License.
36*******************************************************************************/
37
38OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
39SEARCH_DIR(.)
40GROUP(-lgcc -lc -lnosys)
41ENTRY(Reset_Handler)
42
43/* The size of the stack section at the end of CM4 SRAM */
44STACK_SIZE = 0x1000;
45
46/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
47* More about CM0+ prebuilt images, see here:
48* https://github.com/cypresssemiconductorco/psoc6cm0p
49*/
50/* The size of the Cortex-M0+ application image at the start of FLASH */
51FLASH_CM0P_SIZE  = 0x2000;
52
53/* Force symbol to be entered in the output file as an undefined symbol. Doing
54* this may, for example, trigger linking of additional modules from standard
55* libraries. You may list several symbols for each EXTERN, and you may use
56* EXTERN multiple times. This command has the same effect as the -u command-line
57* option.
58*/
59EXTERN(Reset_Handler)
60
61/* The MEMORY section below describes the location and size of blocks of memory in the target.
62* Use this section to specify the memory regions available for allocation.
63*/
64MEMORY
65{
66    /* The ram and flash regions control RAM and flash memory allocation for the CM4 core.
67     * You can change the memory allocation by editing the 'ram' and 'flash' regions.
68     * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
69     * Using this memory region for other purposes will lead to unexpected behavior.
70     * Your changes must be aligned with the corresponding memory regions for CM0+ core in 'xx_cm0plus.ld',
71     * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.ld'.
72     */
73    ram               (rwx)   : ORIGIN = 0x08002000, LENGTH = 0x1D800
74    flash             (rx)    : ORIGIN = 0x10000000, LENGTH = 0x40000
75
76
77    /* The following regions define device specific memory regions and must not be changed. */
78    sflash_user_data  (rx)    : ORIGIN = 0x16000800, LENGTH = 0x800        /* Supervisory flash: User data */
79    sflash_nar        (rx)    : ORIGIN = 0x16001A00, LENGTH = 0x200        /* Supervisory flash: Normal Access Restrictions (NAR) */
80    sflash_public_key (rx)    : ORIGIN = 0x16005A00, LENGTH = 0xC00        /* Supervisory flash: Public Key */
81    sflash_toc_2      (rx)    : ORIGIN = 0x16007C00, LENGTH = 0x200        /* Supervisory flash: Table of Content # 2 */
82    sflash_rtoc_2     (rx)    : ORIGIN = 0x16007E00, LENGTH = 0x200        /* Supervisory flash: Table of Content # 2 Copy */
83    xip               (rx)    : ORIGIN = 0x18000000, LENGTH = 0x8000000    /* 128 MB */
84    efuse             (r)     : ORIGIN = 0x90700000, LENGTH = 0x100000     /*   1 MB */
85}
86
87/* Library configurations */
88GROUP(libgcc.a libc.a libm.a libnosys.a)
89
90/* Linker script to place sections and symbol values. Should be used together
91 * with other linker script that defines memory regions FLASH and RAM.
92 * It references following symbols, which must be defined in code:
93 *   Reset_Handler : Entry of reset handler
94 *
95 * It defines following symbols, which code can use without definition:
96 *   __exidx_start
97 *   __exidx_end
98 *   __copy_table_start__
99 *   __copy_table_end__
100 *   __zero_table_start__
101 *   __zero_table_end__
102 *   __etext
103 *   __data_start__
104 *   __preinit_array_start
105 *   __preinit_array_end
106 *   __init_array_start
107 *   __init_array_end
108 *   __fini_array_start
109 *   __fini_array_end
110 *   __data_end__
111 *   __bss_start__
112 *   __bss_end__
113 *   __end__
114 *   end
115 *   __HeapLimit
116 *   __StackLimit
117 *   __StackTop
118 *   __stack
119 *   __Vectors_End
120 *   __Vectors_Size
121 */
122
123
124SECTIONS
125{
126     /* Cortex-M0+ application flash image area */
127    .cy_m0p_image ORIGIN(flash) :
128    {
129        . = ALIGN(4);
130        __cy_m0p_code_start = . ;
131        KEEP(*(.cy_m0p_image))
132        __cy_m0p_code_end = . ;
133    } > flash
134
135    /* Check if .cy_m0p_image size exceeds FLASH_CM0P_SIZE */
136    ASSERT(__cy_m0p_code_end <= ORIGIN(flash) + FLASH_CM0P_SIZE, "CM0+ flash image overflows with CM4, increase FLASH_CM0P_SIZE")
137
138    /* Cortex-M4 application flash area */
139    .text ORIGIN(flash) + FLASH_CM0P_SIZE :
140    {
141        . = ALIGN(4);
142        __Vectors = . ;
143        KEEP(*(.vectors))
144        . = ALIGN(4);
145        __Vectors_End = .;
146        __Vectors_Size = __Vectors_End - __Vectors;
147        __end__ = .;
148
149        . = ALIGN(4);
150        *(.text*)
151
152        KEEP(*(.init))
153        KEEP(*(.fini))
154
155        /* .ctors */
156        *crtbegin.o(.ctors)
157        *crtbegin?.o(.ctors)
158        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
159        *(SORT(.ctors.*))
160        *(.ctors)
161
162        /* .dtors */
163        *crtbegin.o(.dtors)
164        *crtbegin?.o(.dtors)
165        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
166        *(SORT(.dtors.*))
167        *(.dtors)
168
169        /* Read-only code (constants). */
170        *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
171
172        KEEP(*(.eh_frame*))
173
174       /* section information for utest */
175        . = ALIGN(4);
176        __rt_utest_tc_tab_start = .;
177        KEEP(*(UtestTcTab))
178        __rt_utest_tc_tab_end = .;
179
180        /* section information for finsh shell */
181        . = ALIGN(4);
182        __fsymtab_start = .;
183        KEEP(*(FSymTab))
184        __fsymtab_end = .;
185        . = ALIGN(4);
186        __vsymtab_start = .;
187        KEEP(*(VSymTab))
188        __vsymtab_end = .;
189        . = ALIGN(4);
190
191        /* section information for modules */
192        . = ALIGN(4);
193        __rtmsymtab_start = .;
194        KEEP(*(RTMSymTab))
195        __rtmsymtab_end = .;
196
197        /* section information for initialization */
198        . = ALIGN(4);
199        __rt_init_start = .;
200        KEEP(*(SORT(.rti_fn*)))
201        __rt_init_end = .;
202    } > flash
203
204
205    .ARM.extab :
206    {
207        *(.ARM.extab* .gnu.linkonce.armextab.*)
208    } > flash
209
210    __exidx_start = .;
211
212    .ARM.exidx :
213    {
214        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
215    } > flash
216    __exidx_end = .;
217
218
219    /* To copy multiple ROM to RAM sections,
220     * uncomment .copy.table section and,
221     * define __STARTUP_COPY_MULTIPLE in startup_psoc6_04_cm4.S */
222    .copy.table :
223    {
224        . = ALIGN(4);
225        __copy_table_start__ = .;
226
227        /* Copy interrupt vectors from flash to RAM */
228        LONG (__Vectors)                                    /* From */
229        LONG (__ram_vectors_start__)                        /* To   */
230        LONG (__Vectors_End - __Vectors)                    /* Size */
231
232        /* Copy data section to RAM */
233        LONG (__etext)                                      /* From */
234        LONG (__data_start__)                               /* To   */
235        LONG (__data_end__ - __data_start__)                /* Size */
236
237        __copy_table_end__ = .;
238    } > flash
239
240
241    /* To clear multiple BSS sections,
242     * uncomment .zero.table section and,
243     * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_04_cm4.S */
244    .zero.table :
245    {
246        . = ALIGN(4);
247        __zero_table_start__ = .;
248        LONG (__bss_start__)
249        LONG (__bss_end__ - __bss_start__)
250        __zero_table_end__ = .;
251    } > flash
252
253    __etext =  . ;
254
255
256    .ramVectors (NOLOAD) : ALIGN(8)
257    {
258        __ram_vectors_start__ = .;
259        KEEP(*(.ram_vectors))
260        __ram_vectors_end__   = .;
261    } > ram
262
263
264    .data __ram_vectors_end__ :
265    {
266        . = ALIGN(4);
267        __data_start__ = .;
268
269        *(vtable)
270        *(.data*)
271
272        . = ALIGN(4);
273        /* preinit data */
274        PROVIDE_HIDDEN (__preinit_array_start = .);
275        KEEP(*(.preinit_array))
276        PROVIDE_HIDDEN (__preinit_array_end = .);
277
278        . = ALIGN(4);
279        /* init data */
280        PROVIDE_HIDDEN (__init_array_start = .);
281        KEEP(*(SORT(.init_array.*)))
282        KEEP(*(.init_array))
283        PROVIDE_HIDDEN (__init_array_end = .);
284
285        . = ALIGN(4);
286        /* finit data */
287        PROVIDE_HIDDEN (__fini_array_start = .);
288        KEEP(*(SORT(.fini_array.*)))
289        KEEP(*(.fini_array))
290        PROVIDE_HIDDEN (__fini_array_end = .);
291
292        KEEP(*(.jcr*))
293        . = ALIGN(4);
294
295        KEEP(*(.cy_ramfunc*))
296        . = ALIGN(4);
297
298        __data_end__ = .;
299
300    } > ram AT>flash
301
302
303    /* Place variables in the section that should not be initialized during the
304    *  device startup.
305    */
306    .noinit (NOLOAD) : ALIGN(8)
307    {
308      KEEP(*(.noinit))
309    } > ram
310
311
312    /* The uninitialized global or static variables are placed in this section.
313    *
314    * The NOLOAD attribute tells linker that .bss section does not consume
315    * any space in the image. The NOLOAD attribute changes the .bss type to
316    * NOBITS, and that  makes linker to A) not allocate section in memory, and
317    * A) put information to clear the section with all zeros during application
318    * loading.
319    *
320    * Without the NOLOAD attribute, the .bss section might get PROGBITS type.
321    * This  makes linker to A) allocate zeroed section in memory, and B) copy
322    * this section to RAM during application loading.
323    */
324    .bss (NOLOAD):
325    {
326        . = ALIGN(4);
327        __bss_start__ = .;
328        *(.bss*)
329        *(COMMON)
330        . = ALIGN(4);
331        __bss_end__ = .;
332    } > ram
333
334
335    .heap (NOLOAD):
336    {
337        __HeapBase = .;
338        __end__ = .;
339        end = __end__;
340        KEEP(*(.heap*))
341        . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE;
342        __HeapLimit = .;
343    } > ram
344
345
346    /* .stack_dummy section doesn't contains any symbols. It is only
347     * used for linker to calculate size of stack sections, and assign
348     * values to stack symbols later */
349    .stack_dummy (NOLOAD):
350    {
351        KEEP(*(.stack*))
352    } > ram
353
354
355    /* Set stack top to end of RAM, and stack limit move down by
356     * size of stack_dummy section */
357    __StackTop = ORIGIN(ram) + LENGTH(ram);
358    __StackLimit = __StackTop - SIZEOF(.stack_dummy);
359    PROVIDE(__stack = __StackTop);
360
361    /* Check if data + heap + stack exceeds RAM limit */
362    ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
363
364
365    /* Used for the digital signature of the secure application and the Bootloader SDK application.
366    * The size of the section depends on the required data size. */
367    .cy_app_signature ORIGIN(flash) + LENGTH(flash) - 256 :
368    {
369        KEEP(*(.cy_app_signature))
370    } > flash
371
372
373
374
375    /* Supervisory Flash: User data */
376    .cy_sflash_user_data :
377    {
378        KEEP(*(.cy_sflash_user_data))
379    } > sflash_user_data
380
381
382    /* Supervisory Flash: Normal Access Restrictions (NAR) */
383    .cy_sflash_nar :
384    {
385        KEEP(*(.cy_sflash_nar))
386    } > sflash_nar
387
388
389    /* Supervisory Flash: Public Key */
390    .cy_sflash_public_key :
391    {
392        KEEP(*(.cy_sflash_public_key))
393    } > sflash_public_key
394
395
396    /* Supervisory Flash: Table of Content # 2 */
397    .cy_toc_part2 :
398    {
399        KEEP(*(.cy_toc_part2))
400    } > sflash_toc_2
401
402
403    /* Supervisory Flash: Table of Content # 2 Copy */
404    .cy_rtoc_part2 :
405    {
406        KEEP(*(.cy_rtoc_part2))
407    } > sflash_rtoc_2
408
409
410    /* Places the code in the Execute in Place (XIP) section. See the smif driver
411    *  documentation for details.
412    */
413    cy_xip :
414    {
415        __cy_xip_start = .;
416        KEEP(*(.cy_xip))
417        __cy_xip_end = .;
418    } > xip
419
420
421    /* eFuse */
422    .cy_efuse :
423    {
424        KEEP(*(.cy_efuse))
425    } > efuse
426
427
428    /* These sections are used for additional metadata (silicon revision,
429    *  Silicon/JTAG ID, etc.) storage.
430    */
431    .cymeta         0x90500000 : { KEEP(*(.cymeta)) } :NONE
432}
433
434
435/* The following symbols used by the cymcuelftool. */
436/* Flash */
437__cy_memory_0_start    = 0x10000000;
438__cy_memory_0_length   = 0x00040000;
439__cy_memory_0_row_size = 0x200;
440
441
442/* Supervisory Flash */
443__cy_memory_2_start    = 0x16000000;
444__cy_memory_2_length   = 0x8000;
445__cy_memory_2_row_size = 0x200;
446
447/* XIP */
448__cy_memory_3_start    = 0x18000000;
449__cy_memory_3_length   = 0x08000000;
450__cy_memory_3_row_size = 0x200;
451
452/* eFuse */
453__cy_memory_4_start    = 0x90700000;
454__cy_memory_4_length   = 0x100000;
455__cy_memory_4_row_size = 1;
456
457/* EOF */
458