1 /*******************************************************************************
2 * File Name: cycfg_clocks.c
3 *
4 * Description:
5 * Clock configuration
6 * This file was automatically generated and should not be modified.
7 * Configurator Backend 3.0.0
8 * device-db 4.1.0.3437
9 * mtb-pdl-cat1 3.3.0.21979
10 *
11 ********************************************************************************
12 * Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
13 * an affiliate of Cypress Semiconductor Corporation.
14 * SPDX-License-Identifier: Apache-2.0
15 *
16 * Licensed under the Apache License, Version 2.0 (the "License");
17 * you may not use this file except in compliance with the License.
18 * You may obtain a copy of the License at
19 *
20 * http://www.apache.org/licenses/LICENSE-2.0
21 *
22 * Unless required by applicable law or agreed to in writing, software
23 * distributed under the License is distributed on an "AS IS" BASIS,
24 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
25 * See the License for the specific language governing permissions and
26 * limitations under the License.
27 ********************************************************************************/
28
29 #include "cycfg_clocks.h"
30
31 #if defined (CY_USING_HAL)
32 const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj =
33 {
34 .type = CYHAL_RSC_CLOCK,
35 .block_num = CYBSP_CSD_CLK_DIV_HW,
36 .channel_num = CYBSP_CSD_CLK_DIV_NUM,
37 };
38 #endif //defined (CY_USING_HAL)
39
40
init_cycfg_clocks(void)41 void init_cycfg_clocks(void)
42 {
43 Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 0U);
44 Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 0U, 255U);
45 Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 0U);
46 }
47
reserve_cycfg_clocks(void)48 void reserve_cycfg_clocks(void)
49 {
50 #if defined (CY_USING_HAL)
51 cyhal_hwmgr_reserve(&CYBSP_CSD_CLK_DIV_obj);
52 #endif //defined (CY_USING_HAL)
53 }
54