1 /******************************************************************************* 2 * File Name: cycfg_routing.h 3 * 4 * Description: 5 * Establishes all necessary connections between hardware elements. 6 * This file was automatically generated and should not be modified. 7 * Configurator Backend 3.0.0 8 * device-db 4.1.0.3437 9 * mtb-pdl-cat1 3.3.0.21979 10 * 11 ******************************************************************************** 12 * Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or 13 * an affiliate of Cypress Semiconductor Corporation. 14 * SPDX-License-Identifier: Apache-2.0 15 * 16 * Licensed under the Apache License, Version 2.0 (the "License"); 17 * you may not use this file except in compliance with the License. 18 * You may obtain a copy of the License at 19 * 20 * http://www.apache.org/licenses/LICENSE-2.0 21 * 22 * Unless required by applicable law or agreed to in writing, software 23 * distributed under the License is distributed on an "AS IS" BASIS, 24 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 25 * See the License for the specific language governing permissions and 26 * limitations under the License. 27 ********************************************************************************/ 28 29 #if !defined(CYCFG_ROUTING_H) 30 #define CYCFG_ROUTING_H 31 32 #if defined(__cplusplus) 33 extern "C" { 34 #endif 35 36 #include "cycfg_notices.h" 37 void init_cycfg_routing(void); 38 39 #define ioss_0_port_0_pin_0_ANALOG P0_0_SRSS_WCO_IN 40 #define ioss_0_port_0_pin_1_ANALOG P0_1_SRSS_WCO_OUT 41 #define ioss_0_port_6_pin_6_HSIOM P6_6_CPUSS_SWJ_SWDIO_TMS 42 #define ioss_0_port_6_pin_7_HSIOM P6_7_CPUSS_SWJ_SWCLK_TCLK 43 #define ioss_0_port_7_pin_0_HSIOM HSIOM_SEL_AMUXA 44 #define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_AMUXA 45 #define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_AMUXA 46 #define ioss_0_port_7_pin_3_HSIOM HSIOM_SEL_AMUXA 47 #define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_AMUXA 48 #define ioss_0_port_8_pin_0_HSIOM HSIOM_SEL_AMUXA 49 #define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_AMUXA 50 #define ioss_0_port_9_pin_3_HSIOM HSIOM_SEL_AMUXA 51 52 #if defined(__cplusplus) 53 } 54 #endif 55 56 57 #endif /* CYCFG_ROUTING_H */ 58