1/***************************************************************************//**
2* \file cy8c6xxa_cm4_dual.ld
3* \version 2.91
4*
5* Linker file for the GNU C compiler.
6*
7* The main purpose of the linker script is to describe how the sections in the
8* input files should be mapped into the output file, and to control the memory
9* layout of the output file.
10*
11* \note The entry point location is fixed and starts at 0x10000000. The valid
12* application image should be placed there.
13*
14* \note The linker files included with the PDL template projects must be generic
15* and handle all common use cases. Your project may not use every section
16* defined in the linker files. In that case you may see warnings during the
17* build process. In your project, you can simply comment out or remove the
18* relevant code in the linker file.
19*
20********************************************************************************
21* \copyright
22* Copyright 2016-2021 Cypress Semiconductor Corporation
23* SPDX-License-Identifier: Apache-2.0
24*
25* Licensed under the Apache License, Version 2.0 (the "License");
26* you may not use this file except in compliance with the License.
27* You may obtain a copy of the License at
28*
29*     http://www.apache.org/licenses/LICENSE-2.0
30*
31* Unless required by applicable law or agreed to in writing, software
32* distributed under the License is distributed on an "AS IS" BASIS,
33* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
34* See the License for the specific language governing permissions and
35* limitations under the License.
36*******************************************************************************/
37
38OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
39SEARCH_DIR(.)
40GROUP(-lgcc -lc -lnosys)
41ENTRY(Reset_Handler)
42
43/* The size of the stack section at the end of CM4 SRAM */
44STACK_SIZE = 0x1000;
45
46/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
47* More about CM0+ prebuilt images, see here:
48* https://github.com/cypresssemiconductorco/psoc6cm0p
49*/
50/* The size of the Cortex-M0+ application image at the start of FLASH */
51FLASH_CM0P_SIZE  = 0x2000;
52
53/* Force symbol to be entered in the output file as an undefined symbol. Doing
54* this may, for example, trigger linking of additional modules from standard
55* libraries. You may list several symbols for each EXTERN, and you may use
56* EXTERN multiple times. This command has the same effect as the -u command-line
57* option.
58*/
59EXTERN(Reset_Handler)
60
61/* The MEMORY section below describes the location and size of blocks of memory in the target.
62* Use this section to specify the memory regions available for allocation.
63*/
64MEMORY
65{
66    /* The ram and flash regions control RAM and flash memory allocation for the CM4 core.
67     * You can change the memory allocation by editing the 'ram' and 'flash' regions.
68     * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
69     * Using this memory region for other purposes will lead to unexpected behavior.
70     * Your changes must be aligned with the corresponding memory regions for CM0+ core in 'xx_cm0plus.ld',
71     * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.ld'.
72     */
73    ram               (rwx)   : ORIGIN = 0x08002000, LENGTH = 0xFD800
74    flash             (rx)    : ORIGIN = 0x10000000, LENGTH = 0x200000
75
76    /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash.
77     * You can assign sections to this memory region for only one of the cores.
78     * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
79     * Therefore, repurposing this memory region will prevent such middleware from operation.
80     */
81    em_eeprom         (rx)    : ORIGIN = 0x14000000, LENGTH = 0x8000       /*  32 KB */
82
83    /* The following regions define device specific memory regions and must not be changed. */
84    sflash_user_data  (rx)    : ORIGIN = 0x16000800, LENGTH = 0x800        /* Supervisory flash: User data */
85    sflash_nar        (rx)    : ORIGIN = 0x16001A00, LENGTH = 0x200        /* Supervisory flash: Normal Access Restrictions (NAR) */
86    sflash_public_key (rx)    : ORIGIN = 0x16005A00, LENGTH = 0xC00        /* Supervisory flash: Public Key */
87    sflash_toc_2      (rx)    : ORIGIN = 0x16007C00, LENGTH = 0x200        /* Supervisory flash: Table of Content # 2 */
88    sflash_rtoc_2     (rx)    : ORIGIN = 0x16007E00, LENGTH = 0x200        /* Supervisory flash: Table of Content # 2 Copy */
89    xip               (rx)    : ORIGIN = 0x18000000, LENGTH = 0x8000000    /* 128 MB */
90    efuse             (r)     : ORIGIN = 0x90700000, LENGTH = 0x100000     /*   1 MB */
91}
92
93/* Library configurations */
94GROUP(libgcc.a libc.a libm.a libnosys.a)
95
96/* Linker script to place sections and symbol values. Should be used together
97 * with other linker script that defines memory regions FLASH and RAM.
98 * It references following symbols, which must be defined in code:
99 *   Reset_Handler : Entry of reset handler
100 *
101 * It defines following symbols, which code can use without definition:
102 *   __exidx_start
103 *   __exidx_end
104 *   __copy_table_start__
105 *   __copy_table_end__
106 *   __zero_table_start__
107 *   __zero_table_end__
108 *   __etext
109 *   __data_start__
110 *   __preinit_array_start
111 *   __preinit_array_end
112 *   __init_array_start
113 *   __init_array_end
114 *   __fini_array_start
115 *   __fini_array_end
116 *   __data_end__
117 *   __bss_start__
118 *   __bss_end__
119 *   __end__
120 *   end
121 *   __HeapLimit
122 *   __StackLimit
123 *   __StackTop
124 *   __stack
125 *   __Vectors_End
126 *   __Vectors_Size
127 */
128
129
130SECTIONS
131{
132     /* Cortex-M0+ application flash image area */
133    .cy_m0p_image ORIGIN(flash) :
134    {
135        . = ALIGN(4);
136        __cy_m0p_code_start = . ;
137        KEEP(*(.cy_m0p_image))
138        __cy_m0p_code_end = . ;
139    } > flash
140
141    /* Check if .cy_m0p_image size exceeds FLASH_CM0P_SIZE */
142    ASSERT(__cy_m0p_code_end <= ORIGIN(flash) + FLASH_CM0P_SIZE, "CM0+ flash image overflows with CM4, increase FLASH_CM0P_SIZE")
143
144    /* Cortex-M4 application flash area */
145    .text ORIGIN(flash) + FLASH_CM0P_SIZE :
146    {
147        . = ALIGN(4);
148        __Vectors = . ;
149        KEEP(*(.vectors))
150        . = ALIGN(4);
151        __Vectors_End = .;
152        __Vectors_Size = __Vectors_End - __Vectors;
153        __end__ = .;
154
155        . = ALIGN(4);
156        *(.text*)
157
158        KEEP(*(.init))
159        KEEP(*(.fini))
160
161        /* .ctors */
162        *crtbegin.o(.ctors)
163        *crtbegin?.o(.ctors)
164        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
165        *(SORT(.ctors.*))
166        *(.ctors)
167
168        /* .dtors */
169        *crtbegin.o(.dtors)
170        *crtbegin?.o(.dtors)
171        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
172        *(SORT(.dtors.*))
173        *(.dtors)
174
175        . = ALIGN(4);
176        /* Read-only code (constants). */
177        *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
178        KEEP(*(.eh_frame*))
179
180        /* section information for utest */
181        . = ALIGN(4);
182        __rt_utest_tc_tab_start = .;
183        KEEP(*(UtestTcTab))
184        __rt_utest_tc_tab_end = .;
185
186        /* section information for finsh shell */
187        . = ALIGN(4);
188        __fsymtab_start = .;
189        KEEP(*(FSymTab))
190        __fsymtab_end = .;
191        . = ALIGN(4);
192        __vsymtab_start = .;
193        KEEP(*(VSymTab))
194        __vsymtab_end = .;
195        . = ALIGN(4);
196
197        /* section information for modules */
198        . = ALIGN(4);
199        __rtmsymtab_start = .;
200        KEEP(*(RTMSymTab))
201        __rtmsymtab_end = .;
202
203        /* section information for initialization */
204        . = ALIGN(4);
205        __rt_init_start = .;
206        KEEP(*(SORT(.rti_fn*)))
207        __rt_init_end = .;
208
209    } > flash
210
211    .ARM.extab :
212    {
213        *(.ARM.extab* .gnu.linkonce.armextab.*)
214    } > flash
215
216    __exidx_start = .;
217
218    .ARM.exidx :
219    {
220        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
221    } > flash
222    __exidx_end = .;
223
224
225    /* To copy multiple ROM to RAM sections,
226     * uncomment .copy.table section and,
227     * define __STARTUP_COPY_MULTIPLE in startup_psoc6_02_cm4.S */
228    .copy.table :
229    {
230        . = ALIGN(4);
231        __copy_table_start__ = .;
232
233        /* Copy interrupt vectors from flash to RAM */
234        LONG (__Vectors)                                    /* From */
235        LONG (__ram_vectors_start__)                        /* To   */
236        LONG (__Vectors_End - __Vectors)                    /* Size */
237
238        /* Copy data section to RAM */
239        LONG (__etext)                                      /* From */
240        LONG (__data_start__)                               /* To   */
241        LONG (__data_end__ - __data_start__)                /* Size */
242
243        __copy_table_end__ = .;
244    } > flash
245
246    . = ALIGN(4);
247    .ctors :
248    {
249        PROVIDE(__ctors_start__ = .);
250        KEEP (*(SORT(.init_array.*)))
251        KEEP (*(.init_array))
252        PROVIDE(__ctors_end__ = .);
253    } > flash
254
255    . = ALIGN(4);
256    .dtors :
257    {
258        PROVIDE(__dtors_start__ = .);
259        KEEP(*(SORT(.dtors.*)))
260        KEEP(*(.dtors))
261        PROVIDE(__dtors_end__ = .);
262    } > flash
263
264    /* To clear multiple BSS sections,
265     * uncomment .zero.table section and,
266     * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_02_cm4.S */
267    .zero.table :
268    {
269        . = ALIGN(4);
270        __zero_table_start__ = .;
271        LONG (__bss_start__)
272        LONG (__bss_end__ - __bss_start__)
273        __zero_table_end__ = .;
274    } > flash
275
276    __etext =  . ;
277
278    .ramVectors (NOLOAD) : ALIGN(8)
279    {
280        __ram_vectors_start__ = .;
281        KEEP(*(.ram_vectors))
282        __ram_vectors_end__   = .;
283    } > ram
284
285
286    .data __ram_vectors_end__ :
287    {
288        . = ALIGN(4);
289        __data_start__ = .;
290
291        *(vtable)
292        *(.data*)
293
294        . = ALIGN(4);
295        /* preinit data */
296        PROVIDE_HIDDEN (__preinit_array_start = .);
297        KEEP(*(.preinit_array))
298        PROVIDE_HIDDEN (__preinit_array_end = .);
299
300        . = ALIGN(4);
301        /* init data */
302        PROVIDE_HIDDEN (__init_array_start = .);
303        KEEP(*(SORT(.init_array.*)))
304        KEEP(*(.init_array))
305        PROVIDE_HIDDEN (__init_array_end = .);
306
307        . = ALIGN(4);
308        /* finit data */
309        PROVIDE_HIDDEN (__fini_array_start = .);
310        KEEP(*(SORT(.fini_array.*)))
311        KEEP(*(.fini_array))
312        PROVIDE_HIDDEN (__fini_array_end = .);
313
314        KEEP(*(.jcr*))
315        . = ALIGN(4);
316
317        KEEP(*(.cy_ramfunc*))
318        . = ALIGN(4);
319
320        __data_end__ = .;
321
322    } > ram AT>flash
323
324
325    /* Place variables in the section that should not be initialized during the
326    *  device startup.
327    */
328    .noinit (NOLOAD) : ALIGN(8)
329    {
330      KEEP(*(.noinit))
331    } > ram
332
333
334    /* The uninitialized global or static variables are placed in this section.
335    *
336    * The NOLOAD attribute tells linker that .bss section does not consume
337    * any space in the image. The NOLOAD attribute changes the .bss type to
338    * NOBITS, and that  makes linker to A) not allocate section in memory, and
339    * A) put information to clear the section with all zeros during application
340    * loading.
341    *
342    * Without the NOLOAD attribute, the .bss section might get PROGBITS type.
343    * This  makes linker to A) allocate zeroed section in memory, and B) copy
344    * this section to RAM during application loading.
345    */
346    .bss (NOLOAD):
347    {
348        . = ALIGN(4);
349        __bss_start__ = .;
350        *(.bss*)
351        *(COMMON)
352        . = ALIGN(4);
353        __bss_end__ = .;
354    } > ram
355
356
357    .heap (NOLOAD):
358    {
359        __HeapBase = .;
360        __end__ = .;
361        end = __end__;
362        KEEP(*(.heap*))
363        . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE;
364        __HeapLimit = .;
365    } > ram
366
367
368    /* .stack_dummy section doesn't contains any symbols. It is only
369     * used for linker to calculate size of stack sections, and assign
370     * values to stack symbols later */
371    .stack_dummy (NOLOAD):
372    {
373        KEEP(*(.stack*))
374    } > ram
375
376
377    /* Set stack top to end of RAM, and stack limit move down by
378     * size of stack_dummy section */
379    __StackTop = ORIGIN(ram) + LENGTH(ram);
380    __StackLimit = __StackTop - SIZEOF(.stack_dummy);
381    PROVIDE(__stack = __StackTop);
382
383    /* Check if data + heap + stack exceeds RAM limit */
384    ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
385
386
387    /* Used for the digital signature of the secure application and the Bootloader SDK application.
388    * The size of the section depends on the required data size. */
389    .cy_app_signature ORIGIN(flash) + LENGTH(flash) - 256 :
390    {
391        KEEP(*(.cy_app_signature))
392    } > flash
393
394
395    /* Emulated EEPROM Flash area */
396    .cy_em_eeprom :
397    {
398        KEEP(*(.cy_em_eeprom))
399    } > em_eeprom
400
401
402    /* Supervisory Flash: User data */
403    .cy_sflash_user_data :
404    {
405        KEEP(*(.cy_sflash_user_data))
406    } > sflash_user_data
407
408    /* Supervisory Flash: Normal Access Restrictions (NAR) */
409    .cy_sflash_nar :
410    {
411        KEEP(*(.cy_sflash_nar))
412    } > sflash_nar
413
414
415    /* Supervisory Flash: Public Key */
416    .cy_sflash_public_key :
417    {
418        KEEP(*(.cy_sflash_public_key))
419    } > sflash_public_key
420
421
422    /* Supervisory Flash: Table of Content # 2 */
423    .cy_toc_part2 :
424    {
425        KEEP(*(.cy_toc_part2))
426    } > sflash_toc_2
427
428
429    /* Supervisory Flash: Table of Content # 2 Copy */
430    .cy_rtoc_part2 :
431    {
432        KEEP(*(.cy_rtoc_part2))
433    } > sflash_rtoc_2
434
435
436    /* Places the code in the Execute in Place (XIP) section. See the smif driver
437    *  documentation for details.
438    */
439    cy_xip :
440    {
441        __cy_xip_start = .;
442        KEEP(*(.cy_xip))
443        __cy_xip_end = .;
444    } > xip
445
446
447    /* eFuse */
448    .cy_efuse :
449    {
450        KEEP(*(.cy_efuse))
451    } > efuse
452
453
454    /* These sections are used for additional metadata (silicon revision,
455    *  Silicon/JTAG ID, etc.) storage.
456    */
457    .cymeta         0x90500000 : { KEEP(*(.cymeta)) } :NONE
458}
459
460
461/* The following symbols used by the cymcuelftool. */
462/* Flash */
463__cy_memory_0_start    = 0x10000000;
464__cy_memory_0_length   = 0x00200000;
465__cy_memory_0_row_size = 0x200;
466
467/* Emulated EEPROM Flash area */
468__cy_memory_1_start    = 0x14000000;
469__cy_memory_1_length   = 0x8000;
470__cy_memory_1_row_size = 0x200;
471
472/* Supervisory Flash */
473__cy_memory_2_start    = 0x16000000;
474__cy_memory_2_length   = 0x8000;
475__cy_memory_2_row_size = 0x200;
476
477/* XIP */
478__cy_memory_3_start    = 0x18000000;
479__cy_memory_3_length   = 0x08000000;
480__cy_memory_3_row_size = 0x200;
481
482/* eFuse */
483__cy_memory_4_start    = 0x90700000;
484__cy_memory_4_length   = 0x100000;
485__cy_memory_4_row_size = 1;
486
487/* EOF */
488