README.md
1# CY8CKIT-062S2-43012 BSP
2
3## Overview
4
5The CY8CKIT-062S2-43012 PSoC™ 6S2 Wi-Fi BT Pioneer Kit is a low-cost hardware platform that enables design and debug of PSoC™ 6 MCUs. It comes with a Murata 1LV Module (CYW43012 Wi-Fi + Bluetooth Combo Chip), industry-leading CAPSENSE™ for touch buttons and slider, on-board debugger/programmer with KitProg3, microSD card interface, 512-Mb Quad-SPI NOR flash, PDM-PCM microphone interface.
6
7
8
9To use code from the BSP, simply include a reference to `cybsp.h`.
10
11## Features
12
13### Kit Features:
14
15* Support of up to 2MB Flash and 1MB SRAM
16* Dedicated SDHC to interface with WICED wireless devices.
17* Delivers dual-cores, with a 150-MHz Arm® Cortex®-M4 as the primary application processor and a 100-MHz Arm® Cortex®-M0+ as the secondary processor for low-power operations.
18* Supports Full-Speed USB, capacitive-sensing with CAPSENSE, a PDM-PCM digital microphone interface, a Quad- SPI interface, 13 serial communication blocks, 7 programmable analog blocks, and 56 programmable digital blocks.
19
20### Kit Contents:
21
22* PSoC™ 6S2 Wi-Fi BT Pioneer Board
23* USB Type-A to Micro-B cable
24* Quick Start Guide
25* Four jumper wires (4 inches each)
26* Two jumper wires (5 inches each)
27
28## BSP Configuration
29
30The BSP has a few hooks that allow its behavior to be configured. Some of these items are enabled by default while others must be explicitly enabled. Items enabled by default are specified in the CY8CKIT-062S2-43012.mk file. The items that are enabled can be changed by creating a custom BSP or by editing the application makefile.
31
32Components:
33* Device specific category reference (e.g.: CAT1) - This component, enabled by default, pulls in any device specific code for this board.
34
35Defines:
36* CYBSP_WIFI_CAPABLE - This define, disabled by default, causes the BSP to initialize the interface to an onboard wireless chip if it has one.
37* CY_USING_HAL - This define, enabled by default, specifies that the HAL is intended to be used by the application. This will cause the BSP to include the applicable header file and to initialize the system level drivers.
38* CYBSP_CUSTOM_SYSCLK_PM_CALLBACK - This define, disabled by default, causes the BSP to skip registering its default SysClk Power Management callback, if any, and instead to invoke the application-defined function `cybsp_register_custom_sysclk_pm_callback` to register an application-specific callback.
39
40### Clock Configuration
41
42| Clock | Source | Output Frequency |
43|----------|-----------|------------------|
44| FLL | IMO | 100.0 MHz |
45| PLL | IMO | 48.0 MHz |
46| CLK_HF0 | CLK_PATH0 | 100 MHz |
47
48### Power Configuration
49
50* System Active Power Mode: LP
51* System Idle Power Mode: Deep Sleep
52* VDDA Voltage: 3300 mV
53* VDDD Voltage: 3300 mV
54
55See the [BSP Setttings][settings] for additional board specific configuration settings.
56
57## API Reference Manual
58
59The CY8CKIT-062S2-43012 Board Support Package provides a set of APIs to configure, initialize and use the board resources.
60
61See the [BSP API Reference Manual][api] for the complete list of the provided interfaces.
62
63## More information
64* [CY8CKIT-062S2-43012 BSP API Reference Manual][api]
65* [CY8CKIT-062S2-43012 Documentation](http://www.cypress.com/CY8CKIT-062S2-43012)
66* [Cypress Semiconductor, an Infineon Technologies Company](http://www.cypress.com)
67* [Infineon GitHub](https://github.com/infineon)
68* [ModusToolbox™](https://www.cypress.com/products/modustoolbox-software-environment)
69
70[api]: https://infineon.github.io/TARGET_CY8CKIT-062S2-43012/html/modules.html
71[settings]: https://infineon.github.io/TARGET_CY8CKIT-062S2-43012/html/md_bsp_settings.html
72
73---
74© Cypress Semiconductor Corporation (an Infineon company) or an affiliate of Cypress Semiconductor Corporation, 2019-2022.
