1 /******************************************************************************* 2 * File Name: cycfg_system.h 3 * 4 * Description: 5 * System configuration 6 * This file was automatically generated and should not be modified. 7 * Configurator Backend 3.0.0 8 * device-db 4.3.0.3855 9 * mtb-pdl-cat1 3.4.0.24948 10 * 11 ******************************************************************************** 12 * Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or 13 * an affiliate of Cypress Semiconductor Corporation. 14 * SPDX-License-Identifier: Apache-2.0 15 * 16 * Licensed under the Apache License, Version 2.0 (the "License"); 17 * you may not use this file except in compliance with the License. 18 * You may obtain a copy of the License at 19 * 20 * http://www.apache.org/licenses/LICENSE-2.0 21 * 22 * Unless required by applicable law or agreed to in writing, software 23 * distributed under the License is distributed on an "AS IS" BASIS, 24 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 25 * See the License for the specific language governing permissions and 26 * limitations under the License. 27 ********************************************************************************/ 28 29 #if !defined(CYCFG_SYSTEM_H) 30 #define CYCFG_SYSTEM_H 31 32 #include "cycfg_notices.h" 33 #include "cy_sysclk.h" 34 #include "cy_pra.h" 35 #include "cy_pra_cfg.h" 36 #include "cy_systick.h" 37 #if defined (CY_USING_HAL) 38 #include "cyhal_hwmgr.h" 39 #endif //defined (CY_USING_HAL) 40 #include "cy_syspm.h" 41 42 #if defined(__cplusplus) 43 extern "C" { 44 #endif 45 46 #define cpuss_0_dap_0_ENABLED 1U 47 #define srss_0_clock_0_ENABLED 1U 48 #define srss_0_clock_0_altsystickclk_0_ENABLED 1U 49 #define srss_0_clock_0_bakclk_0_ENABLED 1U 50 #define srss_0_clock_0_fastclk_0_ENABLED 1U 51 #define srss_0_clock_0_fll_0_ENABLED 1U 52 #define srss_0_clock_0_hfclk_0_ENABLED 1U 53 #define CY_CFG_SYSCLK_CLKHF0 0UL 54 #define CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM 0UL 55 #define srss_0_clock_0_ilo_0_ENABLED 1U 56 #define srss_0_clock_0_imo_0_ENABLED 1U 57 #define srss_0_clock_0_lfclk_0_ENABLED 1U 58 #define CY_CFG_SYSCLK_CLKLF_FREQ_HZ 32768 59 #define CY_CFG_SYSCLK_CLKLF_SOURCE CY_SYSCLK_CLKLF_IN_ILO 60 #define srss_0_clock_0_pathmux_0_ENABLED 1U 61 #define srss_0_clock_0_pathmux_1_ENABLED 1U 62 #define srss_0_clock_0_pathmux_2_ENABLED 1U 63 #define srss_0_clock_0_pathmux_3_ENABLED 1U 64 #define srss_0_clock_0_pathmux_4_ENABLED 1U 65 #define srss_0_clock_0_pathmux_5_ENABLED 1U 66 #define srss_0_clock_0_periclk_0_ENABLED 1U 67 #define srss_0_clock_0_pll_0_ENABLED 1U 68 #define srss_0_clock_0_slowclk_0_ENABLED 1U 69 #define srss_0_clock_0_timerclk_0_ENABLED 1U 70 #define srss_0_power_0_ENABLED 1U 71 #define CY_CFG_PWR_MODE_LP 0x01UL 72 #define CY_CFG_PWR_MODE_ULP 0x02UL 73 #define CY_CFG_PWR_MODE_ACTIVE 0x04UL 74 #define CY_CFG_PWR_MODE_SLEEP 0x08UL 75 #define CY_CFG_PWR_MODE_DEEPSLEEP 0x10UL 76 #define CY_CFG_PWR_SYS_IDLE_MODE CY_CFG_PWR_MODE_DEEPSLEEP 77 #define CY_CFG_PWR_SYS_ACTIVE_MODE CY_CFG_PWR_MODE_LP 78 #define CY_CFG_PWR_DEEPSLEEP_LATENCY 0UL 79 #define CY_CFG_PWR_USING_LDO 1 80 #define CY_CFG_PWR_VDDA_MV 3300 81 #define CY_CFG_PWR_VDDD_MV 3300 82 #define CY_CFG_PWR_VBACKUP_MV 3300 83 #define CY_CFG_PWR_VDD_NS_MV 3300 84 #define CY_CFG_PWR_VDDIO0_MV 3300 85 #define CY_CFG_PWR_VDDIO1_MV 3300 86 87 #if defined (CY_USING_HAL) 88 extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj; 89 extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj; 90 extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj; 91 extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_3_obj; 92 extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_4_obj; 93 extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_5_obj; 94 #endif //defined (CY_USING_HAL) 95 96 void init_cycfg_system(void); 97 void reserve_cycfg_system(void); 98 99 #if defined(__cplusplus) 100 } 101 #endif 102 103 104 #endif /* CYCFG_SYSTEM_H */ 105