1/*******************************************************************************
2* \file xmc7200_x8384_cm7.icf
3* \version 1.0.0
4*
5* Linker file for the IAR compiler.
6*
7* The main purpose of the linker script is to describe how the sections in the
8* input files should be mapped into the output file, and to control the memory
9* layout of the output file.
10*
11* \note The entry point is fixed and starts at 0x10000000. The valid application
12* image should be placed there.
13*
14* \note The linker files included with the PDL template projects must be generic
15* and handle all common use cases. Your project may not use every section
16* defined in the linker files. In that case you may see warnings during the
17* build process. In your project, you can simply comment out or remove the
18* relevant code in the linker file.
19*
20********************************************************************************
21* \copyright
22* Copyright 2021 Cypress Semiconductor Corporation
23* SPDX-License-Identifier: Apache-2.0
24*
25* Licensed under the Apache License, Version 2.0 (the "License");
26* you may not use this file except in compliance with the License.
27* You may obtain a copy of the License at
28*
29*     http://www.apache.org/licenses/LICENSE-2.0
30*
31* Unless required by applicable law or agreed to in writing, software
32* distributed under the License is distributed on an "AS IS" BASIS,
33* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
34* See the License for the specific language governing permissions and
35* limitations under the License.
36*******************************************************************************/
37
38define symbol sram_start_reserve                = 0;
39
40define symbol sram_total_size                   = 0x00100000;
41define symbol sram_private_for_srom             = 0x00000800; /* Private SRAM for SROM (e.g. API processing) */
42define symbol sram_used_by_boot                 = 0x0; /* Used during boot by Cypress firmware (content will be overwritten on reset, so it should not be used for loadable sections in case of RAM build configurations) */
43
44define symbol cm0plus_sram_reserve              = 0x00004000; /* 16K   : cm0 sram size */
45define symbol cm7_0_sram_reserve                = 0x000FC000; /* 1008K : cm7_0 sram size */
46
47define symbol code_flash_total_size             = 0x00830000; /* 8384K: total flash size */
48define symbol cm0plus_code_flash_reserve        = 0x00080000; /* 512K : cm0 flash size */
49define symbol cm7_0_code_flash_reserve          = 0x007B0000; /* 7872K: cm7_0 flash size */
50
51
52define symbol code_flash_base_address           = 0x10000000;
53define symbol sram_base_address                 = 0x28000000;
54
55define symbol ecc_init_width                    = 8; /* Most restrictive native ECC width of all "normal" memories (SRAM, DTCM, ITCM) in any Traveo II derivate is used to keep the code generic */
56
57define symbol cm7_heap_reserve                  =  0x00001000;
58define symbol cm7_stack_reserve                 =  0x00001000;
59
60/*###ICF### Section handled by ICF editor, don't touch! ****/
61/*-Editor annotation file-*/
62/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
63/*-Specials-*/
64define symbol __ICFEDIT_intvec_start__ = 0x00000000;
65
66/* The symbols below define the location and size of blocks of memory in the target.
67 * Use these symbols to specify the memory regions available for allocation.
68 */
69
70/* The following symbols control RAM and flash memory allocation for the CM7 cores.
71 * You can change the memory allocation by editing RAM and Flash values.
72 * Your changes must be aligned with the corresponding symbols for CM0+ core in 'xx_cm0plus.icf',
73 * where 'xx' is the device group; for example, 'xmc7100d_x4160_cm0plus.icf'.
74 * any changes here must also be aligned in file 'xmc7xxx_partition.h'.
75 * after which cm0p core aplication must be build and flashed again.
76 */
77/* RAM */
78define symbol __ICFEDIT_region_IRAM1_start__ = 0x28004000; // sram_base_address + cm0plus_sram_reserve;
79define symbol __ICFEDIT_region_IRAM1_end__   = 0x280FFFFF; // cm7_0_sram_reserve;
80define symbol __ICFEDIT_region_IRAM2_start__ = 0x0;
81define symbol __ICFEDIT_region_IRAM2_end__   = 0x0;
82
83/* Flash */
84define symbol __ICFEDIT_region_IROM1_start__ = 0x10080000; // code_flash_base_address + cm0plus_code_flash_reserve
85define symbol __ICFEDIT_region_IROM1_end__   = 0x1082FFFF; // cm7_0_code_flash_reserve
86define symbol __ICFEDIT_region_IROM2_start__ = 0x0;
87define symbol __ICFEDIT_region_IROM2_end__   = 0x0;
88
89define symbol __ICFEDIT_region_EROM1_start__ = 0x0;
90define symbol __ICFEDIT_region_EROM1_end__   = 0x0;
91define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
92define symbol __ICFEDIT_region_EROM2_end__   = 0x0;
93define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
94define symbol __ICFEDIT_region_EROM3_end__   = 0x0;
95
96
97define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
98define symbol __ICFEDIT_region_ERAM1_end__   = 0x0;
99define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
100define symbol __ICFEDIT_region_ERAM2_end__   = 0x0;
101define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
102define symbol __ICFEDIT_region_ERAM3_end__   = 0x0;
103/*-Sizes-*/
104
105define symbol __ICFEDIT_size_cstack__ = 0x00001000; //cm7_stack_reserve
106define symbol __ICFEDIT_size_proc_stack__ = 0x0;
107
108/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */
109define symbol __ICFEDIT_size_heap__ = 0x00001000; //cm7_heap_reserve
110
111/**** End of ICF editor section. ###ICF###*/
112
113define symbol heap_reserve                      = __ICFEDIT_size_heap__;
114define symbol stack_reserve                     = (__ICFEDIT_size_cstack__ + (ecc_init_width - 1)) & (~((ecc_init_width - 1))); /* Ensure that stack size is an integer multiple of ECC init width (round up) */
115
116/* SRAM reservations */
117define symbol _base_SRAM_CM7_0                  = __ICFEDIT_region_IRAM1_start__;
118define symbol _size_SRAM_CM7_0                  = __ICFEDIT_region_IRAM1_end__ - __ICFEDIT_region_IRAM1_start__ + 1;
119
120/* Code flash reservations */
121define symbol _base_CODE_FLASH_CM0P             = code_flash_base_address;
122define symbol _size_CODE_FLASH_CM0P             = cm0plus_code_flash_reserve;
123define symbol _base_CODE_FLASH_CM7_0            = __ICFEDIT_region_IROM1_start__;
124define symbol _size_CODE_FLASH_CM7_0            = __ICFEDIT_region_IROM1_end__ - __ICFEDIT_region_IROM1_start__ + 1;
125
126
127define symbol _base_SRAM                        = _base_SRAM_CM7_0;
128define symbol _size_SRAM                        = _size_SRAM_CM7_0;
129define symbol _base_CODE_FLASH                  = _base_CODE_FLASH_CM7_0;
130define symbol _size_CODE_FLASH                  = _size_CODE_FLASH_CM7_0;
131
132
133/*============================================================
134 * Memory definitions
135 *============================================================
136 */
137
138define memory mem with size = 4G;
139
140define region SRAM                              = mem:[from _base_SRAM                  size _size_SRAM       ];
141define region CODE_FLASH                        = mem:[from _base_CODE_FLASH            size _size_CODE_FLASH ];
142
143/*============================================================
144 * Block definitions
145 *============================================================
146 */
147define block CSTACK         with alignment = 8, size = stack_reserve { };
148define block HEAP           with expanding size, alignment = 8, minimum size = heap_reserve { };
149define block HEAP_STACK     { block HEAP, last block CSTACK };
150define block CM0P_RO with size = (_size_CODE_FLASH_CM0P)  { readonly section .cy_m0p_image };
151define block CY_SHAREDMEM   with alignment = 32 { section .cy_sharedmem };
152
153/*============================================================
154 * Initialization
155 *============================================================
156 */
157initialize by copy { readwrite };
158do not initialize  { section .noinit, section .intvec_ram };
159
160/*============================================================
161 * Placement
162 *============================================================
163 */
164
165/* Flash - Cortex-M0+ application image */
166place at address (_base_CODE_FLASH_CM0P)  { block CM0P_RO };
167
168/* Link location specific assignment of 'readonly' type sections to either SRAM or CODE_FLASH */
169/* Note: .intvec must be the first section in ROM in order for __cm7_vector_base_linker_symbol to be correctly calculated! */
170
171place at start of CODE_FLASH  { section .intvec };
172place in          CODE_FLASH  { readonly };
173
174place in          SRAM  { readwrite };
175place in          SRAM  { block CY_SHAREDMEM };
176place at end   of SRAM  { block HEAP_STACK };
177
178keep {  section .intvec  };
179keep {  section .cy_m0p_image  };
180
181/* Following definitions ensure that SRAM will not be touched at all by startup ECC initialization when code is linked to SRAM,
182 * use debugger script to initialize the SRAM before downloading the application or adjust below symbols to not include
183 * the area of SRAM where "ROM type" sections are linked to
184 */
185define exported symbol __ecc_init_sram_start_address = start(SRAM);
186define exported symbol __ecc_init_sram_end_address   = end(SRAM);
187
188/* EOF */
189