1 /** 2 ****************************************************************************** 3 * @file lib_clk.c 4 * @author Application Team 5 * @version V4.4.0 6 * @date 2018-09-27 7 * @brief Clock library. 8 ****************************************************************************** 9 * @attention 10 * 11 ****************************************************************************** 12 */ 13 #ifndef __LIB_CLK_H 14 #define __LIB_CLK_H 15 16 #ifdef __cplusplus 17 extern "C" { 18 #endif 19 20 #include "target.h" 21 22 /* PLLL Configure */ 23 typedef struct 24 { 25 uint32_t Source; 26 uint32_t State; 27 uint32_t Frequency; 28 } PLLL_ConfTypeDef; 29 30 /* PLLH Configure */ 31 typedef struct 32 { 33 uint32_t Source; 34 uint32_t State; 35 uint32_t Frequency; 36 } PLLH_ConfTypeDef; 37 38 /* RCH Configure */ 39 typedef struct 40 { 41 uint32_t State; 42 } RCH_ConfTypeDef; 43 44 /* XTALH Configure */ 45 typedef struct 46 { 47 uint32_t State; 48 } XTALH_ConfTypeDef; 49 50 /* RTCCLK Configure */ 51 typedef struct 52 { 53 uint32_t Source; 54 uint32_t Divider; 55 } RTCCLK_ConfTypeDef; 56 57 /* HCLK Configure */ 58 typedef struct 59 { 60 uint32_t Divider; /* 1 ~ 256 */ 61 } HCLK_ConfTypeDef; 62 63 /* PCLK Configure */ 64 typedef struct 65 { 66 uint32_t Divider; /* 1 ~ 256 */ 67 } PCLK_ConfTypeDef; 68 69 /* Clock Configure */ 70 typedef struct 71 { 72 uint32_t ClockType; /* The clock to be configured */ 73 74 uint32_t AHBSource; 75 76 PLLL_ConfTypeDef PLLL; 77 78 PLLH_ConfTypeDef PLLH; 79 80 XTALH_ConfTypeDef XTALH; 81 82 RTCCLK_ConfTypeDef RTCCLK; 83 84 HCLK_ConfTypeDef HCLK; 85 86 PCLK_ConfTypeDef PCLK; 87 88 } CLK_InitTypeDef; 89 90 /***** ClockType *****/ 91 #define CLK_TYPE_Msk (0xFFUL) 92 #define CLK_TYPE_ALL CLK_TYPE_Msk 93 #define CLK_TYPE_AHBSRC (0x01UL) /* AHB Clock source to configure */ 94 #define CLK_TYPE_PLLL (0x02UL) /* PLLL to configure */ 95 #define CLK_TYPE_PLLH (0x04UL) /* PLLH to configure */ 96 #define CLK_TYPE_XTALH (0x08UL) /* XTALH to configure */ 97 #define CLK_TYPE_RTCCLK (0x20UL) /* RTCCLK to configure */ 98 #define CLK_TYPE_HCLK (0x40UL) /* AHB Clock to configure */ 99 #define CLK_TYPE_PCLK (0x80UL) /* APB Clock to configure */ 100 101 /***** AHBSource *****/ 102 #define CLK_AHBSEL_6_5MRC MISC2_CLKSEL_CLKSEL_RCOH 103 #define CLK_AHBSEL_6_5MXTAL MISC2_CLKSEL_CLKSEL_XOH 104 #define CLK_AHBSEL_HSPLL MISC2_CLKSEL_CLKSEL_PLLH 105 #define CLK_AHBSEL_RTCCLK MISC2_CLKSEL_CLKSEL_RTCCLK 106 #define CLK_AHBSEL_LSPLL MISC2_CLKSEL_CLKSEL_PLLL 107 108 /***** PLLL_ConfTypeDef PLLL *****/ 109 /* PLLL.Source */ 110 #define CLK_PLLLSRC_RCL PMU_CONTROL_PLLL_SEL 111 #define CLK_PLLLSRC_XTALL (0) 112 /* PLLL.State */ 113 #define CLK_PLLL_ON ANA_REG3_PLLLPDN 114 #define CLK_PLLL_OFF (0) 115 /* PLLL.Frequency */ 116 #define CLK_PLLL_26_2144MHz ANA_REG9_PLLLSEL_26M 117 #define CLK_PLLL_13_1072MHz ANA_REG9_PLLLSEL_13M 118 #define CLK_PLLL_6_5536MHz ANA_REG9_PLLLSEL_6_5M 119 #define CLK_PLLL_3_2768MHz ANA_REG9_PLLLSEL_3_2M 120 #define CLK_PLLL_1_6384MHz ANA_REG9_PLLLSEL_1_6M 121 #define CLK_PLLL_0_8192MHz ANA_REG9_PLLLSEL_800K 122 #define CLK_PLLL_0_4096MHz ANA_REG9_PLLLSEL_400K 123 #define CLK_PLLL_0_2048MHz ANA_REG9_PLLLSEL_200K 124 125 /***** PLLH_ConfTypeDef PLLH *****/ 126 /* PLLH.Source */ 127 #define CLK_PLLHSRC_RCH (0) 128 #define CLK_PLLHSRC_XTALH PMU_CONTROL_PLLH_SEL 129 /* PLLH.State */ 130 #define CLK_PLLH_ON ANA_REG3_PLLHPDN 131 #define CLK_PLLH_OFF (0) 132 /* PLLH.Frequency */ 133 #define CLK_PLLH_13_1072MHz ANA_REG9_PLLHSEL_X2 134 #define CLK_PLLH_16_384MHz ANA_REG9_PLLHSEL_X2_5 135 #define CLK_PLLH_19_6608MHz ANA_REG9_PLLHSEL_X3 136 #define CLK_PLLH_22_9376MHz ANA_REG9_PLLHSEL_X3_5 137 #define CLK_PLLH_26_2144MHz ANA_REG9_PLLHSEL_X4 138 #define CLK_PLLH_29_4912MHz ANA_REG9_PLLHSEL_X4_5 139 #define CLK_PLLH_32_768MHz ANA_REG9_PLLHSEL_X5 140 #define CLK_PLLH_36_0448MHz ANA_REG9_PLLHSEL_X5_5 141 #define CLK_PLLH_39_3216MHz ANA_REG9_PLLHSEL_X6 142 #define CLK_PLLH_42_5984MHz ANA_REG9_PLLHSEL_X6_5 143 #define CLK_PLLH_45_8752MHz ANA_REG9_PLLHSEL_X7 144 #define CLK_PLLH_49_152MHz ANA_REG9_PLLHSEL_X7_5 145 146 /* XTALH_ConfTypeDef XTALH */ 147 /* XTALH.State */ 148 #define CLK_XTALH_ON ANA_REG3_XOHPDN 149 #define CLK_XTALH_OFF (0) 150 151 /* RTCCLK Configure */ 152 /* RTCCLK.Source */ 153 #define CLK_RTCCLKSRC_XTALL (0) 154 #define CLK_RTCCLKSRC_RCL (PMU_CONTROL_RTCLK_SEL) 155 /* RTCCLK.Divider */ 156 #define CLK_RTCCLKDIV_1 (RTC_PSCA_PSCA_0) 157 #define CLK_RTCCLKDIV_4 (RTC_PSCA_PSCA_1) 158 159 //AHB Periphral 160 #define CLK_AHBPERIPHRAL_DMA MISC2_HCLKEN_DMA 161 #define CLK_AHBPERIPHRAL_GPIO MISC2_HCLKEN_GPIO 162 #define CLK_AHBPERIPHRAL_LCD MISC2_HCLKEN_LCD 163 #define CLK_AHBPERIPHRAL_CRYPT MISC2_HCLKEN_CRYPT 164 #define CLK_AHBPERIPHRAL_ALL (MISC2_HCLKEN_DMA \ 165 |MISC2_HCLKEN_GPIO \ 166 |MISC2_HCLKEN_LCD \ 167 |MISC2_HCLKEN_CRYPT) 168 169 //APB Periphral 170 #define CLK_APBPERIPHRAL_DMA MISC2_PCLKEN_DMA 171 #define CLK_APBPERIPHRAL_I2C MISC2_PCLKEN_I2C 172 #define CLK_APBPERIPHRAL_SPI1 MISC2_PCLKEN_SPI1 173 #define CLK_APBPERIPHRAL_UART0 MISC2_PCLKEN_UART0 174 #define CLK_APBPERIPHRAL_UART1 MISC2_PCLKEN_UART1 175 #define CLK_APBPERIPHRAL_UART2 MISC2_PCLKEN_UART2 176 #define CLK_APBPERIPHRAL_UART3 MISC2_PCLKEN_UART3 177 #define CLK_APBPERIPHRAL_UART4 MISC2_PCLKEN_UART4 178 #define CLK_APBPERIPHRAL_UART5 MISC2_PCLKEN_UART5 179 #define CLK_APBPERIPHRAL_ISO78160 MISC2_PCLKEN_ISO78160 180 #define CLK_APBPERIPHRAL_ISO78161 MISC2_PCLKEN_ISO78161 181 #define CLK_APBPERIPHRAL_TIMER MISC2_PCLKEN_TIMER 182 #define CLK_APBPERIPHRAL_MISC MISC2_PCLKEN_MISC 183 #define CLK_APBPERIPHRAL_MISC2 MISC2_PCLKEN_MISC2 184 #define CLK_APBPERIPHRAL_PMU MISC2_PCLKEN_PMU 185 #define CLK_APBPERIPHRAL_RTC MISC2_PCLKEN_RTC 186 #define CLK_APBPERIPHRAL_ANA MISC2_PCLKEN_ANA 187 #define CLK_APBPERIPHRAL_U32K0 MISC2_PCLKEN_U32K0 188 #define CLK_APBPERIPHRAL_U32K1 MISC2_PCLKEN_U32K1 189 #define CLK_APBPERIPHRAL_SPI2 MISC2_PCLKEN_SPI2 190 #define CLK_APBPERIPHRAL_ALL (MISC2_PCLKEN_DMA \ 191 |MISC2_PCLKEN_I2C \ 192 |MISC2_PCLKEN_SPI1 \ 193 |MISC2_PCLKEN_UART0 \ 194 |MISC2_PCLKEN_UART1 \ 195 |MISC2_PCLKEN_UART2 \ 196 |MISC2_PCLKEN_UART3 \ 197 |MISC2_PCLKEN_UART4 \ 198 |MISC2_PCLKEN_UART5 \ 199 |MISC2_PCLKEN_ISO78160 \ 200 |MISC2_PCLKEN_ISO78161 \ 201 |MISC2_PCLKEN_TIMER \ 202 |MISC2_PCLKEN_MISC \ 203 |MISC2_PCLKEN_MISC2 \ 204 |MISC2_PCLKEN_PMU \ 205 |MISC2_PCLKEN_RTC \ 206 |MISC2_PCLKEN_ANA \ 207 |MISC2_PCLKEN_U32K0 \ 208 |MISC2_PCLKEN_U32K1 \ 209 |MISC2_PCLKEN_SPI2) 210 211 /***** PLLStatus (CLK_GetPLLLockStatus) *****/ 212 #define CLK_STATUS_LOCKL ANA_COMPOUT_LOCKL 213 #define CLK_STATUS_LOCKH ANA_COMPOUT_LOCKH 214 215 216 /* Private macros ------------------------------------------------------------*/ 217 #define IS_CLK_TYPE(__TYPE__) ((((__TYPE__) & CLK_TYPE_Msk) != 0UL) &&\ 218 (((__TYPE__) & ~CLK_TYPE_Msk) == 0UL)) 219 220 #define IS_CLK_AHBSRC(__AHBSRC__) (((__AHBSRC__) == CLK_AHBSEL_6_5MRC) ||\ 221 ((__AHBSRC__) == CLK_AHBSEL_6_5MXTAL) ||\ 222 ((__AHBSRC__) == CLK_AHBSEL_HSPLL) ||\ 223 ((__AHBSRC__) == CLK_AHBSEL_RTCCLK) ||\ 224 ((__AHBSRC__) == CLK_AHBSEL_LSPLL)) 225 226 #define IS_CLK_PLLLSRC(__PLLLSRC__) (((__PLLLSRC__) == CLK_PLLLSRC_RCL) ||\ 227 ((__PLLLSRC__) == CLK_PLLLSRC_XTALL)) 228 229 #define IS_CLK_PLLLSTA(__PLLLSTA__) (((__PLLLSTA__) == CLK_PLLL_ON) ||\ 230 ((__PLLLSTA__) == CLK_PLLL_OFF)) 231 232 #define IS_CLK_PLLLFRQ(__PLLLFRQ__) (((__PLLLFRQ__) == CLK_PLLL_26_2144MHz) ||\ 233 ((__PLLLFRQ__) == CLK_PLLL_13_1072MHz) ||\ 234 ((__PLLLFRQ__) == CLK_PLLL_6_5536MHz) ||\ 235 ((__PLLLFRQ__) == CLK_PLLL_3_2768MHz) ||\ 236 ((__PLLLFRQ__) == CLK_PLLL_1_6384MHz) ||\ 237 ((__PLLLFRQ__) == CLK_PLLL_0_8192MHz) ||\ 238 ((__PLLLFRQ__) == CLK_PLLL_0_4096MHz) ||\ 239 ((__PLLLFRQ__) == CLK_PLLL_0_2048MHz)) 240 241 #define IS_CLK_PLLHSRC(__PLLHSRC__) (((__PLLHSRC__) == CLK_PLLHSRC_RCH) ||\ 242 ((__PLLHSRC__) == CLK_PLLHSRC_XTALH)) 243 244 #define IS_CLK_PLLHSTA(__PLLHSTA__) (((__PLLHSTA__) == CLK_PLLH_ON) ||\ 245 ((__PLLHSTA__) == CLK_PLLH_OFF)) 246 247 #define IS_CLK_PLLHFRQ(__PLLHSRC__) (((__PLLHSRC__) == CLK_PLLH_13_1072MHz) ||\ 248 ((__PLLHSRC__) == CLK_PLLH_16_384MHz) ||\ 249 ((__PLLHSRC__) == CLK_PLLH_19_6608MHz) ||\ 250 ((__PLLHSRC__) == CLK_PLLH_22_9376MHz) ||\ 251 ((__PLLHSRC__) == CLK_PLLH_26_2144MHz) ||\ 252 ((__PLLHSRC__) == CLK_PLLH_29_4912MHz) ||\ 253 ((__PLLHSRC__) == CLK_PLLH_32_768MHz) ||\ 254 ((__PLLHSRC__) == CLK_PLLH_36_0448MHz) ||\ 255 ((__PLLHSRC__) == CLK_PLLH_39_3216MHz) ||\ 256 ((__PLLHSRC__) == CLK_PLLH_42_5984MHz) ||\ 257 ((__PLLHSRC__) == CLK_PLLH_45_8752MHz) ||\ 258 ((__PLLHSRC__) == CLK_PLLH_49_152MHz)) 259 260 #define IS_CLK_XTALHSTA(__XTALHSTA__) (((__XTALHSTA__) == CLK_XTALH_ON) ||\ 261 ((__XTALHSTA__) == CLK_XTALH_OFF)) 262 263 #define IS_CLK_RTCSRC(__RTCSRC__) (((__RTCSRC__) == CLK_RTCCLKSRC_XTALL) ||\ 264 ((__RTCSRC__) == CLK_RTCCLKSRC_RCL)) 265 266 #define IS_CLK_RTCDIV(__RTCDIV__) (((__RTCDIV__) == CLK_RTCCLKDIV_1) ||\ 267 ((__RTCDIV__) == CLK_RTCCLKDIV_4)) 268 269 #define IS_CLK_HCLKDIV(__HCLKDIV__) (((__HCLKDIV__) > 0UL) &&\ 270 ((__HCLKDIV__) < 257UL)) 271 272 #define IS_CLK_PCLKDIV(__PCLKDIV__) (((__PCLKDIV__) > 0UL) &&\ 273 ((__PCLKDIV__) < 257UL)) 274 275 #define IS_CLK_AHBPERIPHRAL(__AHBPERIPHRAL__) ((((__AHBPERIPHRAL__) & CLK_AHBPERIPHRAL_ALL) != 0UL) &&\ 276 (((__AHBPERIPHRAL__) & ~CLK_AHBPERIPHRAL_ALL) == 0UL)) 277 278 #define IS_CLK_APBPERIPHRAL(__APBPERIPHRAL__) ((((__APBPERIPHRAL__) & CLK_APBPERIPHRAL_ALL) != 0UL) &&\ 279 (((__APBPERIPHRAL__) & ~CLK_APBPERIPHRAL_ALL) == 0UL)) 280 281 #define IS_CLK_PLLLOCK(__PLLLOCK__) (((__PLLLOCK__) == ANA_COMPOUT_LOCKL) ||\ 282 ((__PLLLOCK__) == ANA_COMPOUT_LOCKH)) 283 /* Exported Functions ------------------------------------------------------- */ 284 /* CLK Exported Functions Group1: 285 Initialization and functions ---------------*/ 286 void CLK_ClockConfig(CLK_InitTypeDef *CLK_ClkInitStruct); 287 288 /* CLK Exported Functions Group2: 289 Peripheral Control -------------------------*/ 290 void CLK_AHBPeriphralCmd(uint32_t Periphral, uint32_t NewState); 291 void CLK_APBPeriphralCmd(uint32_t Periphral, uint32_t NewState); 292 /* CLK Exported Functions Group3: 293 Get clock/configuration information --------*/ 294 uint32_t CLK_GetHCLKFreq(void); 295 uint32_t CLK_GetPCLKFreq(void); 296 void CLK_GetClockConfig(CLK_InitTypeDef *CLK_ClkInitStruct); 297 uint8_t CLK_GetXTALHStatus(void); 298 uint8_t CLK_GetXTALLStatus(void); 299 uint8_t CLK_GetPLLLockStatus(uint32_t PLLStatus); 300 301 #ifdef __cplusplus 302 } 303 #endif 304 305 #endif /* __LIB_CLK_H */ 306 307 /*********************************** END OF FILE ******************************/ 308