1 /** 2 ****************************************************************************** 3 * @file lib_dma.h 4 * @author Application Team 5 * @version V4.4.0 6 * @date 2018-09-27 7 * @brief DMA library. 8 ****************************************************************************** 9 * @attention 10 * 11 ****************************************************************************** 12 */ 13 #ifndef __LIB_DMA_H 14 #define __LIB_DMA_H 15 16 #ifdef __cplusplus 17 extern "C" { 18 #endif 19 20 #include "target.h" 21 22 //Channel 23 #define DMA_CHANNEL_0 0 24 #define DMA_CHANNEL_1 1 25 #define DMA_CHANNEL_2 2 26 #define DMA_CHANNEL_3 3 27 28 typedef struct 29 { 30 uint32_t DestAddr; /* destination address */ 31 uint32_t SrcAddr; /* source address */ 32 uint8_t FrameLen; /* Frame length */ 33 uint8_t PackLen; /* Package length */ 34 uint32_t ContMode; /* Continuous mode */ 35 uint32_t TransMode; /* Transfer mode */ 36 uint32_t ReqSrc; /* DMA request source */ 37 uint32_t DestAddrMode; /* Destination address mode */ 38 uint32_t SrcAddrMode; /* Source address mode */ 39 uint32_t TransSize; /* Transfer size mode */ 40 } DMA_InitType; 41 //ContMode 42 #define DMA_CONTMODE_ENABLE DMA_CTL_CONT 43 #define DMA_CONTMODE_DISABLE 0 44 //TransMode 45 #define DMA_TRANSMODE_SINGLE 0 46 #define DMA_TRANSMODE_PACK DMA_CTL_TMODE 47 //ReqSrc 48 #define DMA_REQSRC_SOFT DMA_CTL_DMASEL_SOFT 49 #define DMA_REQSRC_UART0TX DMA_CTL_DMASEL_UART0TX 50 #define DMA_REQSRC_UART0RX DMA_CTL_DMASEL_UART0RX 51 #define DMA_REQSRC_UART1TX DMA_CTL_DMASEL_UART1TX 52 #define DMA_REQSRC_UART1RX DMA_CTL_DMASEL_UART1RX 53 #define DMA_REQSRC_UART2TX DMA_CTL_DMASEL_UART2TX 54 #define DMA_REQSRC_UART2RX DMA_CTL_DMASEL_UART2RX 55 #define DMA_REQSRC_UART3TX DMA_CTL_DMASEL_UART3TX 56 #define DMA_REQSRC_UART3RX DMA_CTL_DMASEL_UART3RX 57 #define DMA_REQSRC_UART4TX DMA_CTL_DMASEL_UART4TX 58 #define DMA_REQSRC_UART4RX DMA_CTL_DMASEL_UART4RX 59 #define DMA_REQSRC_UART5TX DMA_CTL_DMASEL_UART5TX 60 #define DMA_REQSRC_UART5RX DMA_CTL_DMASEL_UART5RX 61 #define DMA_REQSRC_ISO78160TX DMA_CTL_DMASEL_ISO78160TX 62 #define DMA_REQSRC_ISO78160RX DMA_CTL_DMASEL_ISO78160RX 63 #define DMA_REQSRC_ISO78161TX DMA_CTL_DMASEL_ISO78161TX 64 #define DMA_REQSRC_ISO78161RX DMA_CTL_DMASEL_ISO78161RX 65 #define DMA_REQSRC_TIMER0 DMA_CTL_DMASEL_TIMER0 66 #define DMA_REQSRC_TIMER1 DMA_CTL_DMASEL_TIMER1 67 #define DMA_REQSRC_TIMER2 DMA_CTL_DMASEL_TIMER2 68 #define DMA_REQSRC_TIMER3 DMA_CTL_DMASEL_TIMER3 69 #define DMA_REQSRC_SPI1TX DMA_CTL_DMASEL_SPI1TX 70 #define DMA_REQSRC_SPI1RX DMA_CTL_DMASEL_SPI1RX 71 #define DMA_REQSRC_U32K0 DMA_CTL_DMASEL_U32K0 72 #define DMA_REQSRC_U32K1 DMA_CTL_DMASEL_U32K1 73 #define DMA_REQSRC_CMP1 DMA_CTL_DMASEL_CMP1 74 #define DMA_REQSRC_CMP2 DMA_CTL_DMASEL_CMP2 75 #define DMA_REQSRC_SPI2TX DMA_CTL_DMASEL_SPI2TX 76 #define DMA_REQSRC_SPI2RX DMA_CTL_DMASEL_SPI2RX 77 //DestAddrMode 78 #define DMA_DESTADDRMODE_FIX DMA_CxCTL_DMODE_FIX 79 #define DMA_DESTADDRMODE_PEND DMA_CxCTL_DMODE_PEND 80 #define DMA_DESTADDRMODE_FEND DMA_CxCTL_DMODE_FEND 81 //SrcAddrMode 82 #define DMA_SRCADDRMODE_FIX DMA_CxCTL_SMODE_FIX 83 #define DMA_SRCADDRMODE_PEND DMA_CxCTL_SMODE_PEND 84 #define DMA_SRCADDRMODE_FEND DMA_CxCTL_SMODE_FEND 85 //TransSize 86 #define DMA_TRANSSIZE_BYTE DMA_CxCTL_SIZE_BYTE 87 #define DMA_TRANSSIZE_HWORD DMA_CxCTL_SIZE_HWORD 88 #define DMA_TRANSSIZE_WORD DMA_CxCTL_SIZE_WORD 89 90 typedef struct 91 { 92 uint32_t Mode; /* AES mode */ 93 uint32_t Direction; /* Direction */ 94 uint32_t *KeyStr; /* AES key */ 95 } DMA_AESInitType; 96 //AES MODE 97 #define DMA_AESMODE_128 DMA_AESCTL_MODE_AES128 98 #define DMA_AESMODE_192 DMA_AESCTL_MODE_AES192 99 #define DMA_AESMODE_256 DMA_AESCTL_MODE_AES256 100 //AES Direction 101 #define DMA_AESDIRECTION_ENCODE DMA_AESCTL_ENC 102 #define DMA_AESDIRECTION_DECODE 0 103 104 //INT 105 #define DMA_INT_C3DA DMA_IE_C3DAIE 106 #define DMA_INT_C2DA DMA_IE_C2DAIE 107 #define DMA_INT_C1DA DMA_IE_C1DAIE 108 #define DMA_INT_C0DA DMA_IE_C0DAIE 109 #define DMA_INT_C3FE DMA_IE_C3FEIE 110 #define DMA_INT_C2FE DMA_IE_C2FEIE 111 #define DMA_INT_C1FE DMA_IE_C1FEIE 112 #define DMA_INT_C0FE DMA_IE_C0FEIE 113 #define DMA_INT_C3PE DMA_IE_C3PEIE 114 #define DMA_INT_C2PE DMA_IE_C2PEIE 115 #define DMA_INT_C1PE DMA_IE_C1PEIE 116 #define DMA_INT_C0PE DMA_IE_C0PEIE 117 #define DMA_INT_Msk (0xFFFUL) 118 119 //INTSTS 120 #define DMA_INTSTS_C3DA DMA_STS_C3DA 121 #define DMA_INTSTS_C2DA DMA_STS_C2DA 122 #define DMA_INTSTS_C1DA DMA_STS_C1DA 123 #define DMA_INTSTS_C0DA DMA_STS_C0DA 124 #define DMA_INTSTS_C3FE DMA_STS_C3FE 125 #define DMA_INTSTS_C2FE DMA_STS_C2FE 126 #define DMA_INTSTS_C1FE DMA_STS_C1FE 127 #define DMA_INTSTS_C0FE DMA_STS_C0FE 128 #define DMA_INTSTS_C3PE DMA_STS_C3PE 129 #define DMA_INTSTS_C2PE DMA_STS_C2PE 130 #define DMA_INTSTS_C1PE DMA_STS_C1PE 131 #define DMA_INTSTS_C0PE DMA_STS_C0PE 132 #define DMA_INTSTS_C3BUSY DMA_STS_C3BUSY 133 #define DMA_INTSTS_C2BUSY DMA_STS_C2BUSY 134 #define DMA_INTSTS_C1BUSY DMA_STS_C1BUSY 135 #define DMA_INTSTS_C0BUSY DMA_STS_C0BUSY 136 #define DMA_INTSTS_Msk (0xFFF0UL) 137 138 /* Private macros ------------------------------------------------------------*/ 139 #define IS_DMA_CHANNEL(__CH__) (((__CH__) == DMA_CHANNEL_0) ||\ 140 ((__CH__) == DMA_CHANNEL_1) ||\ 141 ((__CH__) == DMA_CHANNEL_2) ||\ 142 ((__CH__) == DMA_CHANNEL_3)) 143 144 #define IS_DMA_ALIGNEDADDR_WORD(__ADDRW__) (((__ADDRW__) & 0x3U) == 0U) 145 146 #define IS_DMA_ALIGNEDADDR_HWORD(__ADDRHW__) (((__ADDRHW__) & 0x1U) == 0U) 147 148 #define IS_DMA_CONTMOD(__CONTMOD__) (((__CONTMOD__) == DMA_CONTMODE_ENABLE) ||\ 149 ((__CONTMOD__) == DMA_CONTMODE_DISABLE)) 150 151 #define IS_DMA_TRANSMOD(__TRANSMOD__) (((__TRANSMOD__) == DMA_TRANSMODE_SINGLE) ||\ 152 ((__TRANSMOD__) == DMA_TRANSMODE_PACK)) 153 154 #define IS_DMA_REQSRC(__REQSRC__) (((__REQSRC__) == DMA_REQSRC_SOFT) ||\ 155 ((__REQSRC__) == DMA_REQSRC_UART0TX) ||\ 156 ((__REQSRC__) == DMA_REQSRC_UART0RX) ||\ 157 ((__REQSRC__) == DMA_REQSRC_UART1TX) ||\ 158 ((__REQSRC__) == DMA_REQSRC_UART1RX) ||\ 159 ((__REQSRC__) == DMA_REQSRC_UART2TX) ||\ 160 ((__REQSRC__) == DMA_REQSRC_UART2RX) ||\ 161 ((__REQSRC__) == DMA_REQSRC_UART3TX) ||\ 162 ((__REQSRC__) == DMA_REQSRC_UART3RX) ||\ 163 ((__REQSRC__) == DMA_REQSRC_UART4TX) ||\ 164 ((__REQSRC__) == DMA_REQSRC_UART4RX) ||\ 165 ((__REQSRC__) == DMA_REQSRC_UART5TX) ||\ 166 ((__REQSRC__) == DMA_REQSRC_UART5RX) ||\ 167 ((__REQSRC__) == DMA_REQSRC_ISO78160TX) ||\ 168 ((__REQSRC__) == DMA_REQSRC_ISO78160RX) ||\ 169 ((__REQSRC__) == DMA_REQSRC_ISO78161TX) ||\ 170 ((__REQSRC__) == DMA_REQSRC_ISO78161RX) ||\ 171 ((__REQSRC__) == DMA_REQSRC_TIMER0) ||\ 172 ((__REQSRC__) == DMA_REQSRC_TIMER1) ||\ 173 ((__REQSRC__) == DMA_REQSRC_TIMER2) ||\ 174 ((__REQSRC__) == DMA_REQSRC_TIMER3) ||\ 175 ((__REQSRC__) == DMA_REQSRC_SPI1TX) ||\ 176 ((__REQSRC__) == DMA_REQSRC_SPI1RX) ||\ 177 ((__REQSRC__) == DMA_REQSRC_U32K0) ||\ 178 ((__REQSRC__) == DMA_REQSRC_U32K1) ||\ 179 ((__REQSRC__) == DMA_REQSRC_CMP1) ||\ 180 ((__REQSRC__) == DMA_REQSRC_CMP2) ||\ 181 ((__REQSRC__) == DMA_REQSRC_SPI2TX) ||\ 182 ((__REQSRC__) == DMA_REQSRC_SPI2RX)) 183 184 #define IS_DMA_DESTADDRMOD(__DAM__) (((__DAM__) == DMA_DESTADDRMODE_FIX) ||\ 185 ((__DAM__) == DMA_DESTADDRMODE_PEND) ||\ 186 ((__DAM__) == DMA_DESTADDRMODE_FEND)) 187 188 #define IS_DMA_SRCADDRMOD(__SAM__) (((__SAM__) == DMA_SRCADDRMODE_FIX) ||\ 189 ((__SAM__) == DMA_SRCADDRMODE_PEND) ||\ 190 ((__SAM__) == DMA_SRCADDRMODE_FEND)) 191 192 #define IS_DMA_TRANSSIZE(__TSIZE__) (((__TSIZE__) == DMA_TRANSSIZE_BYTE) ||\ 193 ((__TSIZE__) == DMA_TRANSSIZE_HWORD) ||\ 194 ((__TSIZE__) == DMA_TRANSSIZE_WORD)) 195 196 #define IS_DMA_AESMOD(__AESMOD__) (((__AESMOD__) == DMA_AESMODE_128) ||\ 197 ((__AESMOD__) == DMA_AESMODE_192) ||\ 198 ((__AESMOD__) == DMA_AESMODE_256)) 199 200 #define IS_DMA_AESDIR(__AESDIR__) (((__AESDIR__) == DMA_AESDIRECTION_ENCODE) ||\ 201 ((__AESDIR__) == DMA_AESDIRECTION_DECODE)) 202 203 #define IS_DMA_INT(__INT__) ((((__INT__) & DMA_INT_Msk) != 0U) &&\ 204 (((__INT__) & ~DMA_INT_Msk) == 0U)) 205 206 #define IS_DMA_INTFLAGR(__INTFLAGR__) (((__INTFLAGR__) == DMA_INTSTS_C3DA) ||\ 207 ((__INTFLAGR__) == DMA_INTSTS_C2DA) ||\ 208 ((__INTFLAGR__) == DMA_INTSTS_C1DA) ||\ 209 ((__INTFLAGR__) == DMA_INTSTS_C0DA) ||\ 210 ((__INTFLAGR__) == DMA_INTSTS_C3FE) ||\ 211 ((__INTFLAGR__) == DMA_INTSTS_C2FE) ||\ 212 ((__INTFLAGR__) == DMA_INTSTS_C1FE) ||\ 213 ((__INTFLAGR__) == DMA_INTSTS_C0FE) ||\ 214 ((__INTFLAGR__) == DMA_INTSTS_C3PE) ||\ 215 ((__INTFLAGR__) == DMA_INTSTS_C2PE) ||\ 216 ((__INTFLAGR__) == DMA_INTSTS_C1PE) ||\ 217 ((__INTFLAGR__) == DMA_INTSTS_C0PE) ||\ 218 ((__INTFLAGR__) == DMA_INTSTS_C3BUSY) ||\ 219 ((__INTFLAGR__) == DMA_INTSTS_C2BUSY) ||\ 220 ((__INTFLAGR__) == DMA_INTSTS_C1BUSY) ||\ 221 ((__INTFLAGR__) == DMA_INTSTS_C0BUSY)) 222 223 #define IS_DMA_INTFLAGC(__INTFLAGC__) ((((__INTFLAGC__) & DMA_INTSTS_Msk) != 0U) &&\ 224 (((__INTFLAGC__) & ~DMA_INTSTS_Msk) == 0U)) 225 226 /* Exported Functions ------------------------------------------------------- */ 227 /* DMA Exported Functions Group1: 228 (De)Initialization ------------------------*/ 229 void DMA_DeInit(uint32_t Channel); 230 void DMA_Init(DMA_InitType *InitStruct, uint32_t Channel); 231 void DMA_AESDeInit(void); 232 void DMA_AESInit(DMA_AESInitType *InitStruct); 233 /* DMA Exported Functions Group2: 234 Interrupt (flag) --------------------------*/ 235 void DMA_INTConfig(uint32_t INTMask, uint32_t NewState); 236 uint8_t DMA_GetINTStatus(uint32_t INTMask); 237 void DMA_ClearINTStatus(uint32_t INTMask); 238 /* DMA Exported Functions Group3: 239 MISC Configuration ------------------------*/ 240 void DMA_Cmd(uint32_t Channel, uint32_t NewState); 241 void DMA_AESCmd(uint32_t NewState); 242 void DMA_StopTransmit(uint32_t Channel, uint32_t NewState); 243 uint8_t DMA_GetFrameLenTransferred(uint32_t Channel); 244 uint8_t DMA_GetPackLenTransferred(uint32_t Channel); 245 246 247 #ifdef __cplusplus 248 } 249 #endif 250 251 #endif /* __LIB_DMA_H */ 252 253 /*********************************** END OF FILE ******************************/ 254