1 /** 2 ****************************************************************************** 3 * @file lib_pmu.h 4 * @author Application Team 5 * @version V4.4.0 6 * @date 2018-09-27 7 * @brief PMU library. 8 ****************************************************************************** 9 * @attention 10 * 11 ****************************************************************************** 12 */ 13 #ifndef __LIB_PMU_H 14 #define __LIB_PMU_H 15 16 #ifdef __cplusplus 17 extern "C" { 18 #endif 19 20 #include "target.h" 21 22 /** 23 * Deep-sleep low-power configuration 24 */ 25 typedef struct 26 { 27 uint32_t COMP1Power; /* Comparator 1 power control */ 28 uint32_t COMP2Power; /* Comparator 2 power control */ 29 uint32_t TADCPower; /* Tiny ADC power control */ 30 uint32_t BGPPower; /* BGP power control */ 31 uint32_t AVCCPower; /* AVCC power control */ 32 uint32_t LCDPower; /* LCD controller power control */ 33 uint32_t VDCINDetector; /* VDCIN detector control */ 34 uint32_t VDDDetector; /* VDD detector control */ 35 uint32_t AHBPeriphralDisable; /* AHB Periphral clock disable selection */ 36 uint32_t APBPeriphralDisable; /* APB Periphral clock disable selection */ 37 } PMU_LowPWRTypeDef; 38 39 40 /* COMP1Power */ 41 #define PMU_COMP1PWR_ON (ANA_REG3_CMP1PDN) 42 #define PMU_COMP1PWR_OFF (0) 43 #define IS_PMU_COMP1PWR(__COMP1PWR__) (((__COMP1PWR__) == PMU_COMP1PWR_ON) ||\ 44 ((__COMP1PWR__) == PMU_COMP1PWR_OFF)) 45 /* COMP2Power */ 46 #define PMU_COMP2PWR_ON (ANA_REG3_CMP2PDN) 47 #define PMU_COMP2PWR_OFF (0) 48 #define IS_PMU_COMP2PWR(__COMP2PWR__) (((__COMP2PWR__) == PMU_COMP2PWR_ON) ||\ 49 ((__COMP2PWR__) == PMU_COMP2PWR_OFF)) 50 /* TADCPower */ 51 #define PMU_TADCPWR_ON (ANA_REGF_PDNADT) 52 #define PMU_TADCPWR_OFF (0) 53 #define IS_PMU_TADCPWR(__TADCPWR__) (((__TADCPWR__) == PMU_TADCPWR_ON) ||\ 54 ((__TADCPWR__) == PMU_TADCPWR_OFF)) 55 /* BGPPower */ 56 #define PMU_BGPPWR_ON (0) 57 #define PMU_BGPPWR_OFF (ANA_REG3_BGPPD) 58 #define IS_PMU_BGPPWR(__BGPPWR__) (((__BGPPWR__) == PMU_BGPPWR_ON) ||\ 59 ((__BGPPWR__) == PMU_BGPPWR_OFF)) 60 /* AVCCPower */ 61 #define PMU_AVCCPWR_ON (0) 62 #define PMU_AVCCPWR_OFF (ANA_REG8_PD_AVCCLDO) 63 #define IS_PMU_AVCCPWR(__AVCCPWR__) (((__AVCCPWR__) == PMU_AVCCPWR_ON) ||\ 64 ((__AVCCPWR__) == PMU_AVCCPWR_OFF)) 65 /* LCDPower */ 66 #define PMU_LCDPWER_ON (LCD_CTRL_EN) 67 #define PMU_LCDPWER_OFF (0) 68 #define IS_PMU_LCDPWER(__LCDPWER__) (((__LCDPWER__) == PMU_LCDPWER_ON) ||\ 69 ((__LCDPWER__) == PMU_LCDPWER_OFF)) 70 /* VDCINDetector */ 71 #define PMU_VDCINDET_ENABLE (0) 72 #define PMU_VDCINDET_DISABLE (ANA_REGA_PD_VDCINDET) 73 #define IS_PMU_VDCINDET(__VDCINDET__) (((__VDCINDET__) == PMU_VDCINDET_ENABLE) ||\ 74 ((__VDCINDET__) == PMU_VDCINDET_DISABLE)) 75 76 /* VDDDetector */ 77 #define PMU_VDDDET_ENABLE (0) 78 #define PMU_VDDDET_DISABLE (ANA_REG9_PDDET) 79 #define IS_PMU_VDDDET(__VDDDET__) (((__VDDDET__) == PMU_VDDDET_ENABLE) ||\ 80 ((__VDDDET__) == PMU_VDDDET_DISABLE)) 81 82 /* APBPeriphralDisable */ 83 #define PMU_APB_ALL (MISC2_PCLKEN_DMA \ 84 |MISC2_PCLKEN_I2C \ 85 |MISC2_PCLKEN_SPI1 \ 86 |MISC2_PCLKEN_UART0 \ 87 |MISC2_PCLKEN_UART1 \ 88 |MISC2_PCLKEN_UART2 \ 89 |MISC2_PCLKEN_UART3 \ 90 |MISC2_PCLKEN_UART4 \ 91 |MISC2_PCLKEN_UART5 \ 92 |MISC2_PCLKEN_ISO78160\ 93 |MISC2_PCLKEN_ISO78161\ 94 |MISC2_PCLKEN_TIMER \ 95 |MISC2_PCLKEN_MISC \ 96 |MISC2_PCLKEN_U32K0 \ 97 |MISC2_PCLKEN_U32K1 \ 98 |MISC2_PCLKEN_SPI2) 99 #define PMU_APB_DMA MISC2_PCLKEN_DMA 100 #define PMU_APB_I2C MISC2_PCLKEN_I2C 101 #define PMU_APB_SPI1 MISC2_PCLKEN_SPI1 102 #define PMU_APB_UART0 MISC2_PCLKEN_UART0 103 #define PMU_APB_UART1 MISC2_PCLKEN_UART1 104 #define PMU_APB_UART2 MISC2_PCLKEN_UART2 105 #define PMU_APB_UART3 MISC2_PCLKEN_UART3 106 #define PMU_APB_UART4 MISC2_PCLKEN_UART4 107 #define PMU_APB_UART5 MISC2_PCLKEN_UART5 108 #define PMU_APB_ISO78160 MISC2_PCLKEN_ISO78160 109 #define PMU_APB_ISO78161 MISC2_PCLKEN_ISO78161 110 #define PMU_APB_TIMER MISC2_PCLKEN_TIMER 111 #define PMU_APB_MISC MISC2_PCLKEN_MISC 112 #define PMU_APB_U32K0 MISC2_PCLKEN_U32K0 113 #define PMU_APB_U32K1 MISC2_PCLKEN_U32K1 114 #define PMU_APB_SPI2 MISC2_PCLKEN_SPI2 115 /* AHBPeriphralDisable */ 116 #define PMU_AHB_ALL (MISC2_HCLKEN_DMA \ 117 |MISC2_HCLKEN_GPIO \ 118 |MISC2_HCLKEN_LCD \ 119 |MISC2_HCLKEN_CRYPT) 120 #define PMU_AHB_DMA MISC2_HCLKEN_DMA 121 #define PMU_AHB_GPIO MISC2_HCLKEN_GPIO 122 #define PMU_AHB_LCD MISC2_HCLKEN_LCD 123 #define PMU_AHB_CRYPT MISC2_HCLKEN_CRYPT 124 125 //PMU interrupt 126 #define PMU_INT_IOAEN PMU_CONTROL_INT_IOA_EN 127 #define PMU_INT_32K PMU_CONTROL_INT_32K_EN 128 #define PMU_INT_6M PMU_CONTROL_INT_6M_EN 129 #define PMU_INT_Msk (PMU_INT_IOAEN \ 130 |PMU_INT_32K \ 131 |PMU_INT_6M) 132 #define IS_PMU_INT(__INT__) ((((__INT__)&PMU_INT_Msk) != 0U) &&\ 133 (((__INT__)&(~PMU_INT_Msk)) == 0U)) 134 135 //INTStatus 136 #define PMU_INTSTS_32K PMU_STS_INT_32K 137 #define PMU_INTSTS_6M PMU_STS_INT_6M 138 #define PMU_INTSTS_EXTRST PMU_STS_EXTRST 139 #define PMU_INTSTS_PORST PMU_STS_PORST 140 #define PMU_INTSTS_DPORST PMU_STS_DPORST 141 #define PMU_INTSTS_Msk (PMU_INTSTS_32K \ 142 |PMU_INTSTS_6M \ 143 |PMU_INTSTS_EXTRST \ 144 |PMU_INTSTS_PORST \ 145 |PMU_INTSTS_DPORST) 146 #define IS_PMU_INTFLAGR(__INTFLAG__) (((__INTFLAG__) == PMU_INTSTS_32K) ||\ 147 ((__INTFLAG__) == PMU_INTSTS_6M) ||\ 148 ((__INTFLAG__) == PMU_INTSTS_EXTRST) ||\ 149 ((__INTFLAG__) == PMU_INTSTS_PORST) ||\ 150 ((__INTFLAG__) == PMU_INTSTS_DPORST)) 151 152 #define IS_PMU_INTFLAGC(__INTFLAG__) ((((__INTFLAG__)&PMU_INTSTS_Msk) != 0U) &&\ 153 (((__INTFLAG__)&(~PMU_INTSTS_Msk)) == 0U)) 154 155 156 157 //Status 158 #define PMU_STS_32K PMU_STS_EXIST_32K 159 #define PMU_STS_6M PMU_STS_EXIST_6M 160 #define IS_PMU_FLAG(__FLAG__) (((__FLAG__) == PMU_STS_32K) || ((__FLAG__) == PMU_STS_6M)) 161 162 //Wakeup_Event 163 #define IOA_DISABLE (0) 164 #define IOA_RISING (1) 165 #define IOA_FALLING (2) 166 #define IOA_HIGH (3) 167 #define IOA_LOW (4) 168 #define IOA_EDGEBOTH (5) 169 #define IS_PMU_WAKEUP(__WAKEUP__) (((__WAKEUP__) == IOA_DISABLE) ||\ 170 ((__WAKEUP__) == IOA_RISING) ||\ 171 ((__WAKEUP__) == IOA_FALLING) ||\ 172 ((__WAKEUP__) == IOA_HIGH) ||\ 173 ((__WAKEUP__) == IOA_LOW) ||\ 174 ((__WAKEUP__) == IOA_EDGEBOTH)) 175 176 /***** Wakeup_Event (PMU_SleepWKUSRC_Config_RTC) *****/ 177 #define PMU_RTCEVT_ACDONE RTC_INTSTS_INTSTS7 178 #define PMU_RTCEVT_WKUCNT RTC_INTSTS_INTSTS6 179 #define PMU_RTCEVT_MIDNIGHT RTC_INTSTS_INTSTS5 180 #define PMU_RTCEVT_WKUHOUR RTC_INTSTS_INTSTS4 181 #define PMU_RTCEVT_WKUMIN RTC_INTSTS_INTSTS3 182 #define PMU_RTCEVT_WKUSEC RTC_INTSTS_INTSTS2 183 #define PMU_RTCEVT_TIMEILLE RTC_INTSTS_INTSTS1 184 #define PMU_RTCEVT_Msk (PMU_RTCEVT_ACDONE \ 185 |PMU_RTCEVT_WKUCNT \ 186 |PMU_RTCEVT_MIDNIGHT \ 187 |PMU_RTCEVT_WKUHOUR \ 188 |PMU_RTCEVT_WKUMIN \ 189 |PMU_RTCEVT_WKUSEC \ 190 |PMU_RTCEVT_TIMEILLE) 191 #define IS_PMU_RTCEVT(__RTCEVT__) ((((__RTCEVT__)&PMU_RTCEVT_Msk) != 0U) &&\ 192 (((__RTCEVT__)&(~PMU_RTCEVT_Msk)) == 0U)) 193 194 195 /***** BATDisc (PMU_BATDischargeConfig) *****/ 196 #define PMU_BATRTC_DISC ANA_REG6_BATRTCDISC 197 #define IS_PMU_BATRTCDISC(__BATRTCDISC__) ((__BATRTCDISC__) == PMU_BATRTC_DISC) 198 199 /***** PowerThreshold (PMU_PowerAlarmTHConfig) *****/ 200 #define PMU_PWTH_4_5 ANA_REG8_VDDPVDSEL_0 201 #define PMU_PWTH_4_2 ANA_REG8_VDDPVDSEL_1 202 #define PMU_PWTH_3_9 ANA_REG8_VDDPVDSEL_2 203 #define PMU_PWTH_3_6 ANA_REG8_VDDPVDSEL_3 204 #define PMU_PWTH_3_2 ANA_REG8_VDDPVDSEL_4 205 #define PMU_PWTH_2_9 ANA_REG8_VDDPVDSEL_5 206 #define PMU_PWTH_2_6 ANA_REG8_VDDPVDSEL_6 207 #define PMU_PWTH_2_3 ANA_REG8_VDDPVDSEL_7 208 209 #define IS_PMU_PWTH(__PWTH__) (((__PWTH__) == PMU_PWTH_4_5) ||\ 210 ((__PWTH__) == PMU_PWTH_4_2) ||\ 211 ((__PWTH__) == PMU_PWTH_3_9) ||\ 212 ((__PWTH__) == PMU_PWTH_3_6) ||\ 213 ((__PWTH__) == PMU_PWTH_3_2) ||\ 214 ((__PWTH__) == PMU_PWTH_2_9) ||\ 215 ((__PWTH__) == PMU_PWTH_2_6) ||\ 216 ((__PWTH__) == PMU_PWTH_2_3)) 217 218 /***** RTCLDOSel (PMU_RTCLDOConfig) *****/ 219 #define PMU_RTCLDO_1_5 (0) 220 #define PMU_RTCLDO_1_2 ANA_REGA_RTCVSEL 221 222 /***** StatusMask (PMU_GetPowerStatus) *****/ 223 #define PMU_PWRSTS_AVCCLV ANA_COMPOUT_AVCCLV 224 #define PMU_PWRSTS_VDCINDROP ANA_COMPOUT_VDCINDROP 225 #define PMU_PWRSTS_VDDALARM ANA_COMPOUT_VDDALARM 226 227 /***** Debounce (PMU_PWRDropDEBConfig) *****/ 228 #define PMU_PWRDROP_DEB_0 ANA_CTRL_PWRDROPDEB_0 229 #define PMU_PWRDROP_DEB_1 ANA_CTRL_PWRDROPDEB_1 230 #define PMU_PWRDROP_DEB_2 ANA_CTRL_PWRDROPDEB_2 231 #define PMU_PWRDROP_DEB_3 ANA_CTRL_PWRDROPDEB_3 232 #define IS_PMU_PWRDROP_DEB(__DEB__) (((__DEB__) == PMU_PWRDROP_DEB_0) ||\ 233 ((__DEB__) == PMU_PWRDROP_DEB_1) ||\ 234 ((__DEB__) == PMU_PWRDROP_DEB_2) ||\ 235 ((__DEB__) == PMU_PWRDROP_DEB_3)) 236 237 /***** RSTSource (PMU_GetRSTSource) *****/ 238 #define PMU_RSTSRC_EXTRST PMU_STS_EXTRST 239 #define PMU_RSTSRC_PORST PMU_STS_PORST 240 #define PMU_RSTSRC_DPORST PMU_STS_DPORST 241 //#define PMU_RSTSRC_WDTRST PMU_WDTSTS_WDTSTS 242 #define IS_PMU_RSTSRC(__RSTSRC__) (((__RSTSRC__) == PMU_RSTSRC_EXTRST) ||\ 243 ((__RSTSRC__) == PMU_RSTSRC_PORST) ||\ 244 ((__RSTSRC__) == PMU_RSTSRC_DPORST) ) 245 246 /***** PMU_PDNDSleepConfig *****/ 247 //VDCIN_PDNS 248 #define PMU_VDCINPDNS_0 (0) 249 #define PMU_VDCINPDNS_1 (ANA_CTRL_PDNS) 250 #define IS_PMU_VDCINPDNS(__VDCINPDNS__) (((__VDCINPDNS__) == PMU_VDCINPDNS_0) ||\ 251 ((__VDCINPDNS__) == PMU_VDCINPDNS_1)) 252 //VDD_PDNS 253 #define PMU_VDDPDNS_0 (0) 254 #define PMU_VDDPDNS_1 (ANA_CTRL_PDNS2) 255 #define IS_PMU_VDDPDNS(__VDDPDNS__) (((__VDDPDNS__) == PMU_VDDPDNS_0) ||\ 256 ((__VDDPDNS__) == PMU_VDDPDNS_1)) 257 258 /* Exported Functions ------------------------------------------------------- */ 259 260 uint32_t PMU_EnterDSleepMode(void); 261 void PMU_EnterIdleMode(void); 262 uint32_t PMU_EnterSleepMode(void); 263 264 void PMU_INTConfig(uint32_t INTMask, uint32_t NewState); 265 uint8_t PMU_GetINTStatus(uint32_t INTMask); 266 void PMU_ClearINTStatus(uint32_t INTMask); 267 268 uint8_t PMU_GetStatus(uint32_t Mask); 269 uint16_t PMU_GetIOAAllINTStatus(void); 270 uint16_t PMU_GetIOAINTStatus(uint16_t INTMask); 271 void PMU_ClearIOAINTStatus(uint16_t INTMask); 272 273 void PMU_WakeUpPinConfig(uint32_t IOAx, uint32_t Wakeup_Event); 274 275 uint8_t PMU_EnterDSleep_LowPower(PMU_LowPWRTypeDef *InitStruct); 276 uint8_t PMU_EnterSleep_LowPower(PMU_LowPWRTypeDef *InitStruct); 277 #ifndef __GNUC__ 278 void PMU_EnterIdle_LowPower(void); 279 #endif 280 void PMU_SleepWKUSRC_Config_IOA(uint16_t IOAx, uint32_t Wakeup_Event, uint32_t Priority); 281 void PMU_SleepWKUSRC_Config_RTC(uint32_t Wakeup_Event, uint32_t Priority); 282 void PMU_DeepSleepWKUSRC_Config_IOA(uint16_t IOAx, uint32_t Wakeup_Event); 283 void PMU_DeepSleepWKUSRC_Config_RTC(uint32_t Wakeup_Event); 284 void PMU_PDNDSleepConfig(uint32_t VDCIN_PDNS, uint32_t VDD_PDNS); 285 286 /***** BGP functions *****/ 287 void PMU_BGP_Cmd(uint32_t NewState); 288 289 /***** VDD functions *****/ 290 void PMU_VDDAlarmTHConfig(uint32_t PowerThreshold); 291 uint8_t PMU_GetVDDALARMStatus(void); 292 void PMU_VDDDetectorCmd(uint32_t NewState); 293 294 /***** AVCC functions *****/ 295 void PMU_AVCC_Cmd(uint32_t NewState); 296 void PMU_AVCCOutput_Cmd(uint32_t NewState); 297 void PMU_AVCCLVDetector_Cmd(uint32_t NewState); 298 uint8_t PMU_GetAVCCLVStatus(void); 299 300 /***** VDCIN functions *****/ 301 void PMU_VDCINDetector_Cmd(uint32_t NewState); 302 uint8_t PMU_GetVDCINDropStatus(void); 303 304 /***** BAT functions *****/ 305 void PMU_BATDischargeConfig(uint32_t BATDisc, uint32_t NewState); 306 307 /***** Other functions *****/ 308 uint8_t PMU_GetModeStatus(void); 309 uint8_t PMU_GetPowerStatus(uint32_t StatusMask); 310 void PMU_PWRDropDEBConfig(uint32_t Debounce); 311 uint8_t PMU_GetRSTSource(uint32_t RSTSource); 312 313 #ifdef __cplusplus 314 } 315 #endif 316 317 #endif /* __LIB_PMU_H */ 318 319 /*********************************** END OF FILE ******************************/ 320