1 /**
2 ******************************************************************************
3 * @file lib_clk.c
4 * @author Application Team
5 * @version V4.4.0
6 * @date 2018-09-27
7 * @brief Clock library.
8 ******************************************************************************
9 * @attention
10 *
11 ******************************************************************************
12 */
13 #include "lib_clk.h"
14
15 __IO uint32_t ana_reg3_tmp;
16 /**
17 * @brief Initializes the CPU, AHB and APB buses clocks according to the specified
18 * parameters in the CLK_ClkInitStruct.
19 *
20 * @note This function performs the following:
21 * 1. If want to switch AHB clock source, enable BGP, enable 6.5M RC,
22 * AHB clock source switch to RCH first.
23 * 2. configure clock (except AHB clock source configuration). - optional
24 * 3. configure AHB clock source. - optional
25 * 4. HCLK/PCLK divider configuration. - optional
26 *
27 * @note CLK_InitTypeDef *CLK_ClkInitStruct
28 * [in]CLK_ClkInitStruct->ClockType, can use the ��|�� operator, the selection of parameters is as follows
29 * CLK_TYPE_ALL
30 * CLK_TYPE_AHBSRC
31 * CLK_TYPE_PLLL
32 * CLK_TYPE_PLLH
33 * CLK_TYPE_XTALH
34 * CLK_TYPE_RTCCLK
35 * CLK_TYPE_HCLK
36 * CLK_TYPE_PCLK
37 *
38 * CLK_TYPE_ALL All clocks' configurations is valid
39 * CLK_TYPE_AHBSRC CLK_ClkInitStruct->AHBSource(AHB Clock source configuration) is valid
40 * [in]CLK_ClkInitStruct->AHBSource:
41 * CLK_AHBSEL_6_5MRC
42 * CLK_AHBSEL_6_5MXTAL
43 * CLK_AHBSEL_HSPLL
44 * CLK_AHBSEL_RTCCLK
45 * CLK_AHBSEL_LSPLL
46 * CLK_TYPE_PLLL CLK_ClkInitStruct->PLLL(PLLL configuration) is valid
47 * [in]CLK_ClkInitStruct->PLLL.State:
48 * CLK_PLLL_ON (PLLL.Source/Frequency configuration is valid)
49 * CLK_PLLL_OFF (PLLL.Source/Frequency configuration is not valid)
50 * [in]CLK_ClkInitStruct->PLLL.Source:
51 * CLK_PLLLSRC_RCL
52 * CLK_PLLLSRC_XTALL
53 * [in]CLK_ClkInitStruct->PLLL.Frequency:
54 * CLK_PLLL_26_2144MHz
55 * CLK_PLLL_13_1072MHz
56 * CLK_PLLL_6_5536MHz
57 * CLK_PLLL_3_2768MHz
58 * CLK_PLLL_1_6384MHz
59 * CLK_PLLL_0_8192MHz
60 * CLK_PLLL_0_4096MHz
61 * CLK_PLLL_0_2048MHz
62 * CLK_TYPE_PLLH CLK_ClkInitStruct->PLLH(PLLH configuration) is valid
63 * [in]CLK_ClkInitStruct->PLLH.State:
64 * CLK_PLLH_ON (PLLH.Source/Frequency configuration is valid)
65 * CLK_PLLH_OFF (PLLH.Source/Frequency configuration is not valid)
66 * [in]CLK_ClkInitStruct->PLLH.Source:
67 * CLK_PLLHSRC_RCH
68 * CLK_PLLHSRC_XTALH
69 * [in]CLK_ClkInitStruct->PLLH.Frequency:
70 * CLK_PLLH_13_1072MHz
71 * CLK_PLLH_16_384MHz
72 * CLK_PLLH_19_6608MHz
73 * CLK_PLLH_22_9376MHz
74 * CLK_PLLH_26_2144MHz
75 * CLK_PLLH_29_4912MHz
76 * CLK_PLLH_32_768MHz
77 * CLK_PLLH_36_0448MHz
78 * CLK_PLLH_39_3216MHz
79 * CLK_PLLH_42_5984MHz
80 * CLK_PLLH_45_8752MHz
81 * CLK_PLLH_49_152MHz
82 * CLK_TYPE_XTALH CLK_ClkInitStruct->XTALH(XTALH configuration) is valid
83 * [in]CLK_ClkInitStruct->XTALH.State:
84 * CLK_XTALH_ON
85 * CLK_XTALH_OFF
86 * CLK_TYPE_RTCCLK CLK_ClkInitStruct->RTCCLK(RTCCLK configuration) is valid
87 * [in]CLK_ClkInitStruct->RTCCLK.Source:
88 * CLK_RTCCLKSRC_XTALL
89 * CLK_RTCCLKSRC_RCL
90 * [in]CLK_ClkInitStruct->RTCCLK.Divider:
91 * CLK_RTCCLKDIV_1
92 * CLK_RTCCLKDIV_4
93 * CLK_TYPE_HCLK CLK_ClkInitStruct->HCLK(AHB Clock(divider) configuration) is valid
94 * [in]CLK_ClkInitStruct->HCLK.Divider:
95 * 1 ~ 256
96 * CLK_TYPE_PCLK CLK_ClkInitStruct->PCLK(APB Clock(divider) configuration) is valid
97 * [in]CLK_ClkInitStruct->PCLK.Divider:
98 * 1 ~ 256
99 *
100 * @param CLK_ClkInitStruct pointer to an CLK_InitTypeDef structure that
101 * contains the configuration information for the clocks.
102 *
103 * @retval None
104 */
CLK_ClockConfig(CLK_InitTypeDef * CLK_ClkInitStruct)105 void CLK_ClockConfig(CLK_InitTypeDef *CLK_ClkInitStruct)
106 {
107 uint32_t tmp;
108
109 assert_parameters(IS_CLK_TYPE(CLK_ClkInitStruct->ClockType));
110
111 if (CLK_ClkInitStruct->ClockType & CLK_TYPE_AHBSRC)
112 {
113 /* Enable BGP */
114 ana_reg3_tmp &= ~ANA_REG3_BGPPD;
115 /* Enable 6.5M RC */
116 ana_reg3_tmp &= ~ANA_REG3_RCHPD;
117 ANA->REG3 = ana_reg3_tmp;
118 /* AHB clock source switch to RCH */
119 MISC2->CLKSEL = 0;
120 }
121
122 ANA->REGA &= ~BIT6;
123 ANA->REG2 &= ~BIT7;
124
125 /*---------- XTALH configuration ----------*/
126 if ((CLK_ClkInitStruct->ClockType) & CLK_TYPE_XTALH)
127 {
128 assert_parameters(IS_CLK_XTALHSTA(CLK_ClkInitStruct->XTALH.State));
129
130 /* XTALH state configure */
131 ana_reg3_tmp &= ~ANA_REG3_XOHPDN;
132 ana_reg3_tmp |= CLK_ClkInitStruct->XTALH.State;
133 ANA->REG3 = ana_reg3_tmp;
134 }
135
136 /*-------------------- PLLL configuration --------------------*/
137 if ((CLK_ClkInitStruct->ClockType) & CLK_TYPE_PLLL)
138 {
139 assert_parameters(IS_CLK_PLLLSRC(CLK_ClkInitStruct->PLLL.Source));
140 assert_parameters(IS_CLK_PLLLSTA(CLK_ClkInitStruct->PLLL.State));
141 assert_parameters(IS_CLK_PLLLFRQ(CLK_ClkInitStruct->PLLL.Frequency));
142
143 /* XTALL power up */
144 tmp = ANA->REG2;
145 tmp &= ~BIT7;
146 ANA->REG2 = tmp;
147
148 /* PLLL state configure */
149 if (CLK_ClkInitStruct->PLLL.State == CLK_PLLL_ON)
150 {
151 /* power up PLLL */
152 ana_reg3_tmp |= ANA_REG3_PLLLPDN;
153 ANA->REG3 = ana_reg3_tmp;
154
155 /* Configure PLLL frequency */
156 tmp = ANA->REG9;
157 tmp &= ~ANA_REG9_PLLLSEL;
158 tmp |= CLK_ClkInitStruct->PLLL.Frequency;
159 ANA->REG9 = tmp;
160
161 /* Configure PLLL input clock selection */
162 tmp = PMU->CONTROL;
163 tmp &= ~PMU_CONTROL_PLLL_SEL;
164 tmp |= CLK_ClkInitStruct->PLLL.Source;
165 PMU->CONTROL = tmp;
166 }
167 else
168 {
169 /* power down PLLL */
170 ana_reg3_tmp &= ~ANA_REG3_PLLLPDN;
171 ANA->REG3 = ana_reg3_tmp;
172 }
173 }
174
175 /*-------------------- PLLH configuration --------------------*/
176 if ((CLK_ClkInitStruct->ClockType) & CLK_TYPE_PLLH)
177 {
178 assert_parameters(IS_CLK_PLLHSRC(CLK_ClkInitStruct->PLLH.Source));
179 assert_parameters(IS_CLK_PLLHSTA(CLK_ClkInitStruct->PLLH.State));
180 assert_parameters(IS_CLK_PLLHFRQ(CLK_ClkInitStruct->PLLH.Frequency));
181
182 /* PLLH state configure */
183 if (CLK_ClkInitStruct->PLLH.State == CLK_PLLH_ON)
184 {
185 /* Power up PLLH */
186 ana_reg3_tmp |= ANA_REG3_PLLHPDN;
187 ANA->REG3 = ana_reg3_tmp;
188
189 /* Configure PLLH frequency */
190 tmp = ANA->REG9;
191 tmp &= ~ANA_REG9_PLLHSEL;
192 tmp |= CLK_ClkInitStruct->PLLH.Frequency;
193 ANA->REG9 = tmp;
194
195 /* Clock input source, XTALH, XOH power on*/
196 if (CLK_ClkInitStruct->PLLH.Source == CLK_PLLHSRC_XTALH)
197 {
198 ana_reg3_tmp |= ANA_REG3_XOHPDN;
199 ANA->REG3 = ana_reg3_tmp;
200 }
201
202 /* Configure PLLH input clock selection */
203 tmp = PMU->CONTROL;
204 tmp &= ~PMU_CONTROL_PLLH_SEL;
205 tmp |= CLK_ClkInitStruct->PLLH.Source;
206 PMU->CONTROL = tmp;
207 }
208 else
209 {
210 /* Power down PLLH */
211 ana_reg3_tmp &= ~ANA_REG3_PLLHPDN;
212 ANA->REG3 = ana_reg3_tmp;
213 }
214 }
215
216 /*---------- RTCCLK configuration ----------*/
217 if ((CLK_ClkInitStruct->ClockType) & CLK_TYPE_RTCCLK)
218 {
219 assert_parameters(IS_CLK_RTCSRC(CLK_ClkInitStruct->RTCCLK.Source));
220 assert_parameters(IS_CLK_RTCDIV(CLK_ClkInitStruct->RTCCLK.Divider));
221
222 /* RTCCLK source(optional) */
223 tmp = PMU->CONTROL;
224 tmp &= ~PMU_CONTROL_RTCLK_SEL;
225 tmp |= CLK_ClkInitStruct->RTCCLK.Source;
226 PMU->CONTROL = tmp;
227
228 /*----- RTCCLK Divider -----*/
229 RTC_PrescalerConfig(CLK_ClkInitStruct->RTCCLK.Divider);
230 }
231
232 /*---------- AHB clock source configuration ----------*/
233 if ((CLK_ClkInitStruct->ClockType) & CLK_TYPE_AHBSRC)
234 {
235 assert_parameters(IS_CLK_AHBSRC(CLK_ClkInitStruct->AHBSource));
236
237 /* clock source: 6.5M RC */
238 if (CLK_ClkInitStruct->AHBSource == CLK_AHBSEL_6_5MRC)
239 {
240 /* clock source configuration */
241 MISC2->CLKSEL = CLK_ClkInitStruct->AHBSource;
242 }
243
244 /* clock source: 6_5MXTAL */
245 else if (CLK_ClkInitStruct->AHBSource == CLK_AHBSEL_6_5MXTAL)
246 {
247 /* Power up 6.5M xtal */
248 ana_reg3_tmp |= ANA_REG3_XOHPDN;
249 ANA->REG3 = ana_reg3_tmp;
250 /* clock source configuration */
251 MISC2->CLKSEL = CLK_ClkInitStruct->AHBSource;
252 }
253
254 /* clock source: PLLH */
255 else if (CLK_ClkInitStruct->AHBSource == CLK_AHBSEL_HSPLL)
256 {
257 /* Power up PLLH */
258 ana_reg3_tmp |= ANA_REG3_PLLHPDN;
259 ANA->REG3 = ana_reg3_tmp;
260 /* while loop until PLLL is lock */
261 while (!(ANA->COMPOUT & ANA_COMPOUT_LOCKH))
262 {
263 }
264 /* clock source configuration */
265 MISC2->CLKSEL = CLK_ClkInitStruct->AHBSource;
266 }
267
268 /* clock source: PLLL */
269 else if (CLK_ClkInitStruct->AHBSource == CLK_AHBSEL_LSPLL)
270 {
271 /* Power up PLLL */
272 ana_reg3_tmp |= ANA_REG3_PLLLPDN;
273 ANA->REG3 = ana_reg3_tmp;
274 /* while loop until PLLL is lock */
275 while (!(ANA->COMPOUT & ANA_COMPOUT_LOCKL))
276 {
277 }
278 /* clock source configuration */
279 MISC2->CLKSEL = CLK_ClkInitStruct->AHBSource;
280 }
281 /* clock source: RTCCLK */
282 else
283 {
284 /* clock source configuration */
285 MISC2->CLKSEL = CLK_ClkInitStruct->AHBSource;
286 }
287 }
288
289 /*---------- HCLK configuration ----------*/
290 if ((CLK_ClkInitStruct->ClockType) & CLK_TYPE_HCLK)
291 {
292 assert_parameters(IS_CLK_HCLKDIV(CLK_ClkInitStruct->HCLK.Divider));
293
294 MISC2->CLKDIVH = (CLK_ClkInitStruct->HCLK.Divider) - 1;
295 }
296
297 /*---------- PCLK configuration ----------*/
298 if ((CLK_ClkInitStruct->ClockType) & CLK_TYPE_PCLK)
299 {
300 assert_parameters(IS_CLK_PCLKDIV(CLK_ClkInitStruct->PCLK.Divider));
301
302 MISC2->CLKDIVP = (CLK_ClkInitStruct->PCLK.Divider) - 1;
303 }
304 }
305
306 /**
307 * @brief AHB Periphral clock control.
308 * @param Periphral: can use the ��|�� operator
309 CLK_AHBPERIPHRAL_DMA
310 CLK_AHBPERIPHRAL_GPIO
311 CLK_AHBPERIPHRAL_LCD
312 CLK_AHBPERIPHRAL_CRYPT
313 NewState:
314 ENABLE
315 DISABLE
316 * @retval None.
317 */
CLK_AHBPeriphralCmd(uint32_t Periphral,uint32_t NewState)318 void CLK_AHBPeriphralCmd(uint32_t Periphral, uint32_t NewState)
319 {
320 /* Check parameters */
321 assert_parameters(IS_CLK_AHBPERIPHRAL(Periphral));
322 assert_parameters(IS_FUNCTIONAL_STATE(NewState));
323
324 if (NewState == ENABLE)
325 {
326 MISC2->HCLKEN |= Periphral;
327 }
328 else
329 {
330 MISC2->HCLKEN &= ~Periphral;
331 }
332 }
333
334 /**
335 * @brief APB Periphral clock control.
336 * @param Periphral: can use the ��|�� operator
337 CLK_APBPERIPHRAL_DMA
338 CLK_APBPERIPHRAL_I2C
339 CLK_APBPERIPHRAL_SPI1
340 CLK_APBPERIPHRAL_SPI2
341 CLK_APBPERIPHRAL_UART0
342 CLK_APBPERIPHRAL_UART1
343 CLK_APBPERIPHRAL_UART2
344 CLK_APBPERIPHRAL_UART3
345 CLK_APBPERIPHRAL_UART4
346 CLK_APBPERIPHRAL_UART5
347 CLK_APBPERIPHRAL_ISO78160
348 CLK_APBPERIPHRAL_ISO78161
349 CLK_APBPERIPHRAL_TIMER
350 CLK_APBPERIPHRAL_MISC
351 CLK_APBPERIPHRAL_MISC2
352 CLK_APBPERIPHRAL_PMU
353 CLK_APBPERIPHRAL_RTC
354 CLK_APBPERIPHRAL_ANA
355 CLK_APBPERIPHRAL_U32K0
356 CLK_APBPERIPHRAL_U32K1
357 NewState:
358 ENABLE
359 DISABLE
360 * @retval None.
361 */
CLK_APBPeriphralCmd(uint32_t Periphral,uint32_t NewState)362 void CLK_APBPeriphralCmd(uint32_t Periphral, uint32_t NewState)
363 {
364 /* Check parameters */
365 assert_parameters(IS_CLK_APBPERIPHRAL(Periphral));
366 assert_parameters(IS_FUNCTIONAL_STATE(NewState));
367
368 if (NewState == ENABLE)
369 {
370 MISC2->PCLKEN |= Periphral;
371 }
372 else
373 {
374 MISC2->PCLKEN &= ~Periphral;
375 }
376 }
377
378 /**
379 * @brief Returns the HCLK frequency
380 * @param None
381 * @retval HCLK frequency
382 */
CLK_GetHCLKFreq(void)383 uint32_t CLK_GetHCLKFreq(void)
384 {
385 uint32_t ahb_clksrc;
386 uint32_t ahb_div;
387 uint32_t pllh_frq;
388 uint32_t plll_frq;
389 uint32_t rtcclk_div;
390 uint32_t hclk;
391
392 /* Get current AHB clock source */
393 ahb_clksrc = MISC2->CLKSEL & MISC2_CLKSEL_CLKSEL;
394 /* Get AHB clock divider */
395 ahb_div = (MISC2->CLKDIVH & MISC2_CLKDIVH_CLKDIVH) + 1;
396
397 switch (ahb_clksrc)
398 {
399 /* AHB Clock source : 6.5M RC */
400 case MISC2_CLKSEL_CLKSEL_RCOH:
401 hclk = 6553600 / ahb_div;
402 break;
403
404 /* AHB Clock source : 6.5M XTAL */
405 case MISC2_CLKSEL_CLKSEL_XOH:
406 hclk = 6553600 / ahb_div;
407 break;
408
409 /* AHB Clock source : PLLH */
410 case MISC2_CLKSEL_CLKSEL_PLLH:
411 /* Get PLLH Frequency */
412 pllh_frq = ANA->REG9 & ANA_REG9_PLLHSEL;
413 switch (pllh_frq)
414 {
415 case ANA_REG9_PLLHSEL_X2:
416 hclk = 13107200 / ahb_div;
417 break;
418
419 case ANA_REG9_PLLHSEL_X2_5:
420 hclk = 16384000 / ahb_div;
421 break;
422
423 case ANA_REG9_PLLHSEL_X3:
424 hclk = 19660800 / ahb_div;
425 break;
426
427 case ANA_REG9_PLLHSEL_X3_5:
428 hclk = 22937600 / ahb_div;
429 break;
430
431 case ANA_REG9_PLLHSEL_X4:
432 hclk = 26214400 / ahb_div;
433 break;
434
435 case ANA_REG9_PLLHSEL_X4_5:
436 hclk = 29491200 / ahb_div;
437 break;
438
439 case ANA_REG9_PLLHSEL_X5:
440 hclk = 32768000 / ahb_div;
441 break;
442
443 case ANA_REG9_PLLHSEL_X5_5:
444 hclk = 36044800 / ahb_div;
445 break;
446
447 case ANA_REG9_PLLHSEL_X6:
448 hclk = 39321600 / ahb_div;
449 break;
450
451 case ANA_REG9_PLLHSEL_X6_5:
452 hclk = 42598400 / ahb_div;
453 break;
454
455 case ANA_REG9_PLLHSEL_X7:
456 hclk = 45875200 / ahb_div;
457 break;
458
459 case ANA_REG9_PLLHSEL_X7_5:
460 hclk = 49152000 / ahb_div;
461 break;
462
463 default:
464 hclk = 0;
465 break;
466 }
467 break;
468
469 /* AHB Clock source : RTCCLK */
470 case MISC2_CLKSEL_CLKSEL_RTCCLK:
471 /* Get current RTC clock divider */
472 rtcclk_div = RTC->PSCA & RTC_PSCA_PSCA;
473 if (rtcclk_div == RTC_PSCA_PSCA_0)
474 {
475 hclk = 32768 / ahb_div;
476 }
477 else if (rtcclk_div == RTC_PSCA_PSCA_1)
478 {
479 hclk = 8192 / ahb_div;
480 }
481 else
482 {
483 hclk = 0;
484 }
485 break;
486
487 /* AHB Clock source : PLLL */
488 case MISC2_CLKSEL_CLKSEL_PLLL:
489 /* Get PLLL Frequency */
490 plll_frq = ANA->REG9 & ANA_REG9_PLLLSEL;
491 switch (plll_frq)
492 {
493 case ANA_REG9_PLLLSEL_26M:
494 hclk = 26214400 / ahb_div;
495 break;
496
497 case ANA_REG9_PLLLSEL_13M:
498 hclk = 13107200 / ahb_div;
499 break;
500
501 case ANA_REG9_PLLLSEL_6_5M:
502 hclk = 6553600 / ahb_div;
503 break;
504
505 case ANA_REG9_PLLLSEL_3_2M:
506 hclk = 3276800 / ahb_div;
507 break;
508
509 case ANA_REG9_PLLLSEL_1_6M:
510 hclk = 1638400 / ahb_div;
511 break;
512
513 case ANA_REG9_PLLLSEL_800K:
514 hclk = 819200 / ahb_div;
515 break;
516
517 case ANA_REG9_PLLLSEL_400K:
518 hclk = 409600 / ahb_div;
519 break;
520
521 case ANA_REG9_PLLLSEL_200K:
522 hclk = 204800 / ahb_div;
523 break;
524
525 default:
526 hclk = 0;
527 break;
528 }
529 break;
530
531 default:
532 hclk = 0;
533 break;
534 }
535
536 return (hclk);
537 }
538
539 /**
540 * @brief Returns the PCLK frequency
541 * @param None
542 * @retval PCLK frequency
543 */
CLK_GetPCLKFreq(void)544 uint32_t CLK_GetPCLKFreq(void)
545 {
546 return ((CLK_GetHCLKFreq()) / ((MISC2->CLKDIVP & MISC2_CLKDIVP_CLKDIVP) + 1));
547 }
548
549 /**
550 * @brief Get the CLK_ClkInitStruct according to the internal
551 * Clock configuration registers.
552 *
553 * @param CLK_ClkInitStruct pointer to an CLK_ClkInitStruct structure that
554 * contains the current clock configuration.
555 *
556 * @retval None
557 */
CLK_GetClockConfig(CLK_InitTypeDef * CLK_ClkInitStruct)558 void CLK_GetClockConfig(CLK_InitTypeDef *CLK_ClkInitStruct)
559 {
560 /* Set all possible values for the Clock type parameter --------------------*/
561 CLK_ClkInitStruct->ClockType = CLK_TYPE_ALL;
562
563 /* Get AHB clock source ----------------------------------------------------*/
564 CLK_ClkInitStruct->AHBSource = (uint32_t)(MISC2->CLKSEL & MISC2_CLKSEL_CLKSEL);
565 /* Get PLLL clock configration ---------------------------------------------*/
566 CLK_ClkInitStruct->PLLL.Source = (uint32_t)(PMU->CONTROL & PMU_CONTROL_PLLL_SEL);
567 CLK_ClkInitStruct->PLLL.Frequency = (uint32_t)(ANA->REG9 & ANA_REG9_PLLLSEL);
568 CLK_ClkInitStruct->PLLL.State = (uint32_t)(ANA->REG3 & ANA_REG3_PLLLPDN);
569 /* Get PLLH clock configuration --------------------------------------------*/
570 CLK_ClkInitStruct->PLLH.Source = (uint32_t)(PMU->CONTROL & PMU_CONTROL_PLLH_SEL);
571 CLK_ClkInitStruct->PLLH.Frequency = (uint32_t)(ANA->REG9 & ANA_REG9_PLLHSEL);
572 CLK_ClkInitStruct->PLLH.State = (uint32_t)(ANA->REG3 & ANA_REG3_PLLHPDN);
573 /* Get XTALH configuration -------------------------------------------------*/
574 CLK_ClkInitStruct->XTALH.State = (uint32_t)(ANA->REG3 & ANA_REG3_XOHPDN);
575 /* Get HCLK(Divider) configuration -----------------------------------------*/
576 CLK_ClkInitStruct->HCLK.Divider = (uint32_t)((MISC2->CLKDIVH & MISC2_CLKDIVH_CLKDIVH) + 1);
577 /* Get PCLK((Divider) configuration ----------------------------------------*/
578 CLK_ClkInitStruct->PCLK.Divider = (uint32_t)((MISC2->CLKDIVP & MISC2_CLKDIVP_CLKDIVP) + 1);
579 }
580
581 /**
582 * @brief Get current external 6.5M crystal status.
583 *
584 * @param None
585 *
586 * @retval 6.5M crystal status
587 * 0: 6.5536M crystal is absent.
588 * 1: 6.5536M crystal is present.
589 */
CLK_GetXTALHStatus(void)590 uint8_t CLK_GetXTALHStatus(void)
591 {
592 if (PMU->STS & PMU_STS_EXIST_6M)
593 return (1);
594 else
595 return (0);
596 }
597
598 /**
599 * @brief Get current external 32K crystal status.
600 *
601 * @param None
602 *
603 * @retval 32K crystal status
604 * 0: 32K crystal is absent
605 * 1: 32K crystal is present.
606 */
CLK_GetXTALLStatus(void)607 uint8_t CLK_GetXTALLStatus(void)
608 {
609 if (PMU->STS & PMU_STS_EXIST_32K)
610 return (1);
611 else
612 return (0);
613 }
614
615 /**
616 * @brief Get PLL lock status.
617 * @param PLLStatus:
618 * CLK_STATUS_LOCKL
619 * CLK_STATUS_LOCKH
620 * @retval PLL lock status
621 * 0 PLL is not locked.
622 * 1 PLL is locked.
623 */
CLK_GetPLLLockStatus(uint32_t PLLStatus)624 uint8_t CLK_GetPLLLockStatus(uint32_t PLLStatus)
625 {
626 /* Check parameters */
627 assert_parameters(IS_CLK_PLLLOCK(PLLStatus));
628
629 if (ANA->COMPOUT & PLLStatus)
630 return 1;
631 else
632 return 0;
633 }
634
635 /*********************************** END OF FILE ******************************/
636