1 /**
2 ******************************************************************************
3 * @file lib_dma.c
4 * @author Application Team
5 * @version V4.4.0
6 * @date 22018-09-27
7 * @brief DMA library.
8 ******************************************************************************
9 * @attention
10 *
11 ******************************************************************************
12 */
13 #include "lib_dma.h"
14
15 //registers default reset values
16 #define DMA_CxCTL_RSTValue (0UL)
17 #define DMA_CxSRC_RSTValue (0UL)
18 #define DMA_CxDST_RSTValue (0UL)
19 #define DMA_AESCTL_RSTValue (0UL)
20 #define DMA_AESKEY_RSTValue (0UL)
21
22 /**
23 * @brief Initializes the DMA Cx peripheral registers to their default reset values.
24 * @param Channel: DMA_CHANNEL_0~DMA_CHANNEL_3
25 * @retval None
26 */
DMA_DeInit(uint32_t Channel)27 void DMA_DeInit(uint32_t Channel)
28 {
29 __IO uint32_t *addr;
30
31 /* Check parameters */
32 assert_parameters(IS_DMA_CHANNEL(Channel));
33
34 /* channel x disable, clear stop */
35 addr = &DMA->C0CTL + Channel*4;
36 *addr &= ~(DMA_CxCTL_EN | DMA_CTL_STOP);
37
38 /* interrupt disable */
39 DMA->IE &= ~((1<<(Channel))\
40 |(1<<(Channel+4))\
41 |(1<<(Channel+8)));
42
43 /* interrupt state clear */
44 DMA->STS = (1<<(Channel+4))\
45 |(1<<(Channel+8))\
46 |(1<<(Channel+12));
47
48 /* DMA_CxCTL */
49 addr = &DMA->C0CTL + Channel*4;
50 *addr = DMA_CxCTL_RSTValue;
51
52 /* DMA_CxSRC */
53 addr = &DMA->C0SRC + Channel*4;
54 *addr = DMA_CxSRC_RSTValue;
55
56 /* DMA_CxDST */
57 addr = &DMA->C0DST + Channel*4;
58 *addr = DMA_CxDST_RSTValue;
59 }
60
61 /**
62 * @brief DMA channel x initialization.
63 * @param InitStruct: DMA configuration.
64 DestAddr : destination address
65 SrcAddr : source address
66 FrameLen : Frame length (Ranges 0~255, actual length FrameLen+1)
67 PackLen : Package length (Ranges 0~255, actual length PackLen+1)
68 ContMode:
69 DMA_CONTMODE_ENABLE
70 DMA_CONTMODE_DISABLE
71 TransMode:
72 DMA_TRANSMODE_SINGLE
73 DMA_TRANSMODE_PACK
74 ReqSrc:
75 DMA_REQSRC_SOFT
76 DMA_REQSRC_UART0TX
77 DMA_REQSRC_UART0RX
78 DMA_REQSRC_UART1TX
79 DMA_REQSRC_UART1RX
80 DMA_REQSRC_UART2TX
81 DMA_REQSRC_UART2RX
82 DMA_REQSRC_UART3TX
83 DMA_REQSRC_UART3RX
84 DMA_REQSRC_UART4TX
85 DMA_REQSRC_UART4RX
86 DMA_REQSRC_UART5TX
87 DMA_REQSRC_UART5RX
88 DMA_REQSRC_ISO78160TX
89 DMA_REQSRC_ISO78160RX
90 DMA_REQSRC_ISO78161TX
91 DMA_REQSRC_ISO78161RX
92 DMA_REQSRC_TIMER0
93 DMA_REQSRC_TIMER1
94 DMA_REQSRC_TIMER2
95 DMA_REQSRC_TIMER3
96 DMA_REQSRC_SPI1TX
97 DMA_REQSRC_SPI1RX
98 DMA_REQSRC_U32K0
99 DMA_REQSRC_U32K1
100 DMA_REQSRC_CMP1
101 DMA_REQSRC_CMP2
102 DMA_REQSRC_SPI2TX
103 DMA_REQSRC_SPI2RX
104 DestAddrMode:
105 DMA_DESTADDRMODE_FIX
106 DMA_DESTADDRMODE_PEND
107 DMA_DESTADDRMODE_FEND
108 SrcAddrMode:
109 DMA_SRCADDRMODE_FIX
110 DMA_SRCADDRMODE_PEND
111 DMA_SRCADDRMODE_FEND
112 TransSize:
113 DMA_TRANSSIZE_BYTE
114 DMA_TRANSSIZE_HWORD
115 DMA_TRANSSIZE_WORD
116 Channel:
117 DMA_CHANNEL_0
118 DMA_CHANNEL_1
119 DMA_CHANNEL_2
120 DMA_CHANNEL_3
121 * @retval None
122 */
DMA_Init(DMA_InitType * InitStruct,uint32_t Channel)123 void DMA_Init(DMA_InitType *InitStruct, uint32_t Channel)
124 {
125 uint32_t tmp;
126 __IO uint32_t *addr;
127
128 /* Check parameters */
129 assert_parameters(IS_DMA_CHANNEL(Channel));
130 assert_parameters(IS_DMA_CONTMOD(InitStruct->ContMode));
131 assert_parameters(IS_DMA_TRANSMOD(InitStruct->TransMode));
132 assert_parameters(IS_DMA_REQSRC(InitStruct->ReqSrc));
133 assert_parameters(IS_DMA_DESTADDRMOD(InitStruct->DestAddrMode));
134 assert_parameters(IS_DMA_SRCADDRMOD(InitStruct->SrcAddrMode));
135 assert_parameters(IS_DMA_TRANSSIZE(InitStruct->TransSize));
136
137 if (InitStruct->TransSize == DMA_TRANSSIZE_HWORD)
138 {
139 assert_parameters(IS_DMA_ALIGNEDADDR_HWORD(InitStruct->SrcAddr));
140 assert_parameters(IS_DMA_ALIGNEDADDR_HWORD(InitStruct->DestAddr));
141 }
142 if (InitStruct->TransSize == DMA_TRANSSIZE_WORD)
143 {
144 assert_parameters(IS_DMA_ALIGNEDADDR_WORD(InitStruct->SrcAddr));
145 assert_parameters(IS_DMA_ALIGNEDADDR_WORD(InitStruct->DestAddr));
146 }
147
148 addr = &DMA->C0DST + Channel*4;
149 *addr = InitStruct->DestAddr;
150
151 addr = &DMA->C0SRC + Channel*4;
152 *addr = InitStruct->SrcAddr;
153
154 addr = &DMA->C0CTL + Channel*4;
155
156 tmp = *addr;
157 tmp &= ~(DMA_CTL_FLEN\
158 |DMA_CTL_PLEN\
159 |DMA_CTL_CONT\
160 |DMA_CTL_TMODE\
161 |DMA_CTL_DMASEL\
162 |DMA_CxCTL_DMODE\
163 |DMA_CxCTL_SMODE\
164 |DMA_CxCTL_SIZE);
165 tmp |= ((InitStruct->FrameLen<<DMA_CTL_FLEN_Pos)\
166 |(InitStruct->PackLen<<DMA_CTL_PLEN_Pos)\
167 |(InitStruct->ContMode)\
168 |(InitStruct->TransMode)\
169 |(InitStruct->ReqSrc)\
170 |(InitStruct->DestAddrMode)\
171 |(InitStruct->SrcAddrMode)\
172 |(InitStruct->TransSize));
173 *addr = tmp;
174 }
175
176 /**
177 * @brief Initializes the DMA AES channel3 registers to their default reset values.
178 * @param None
179 * @retval None
180 */
DMA_AESDeInit(void)181 void DMA_AESDeInit(void)
182 {
183 DMA->AESCTL = DMA_AESCTL_RSTValue;
184 DMA->AESKEY0 = DMA_AESKEY_RSTValue;
185 DMA->AESKEY1 = DMA_AESKEY_RSTValue;
186 DMA->AESKEY2 = DMA_AESKEY_RSTValue;
187 DMA->AESKEY3 = DMA_AESKEY_RSTValue;
188 DMA->AESKEY4 = DMA_AESKEY_RSTValue;
189 DMA->AESKEY5 = DMA_AESKEY_RSTValue;
190 DMA->AESKEY6 = DMA_AESKEY_RSTValue;
191 DMA->AESKEY7 = DMA_AESKEY_RSTValue;
192 }
193
194 /**
195 * @brief AES initialization.
196 * @param InitStruct: AES configuration.
197 Mode:
198 DMA_AESMODE_128
199 DMA_AESMODE_192
200 DMA_AESMODE_256
201 Direction:
202 DMA_AESDIRECTION_ENCODE
203 DMA_AESDIRECTION_DECODE
204 KeyStr: the pointer to DMA_AESKEYx register
205 * @retval None
206 */
DMA_AESInit(DMA_AESInitType * InitStruct)207 void DMA_AESInit(DMA_AESInitType *InitStruct)
208 {
209 uint32_t tmp;
210
211 /* Check parameters */
212 assert_parameters(IS_DMA_AESMOD(InitStruct->Mode));
213 assert_parameters(IS_DMA_AESDIR(InitStruct->Direction));
214
215 tmp = DMA->AESCTL;
216 tmp &= ~(DMA_AESCTL_MODE\
217 |DMA_AESCTL_ENC);
218 tmp |= (InitStruct->Mode\
219 |InitStruct->Direction);
220 DMA->AESCTL = tmp;
221 DMA->AESKEY0 = InitStruct->KeyStr[0];
222 DMA->AESKEY1 = InitStruct->KeyStr[1];
223 DMA->AESKEY2 = InitStruct->KeyStr[2];
224 DMA->AESKEY3 = InitStruct->KeyStr[3];
225
226 if ((InitStruct->Mode == DMA_AESMODE_192) ||\
227 (InitStruct->Mode == DMA_AESMODE_256))
228 {
229 DMA->AESKEY4 = InitStruct->KeyStr[4];
230 DMA->AESKEY5 = InitStruct->KeyStr[5];
231 }
232 if (InitStruct->Mode == DMA_AESMODE_256)
233 {
234 DMA->AESKEY6 = InitStruct->KeyStr[6];
235 DMA->AESKEY7 = InitStruct->KeyStr[7];
236 }
237 }
238
239 /**
240 * @brief Interrupt configure.
241 * @param INTMask: can use the ��|�� operator
242 DMA_INT_C3DA
243 DMA_INT_C2DA
244 DMA_INT_C1DA
245 DMA_INT_C0DA
246 DMA_INT_C3FE
247 DMA_INT_C2FE
248 DMA_INT_C1FE
249 DMA_INT_C0FE
250 DMA_INT_C3PE
251 DMA_INT_C2PE
252 DMA_INT_C1PE
253 DMA_INT_C0PE
254 NewState:
255 ENABLE
256 DISABLE
257 * @retval None
258 */
DMA_INTConfig(uint32_t INTMask,uint32_t NewState)259 void DMA_INTConfig(uint32_t INTMask, uint32_t NewState)
260 {
261 /* Check parameters */
262 assert_parameters(IS_DMA_INT(INTMask));
263 assert_parameters(IS_FUNCTIONAL_STATE(NewState));
264
265 if (NewState == ENABLE)
266 DMA->IE |= INTMask;
267 else
268 DMA->IE &= ~INTMask;
269 }
270
271 /**
272 * @brief Get interrupt status.
273 * @param INTMask:
274 DMA_INTSTS_C3DA
275 DMA_INTSTS_C2DA
276 DMA_INTSTS_C1DA
277 DMA_INTSTS_C0DA
278 DMA_INTSTS_C3FE
279 DMA_INTSTS_C2FE
280 DMA_INTSTS_C1FE
281 DMA_INTSTS_C0FE
282 DMA_INTSTS_C3PE
283 DMA_INTSTS_C2PE
284 DMA_INTSTS_C1PE
285 DMA_INTSTS_C0PE
286 DMA_INTSTS_C3BUSY
287 DMA_INTSTS_C2BUSY
288 DMA_INTSTS_C1BUSY
289 DMA_INTSTS_C0BUSY
290 * @retval interrupt status.
291 */
DMA_GetINTStatus(uint32_t INTMask)292 uint8_t DMA_GetINTStatus(uint32_t INTMask)
293 {
294 /* Check parameters */
295 assert_parameters(IS_DMA_INTFLAGR(INTMask));
296
297 if (DMA->STS&INTMask)
298 return 1;
299 else
300 return 0;
301 }
302
303 /**
304 * @brief Clear interrupt status.
305 * @param INTMask: can use the ��|�� operator
306 DMA_INTSTS_C3DA
307 DMA_INTSTS_C2DA
308 DMA_INTSTS_C1DA
309 DMA_INTSTS_C0DA
310 DMA_INTSTS_C3FE
311 DMA_INTSTS_C2FE
312 DMA_INTSTS_C1FE
313 DMA_INTSTS_C0FE
314 DMA_INTSTS_C3PE
315 DMA_INTSTS_C2PE
316 DMA_INTSTS_C1PE
317 DMA_INTSTS_C0PE
318 * @retval None
319 */
DMA_ClearINTStatus(uint32_t INTMask)320 void DMA_ClearINTStatus(uint32_t INTMask)
321 {
322 /* Check parameters */
323 assert_parameters(IS_DMA_INTFLAGC(INTMask));
324
325 DMA->STS = INTMask;
326 }
327
328 /**
329 * @brief DMA channel enable.
330 * @param Channel:
331 DMA_CHANNEL_0
332 DMA_CHANNEL_1
333 DMA_CHANNEL_2
334 DMA_CHANNEL_3
335 NewState:
336 ENABLE
337 DISABLE
338 * @retval None
339 */
DMA_Cmd(uint32_t Channel,uint32_t NewState)340 void DMA_Cmd(uint32_t Channel, uint32_t NewState)
341 {
342 __IO uint32_t *addr;
343
344 /* Check parameters */
345 assert_parameters(IS_DMA_CHANNEL(Channel));
346 assert_parameters(IS_FUNCTIONAL_STATE(NewState));
347
348 addr = &DMA->C0CTL + Channel*4;
349
350 if (NewState == ENABLE)
351 *addr |= DMA_CxCTL_EN;
352 else
353 *addr &= ~DMA_CxCTL_EN;
354 }
355
356 /**
357 * @brief Enable AES encrypt/decrypt function of DMA channel3.
358 * @param NewState:
359 ENABLE
360 DISABLE
361 * @retval None
362 */
DMA_AESCmd(uint32_t NewState)363 void DMA_AESCmd(uint32_t NewState)
364 {
365 /* Check parameters */
366 assert_parameters(IS_FUNCTIONAL_STATE(NewState));
367
368 if (NewState == ENABLE)
369 DMA->C3CTL |= DMA_CTL_AESEN;
370 else
371 DMA->C3CTL &= ~DMA_CTL_AESEN;
372 }
373
374 /**
375 * @brief DMA stop transmit.
376 * @param Channel:
377 DMA_CHANNEL_0
378 DMA_CHANNEL_1
379 DMA_CHANNEL_2
380 DMA_CHANNEL_3
381 NewState:
382 ENABLE
383 DISABLE
384 * @retval None
385 */
DMA_StopTransmit(uint32_t Channel,uint32_t NewState)386 void DMA_StopTransmit(uint32_t Channel, uint32_t NewState)
387 {
388 __IO uint32_t *addr;
389
390 /* Check parameters */
391 assert_parameters(IS_DMA_CHANNEL(Channel));
392 assert_parameters(IS_FUNCTIONAL_STATE(NewState));
393
394 addr = &DMA->C0CTL + Channel*4;
395
396 if (NewState == ENABLE)
397 *addr |= DMA_CTL_STOP;
398 else
399 *addr &= ~DMA_CTL_STOP;
400 }
401
402 /**
403 * @brief Get current frame transferred length.
404 * @param Channel:
405 DMA_CHANNEL_0
406 DMA_CHANNEL_1
407 DMA_CHANNEL_2
408 DMA_CHANNEL_3
409 * @retval Current frame transferred length.
410 */
DMA_GetFrameLenTransferred(uint32_t Channel)411 uint8_t DMA_GetFrameLenTransferred(uint32_t Channel)
412 {
413 __IO uint32_t *addr;
414
415 /* Check parameters */
416 assert_parameters(IS_DMA_CHANNEL(Channel));
417
418 addr = &DMA->C0LEN + Channel*4;
419 return ((*addr&0xFF00)>>8);
420 }
421
422 /**
423 * @brief Get current package transferred length.
424 * @param Channel:
425 DMA_CHANNEL_0
426 DMA_CHANNEL_1
427 DMA_CHANNEL_2
428 DMA_CHANNEL_3
429 * @retval Current package transferred length.
430 */
DMA_GetPackLenTransferred(uint32_t Channel)431 uint8_t DMA_GetPackLenTransferred(uint32_t Channel)
432 {
433 __IO uint32_t *addr;
434
435 /* Check parameters */
436 assert_parameters(IS_DMA_CHANNEL(Channel));
437
438 addr = &DMA->C0LEN + Channel*4;
439 return (*addr&0xFF);
440 }
441
442 /*********************************** END OF FILE ******************************/
443