1 /** 2 ****************************************************************************** 3 * @file lib_adc.h 4 * @author Application Team 5 * @version V1.1.0 6 * @date 2019-10-28 7 * @brief ADC library. 8 ****************************************************************************** 9 * @attention 10 * 11 ****************************************************************************** 12 */ 13 #ifndef __LIB_ADC_H 14 #define __LIB_ADC_H 15 16 #ifdef __cplusplus 17 extern "C" { 18 #endif 19 20 #include "target.h" 21 22 typedef struct 23 { 24 uint32_t Mode; 25 uint32_t ClockSource; 26 uint32_t ClockFrq; 27 uint32_t SkipSample; 28 uint32_t AverageSample; 29 uint32_t TriggerSource; 30 uint32_t Channel; 31 uint32_t ResDivEnable; 32 uint32_t AverageEnable; 33 } ADC_InitType; 34 35 typedef struct 36 { 37 uint32_t THDChannel; 38 uint8_t UpperTHD; 39 uint8_t LowerTHD; 40 uint32_t TriggerSel; 41 uint32_t THDSource; 42 } ADCTHD_InitType; 43 44 /* Exported constants --------------------------------------------------------*/ 45 //Mode 46 #define ADC_MODE_DC (0UL) 47 #define ADC_MODE_AC (1UL) 48 #define ADC_MODE_TEMP (2UL) 49 #define IS_ADC_MODE(__MODE__) (((__MODE__) == ADC_MODE_DC) ||\ 50 ((__MODE__) == ADC_MODE_AC) ||\ 51 ((__MODE__) == ADC_MODE_TEMP)) 52 //ClockSource 53 #define ADC_CLKSRC_RCH (0) 54 #define ADC_CLKSRC_PLLL ANA_ADCCTRL0_CLKSRCSEL 55 #define IS_ADC_CLKSRC(__CLKSRC__) (((__CLKSRC__) == ADC_CLKSRC_RCH) ||\ 56 ((__CLKSRC__) == ADC_CLKSRC_PLLL)) 57 //ClockFrq 58 #define ADC_CLKFRQ_HIGH (0UL) 59 #define ADC_CLKFRQ_LOW (1UL) 60 #define IS_ADC_CLKFRQ(__CLKFRQ__) (((__CLKFRQ__) == ADC_CLKFRQ_HIGH) ||\ 61 ((__CLKFRQ__) == ADC_CLKFRQ_LOW)) 62 //SkipSample 63 #define ADC_SKIP_0 (0x0UL << RTC_ADCMACTL_SKIP_SAMPLE_Pos) 64 #define ADC_SKIP_4 (0x4UL << RTC_ADCMACTL_SKIP_SAMPLE_Pos) 65 #define ADC_SKIP_8 (0x7UL << RTC_ADCMACTL_SKIP_SAMPLE_Pos) 66 #define ADC_SKIP_12 (0x12UL << RTC_ADCMACTL_SKIP_SAMPLE_Pos) 67 #define IS_ADC_SKIP(__SKIP__) (((__SKIP__) == ADC_SKIP_0) ||\ 68 ((__SKIP__) == ADC_SKIP_4) ||\ 69 ((__SKIP__) == ADC_SKIP_8) ||\ 70 ((__SKIP__) == ADC_SKIP_12)) 71 //AverageSample 72 #define ADC_AVERAGE_2 (0x0UL << RTC_ADCMACTL_AVERAGE_SAMPLE_Pos) 73 #define ADC_AVERAGE_4 (0x1UL << RTC_ADCMACTL_AVERAGE_SAMPLE_Pos) 74 #define ADC_AVERAGE_8 (0x2UL << RTC_ADCMACTL_AVERAGE_SAMPLE_Pos) 75 #define ADC_AVERAGE_16 (0x3UL << RTC_ADCMACTL_AVERAGE_SAMPLE_Pos) 76 #define ADC_AVERAGE_32 (0x4UL << RTC_ADCMACTL_AVERAGE_SAMPLE_Pos) 77 #define ADC_AVERAGE_64 (0x5UL << RTC_ADCMACTL_AVERAGE_SAMPLE_Pos) 78 #define IS_ADC_AVERAG(__AVERAG__) (((__AVERAG__) == ADC_AVERAGE_2) ||\ 79 ((__AVERAG__) == ADC_AVERAGE_4) ||\ 80 ((__AVERAG__) == ADC_AVERAGE_8) ||\ 81 ((__AVERAG__) == ADC_AVERAGE_16) ||\ 82 ((__AVERAG__) == ADC_AVERAGE_32) ||\ 83 ((__AVERAG__) == ADC_AVERAGE_64)) 84 //TriggerSource 85 #define ADC_TRIGSOURCE_OFF (0x0UL << ANA_ADCCTRL0_AEN_Pos) 86 #define ADC_TRIGSOURCE_ITVSITV (0x1UL << ANA_ADCCTRL0_AEN_Pos) 87 #define ADC_TRIGSOURCE_WKUSEC (0x2UL << ANA_ADCCTRL0_AEN_Pos) 88 #define ADC_TRIGSOURCE_ALARM (0x3UL << ANA_ADCCTRL0_AEN_Pos) 89 #define ADC_TRIGSOURCE_TMR0 (0x4UL << ANA_ADCCTRL0_AEN_Pos) 90 #define ADC_TRIGSOURCE_TMR1 (0x5UL << ANA_ADCCTRL0_AEN_Pos) 91 #define ADC_TRIGSOURCE_TMR2 (0x6UL << ANA_ADCCTRL0_AEN_Pos) 92 #define ADC_TRIGSOURCE_TMR3 (0x7UL << ANA_ADCCTRL0_AEN_Pos) 93 #define IS_ADC_TRIGSOURCE(__TRIGSOURCE__) (((__TRIGSOURCE__) == ADC_TRIGSOURCE_OFF) ||\ 94 ((__TRIGSOURCE__) == ADC_TRIGSOURCE_ITVSITV) ||\ 95 ((__TRIGSOURCE__) == ADC_TRIGSOURCE_WKUSEC) ||\ 96 ((__TRIGSOURCE__) == ADC_TRIGSOURCE_ALARM) ||\ 97 ((__TRIGSOURCE__) == ADC_TRIGSOURCE_TMR0) ||\ 98 ((__TRIGSOURCE__) == ADC_TRIGSOURCE_TMR1) ||\ 99 ((__TRIGSOURCE__) == ADC_TRIGSOURCE_TMR2) ||\ 100 ((__TRIGSOURCE__) == ADC_TRIGSOURCE_TMR3)) 101 //Channel 102 #define ADC_CHANNEL_NONE (0 << 0UL) 103 #define ADC_CHANNEL_GND0 (1 << 0UL) 104 #define ADC_CHANNEL_BAT1 (1 << 1UL) 105 #define ADC_CHANNEL_BATRTC (1 << 2UL) 106 #define ADC_CHANNEL_CH3 (1 << 3UL) 107 #define ADC_CHANNEL_CH4 (1 << 4UL) 108 #define ADC_CHANNEL_CH5 (1 << 5UL) 109 #define ADC_CHANNEL_CH6 (1 << 6UL) 110 #define ADC_CHANNEL_CH7 (1 << 7UL) 111 #define ADC_CHANNEL_CH8 (1 << 8UL) 112 #define ADC_CHANNEL_CH9 (1 << 9UL) 113 #define ADC_CHANNEL_TEMP (1 << 10UL) 114 #define ADC_CHANNEL_CH11 (1 << 11UL) 115 #define ADC_CHANNEL_DVCC (1 << 12UL) 116 #define ADC_CHANNEL_GND13 (1 << 13UL) 117 #define ADC_CHANNEL_GND14 (1 << 14UL) 118 #define ADC_CHANNEL_GND15 (1 << 15UL) 119 #define ADC_CHANNEL_DC_Msk (0xFBFFUL) 120 #define ADC_CHANNEL_DC_ALL ADC_CHANNEL_DC_Msk 121 #define ADC_CHANNEL_AC_Msk (0x0BF8UL) 122 #define ADC_CHANNEL_AC_ALL ADC_CHANNEL_AC_Msk 123 #define IS_ADC_CHANNEL_GETDATA(__CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_GND0) ||\ 124 ((__CHANNEL__) == ADC_CHANNEL_BAT1) ||\ 125 ((__CHANNEL__) == ADC_CHANNEL_BATRTC) ||\ 126 ((__CHANNEL__) == ADC_CHANNEL_CH3) ||\ 127 ((__CHANNEL__) == ADC_CHANNEL_CH4) ||\ 128 ((__CHANNEL__) == ADC_CHANNEL_CH5) ||\ 129 ((__CHANNEL__) == ADC_CHANNEL_CH6) ||\ 130 ((__CHANNEL__) == ADC_CHANNEL_CH7) ||\ 131 ((__CHANNEL__) == ADC_CHANNEL_CH8) ||\ 132 ((__CHANNEL__) == ADC_CHANNEL_CH9) ||\ 133 ((__CHANNEL__) == ADC_CHANNEL_TEMP) ||\ 134 ((__CHANNEL__) == ADC_CHANNEL_CH11) ||\ 135 ((__CHANNEL__) == ADC_CHANNEL_DVCC) ||\ 136 ((__CHANNEL__) == ADC_CHANNEL_GND13) ||\ 137 ((__CHANNEL__) == ADC_CHANNEL_GND14) ||\ 138 ((__CHANNEL__) == ADC_CHANNEL_GND15)) 139 #define IS_ADC_CHANNEL_AC(__CHANNEL__) ((((__CHANNEL__) & ADC_CHANNEL_AC_Msk) != 0UL) &&\ 140 (((__CHANNEL__) & ~ADC_CHANNEL_AC_Msk) == 0UL)) 141 #define IS_ADC_CHANNEL_DC(__CHANNEL__) ((((__CHANNEL__) & ADC_CHANNEL_DC_Msk) != 0UL) &&\ 142 (((__CHANNEL__) & ~ADC_CHANNEL_DC_Msk) == 0UL)) 143 #define IS_ADC_CHANNEL_TEMP(__CHANNEL__) ((__CHANNEL__) == ADC_CHANNEL_TEMP) 144 #define IS_ADC_CHANNEL_EN_DC(__CHANNEL__) (((((__CHANNEL__) & ADC_CHANNEL_DC_Msk) != 0UL) && (((__CHANNEL__) & ~ADC_CHANNEL_DC_Msk) == 0UL)) ||\ 145 ((__CHANNEL__) == ADC_CHANNEL_NONE)) 146 #define IS_ADC_CHANNEL_EN_AC(__CHANNEL__) (((((__CHANNEL__) & ADC_CHANNEL_AC_Msk) != 0UL) && (((__CHANNEL__) & ~ADC_CHANNEL_AC_Msk) == 0UL)) ||\ 147 ((__CHANNEL__) == ADC_CHANNEL_NONE)) 148 149 #define ADC_CHANNEL_Pos (0UL) 150 #define ADC_CHANNEL_SHIFT (ANA_ADCCTRL2_SCAN_CHx_Pos - ADC_CHANNEL_Pos) 151 #define ADC_AVERAGECH_SHIFT (RTC_ADCMACTL_AVERAGE_CHx_Pos - ADC_CHANNEL_Pos) 152 #define ADC_RESDIVCH_SHIFT (ANA_ADCCTRL1_RESDIV_CHx_Pos - ADC_CHANNEL_Pos) 153 154 //THDChannel 155 #define ADC_THDCHANNEL0 (0UL) 156 #define ADC_THDCHANNEL1 (1UL) 157 #define ADC_THDCHANNEL2 (2UL) 158 #define ADC_THDCHANNEL3 (3UL) 159 #define IS_ADC_THDCHANNEL(THDCHANNEL) (((THDCHANNEL) == ADC_THDCHANNEL0) ||\ 160 ((THDCHANNEL) == ADC_THDCHANNEL1) ||\ 161 ((THDCHANNEL) == ADC_THDCHANNEL2) ||\ 162 ((THDCHANNEL) == ADC_THDCHANNEL3)) 163 164 //TriggerSel 165 #define ADC_THDSEL_HIGH (0UL) 166 #define ADC_THDSEL_RISING (1UL) 167 #define ADC_THDSEL_FALLING (2UL) 168 #define ADC_THDSEL_BOTH (3UL) 169 #define IS_ADC_THDSEL(__THDSEL__) (((__THDSEL__) == ADC_THDSEL_HIGH) ||\ 170 ((__THDSEL__) == ADC_THDSEL_RISING) ||\ 171 ((__THDSEL__) == ADC_THDSEL_FALLING) ||\ 172 ((__THDSEL__) == ADC_THDSEL_BOTH)) 173 174 //INTMask 175 #define ADC_INT_UPPER_TH3 ANA_INTEN_INTEN21 176 #define ADC_INT_LOWER_TH3 ANA_INTEN_INTEN20 177 #define ADC_INT_UPPER_TH2 ANA_INTEN_INTEN19 178 #define ADC_INT_LOWER_TH2 ANA_INTEN_INTEN18 179 #define ADC_INT_UPPER_TH1 ANA_INTEN_INTEN17 180 #define ADC_INT_LOWER_TH1 ANA_INTEN_INTEN16 181 #define ADC_INT_UPPER_TH0 ANA_INTEN_INTEN15 182 #define ADC_INT_LOWER_TH0 ANA_INTEN_INTEN14 183 #define ADC_INT_AUTODONE ANA_INTEN_INTEN1 184 #define ADC_INT_MANUALDONE ANA_INTEN_INTEN0 185 #define ADC_INT_Msk (0x3FC003UL) 186 #define IS_ADC_INT(__INT__) ((((__INT__) & ADC_INT_Msk) != 0UL) &&\ 187 (((__INT__) & ~ADC_INT_Msk) == 0UL)) 188 189 //INTSTS 190 #define ADC_INTSTS_UPPER_TH3 ANA_INTSTS_INTSTS21 191 #define ADC_INTSTS_LOWER_TH3 ANA_INTSTS_INTSTS20 192 #define ADC_INTSTS_UPPER_TH2 ANA_INTSTS_INTSTS19 193 #define ADC_INTSTS_LOWER_TH2 ANA_INTSTS_INTSTS18 194 #define ADC_INTSTS_UPPER_TH1 ANA_INTSTS_INTSTS17 195 #define ADC_INTSTS_LOWER_TH1 ANA_INTSTS_INTSTS16 196 #define ADC_INTSTS_UPPER_TH0 ANA_INTSTS_INTSTS15 197 #define ADC_INTSTS_LOWER_TH0 ANA_INTSTS_INTSTS14 198 #define ADC_INTSTS_AUTODONE ANA_INTSTS_INTSTS1 199 #define ADC_INTSTS_MANUALDONE ANA_INTSTS_INTSTS0 200 #define ADC_INTSTS_Msk (0x3FC003UL) 201 #define IS_ADC_INTFLAGC(__INTFLAGC__) ((((__INTFLAGC__) & ADC_INTSTS_Msk) != 0U) &&\ 202 (((__INTFLAGC__) & ~ADC_INTSTS_Msk) == 0U)) 203 204 #define IS_ADC_INTFLAGR(__INTFLAGR__) (((__INTFLAGR__) == ADC_INTSTS_UPPER_TH3) ||\ 205 ((__INTFLAGR__) == ADC_INTSTS_LOWER_TH3) ||\ 206 ((__INTFLAGR__) == ADC_INTSTS_UPPER_TH2) ||\ 207 ((__INTFLAGR__) == ADC_INTSTS_LOWER_TH2) ||\ 208 ((__INTFLAGR__) == ADC_INTSTS_UPPER_TH1) ||\ 209 ((__INTFLAGR__) == ADC_INTSTS_LOWER_TH1) ||\ 210 ((__INTFLAGR__) == ADC_INTSTS_UPPER_TH0) ||\ 211 ((__INTFLAGR__) == ADC_INTSTS_LOWER_TH0) ||\ 212 ((__INTFLAGR__) == ADC_INTSTS_AUTODONE) ||\ 213 ((__INTFLAGR__) == ADC_INTSTS_MANUALDONE)) 214 215 #define ADC_FLAG_CONV_ERR (0x1U << ANA_ADCCTRL2_CONV_ERR_Pos) 216 #define ADC_FLAG_CAL_ERR (0x1U << ANA_ADCCTRL2_CAL_ERR_Pos) 217 #define ADC_FLAG_CAL_DONE (0x1U << ANA_ADCCTRL2_RTC_CAL_DONE_Pos) 218 #define ADC_FLAG_BUSY (0x1U << ANA_ADCCTRL2_BUSY_Pos) 219 #define IS_ADC_ADCFLAG(__ADCFLAG__) (((__ADCFLAG__) == ADC_FLAG_CONV_ERR) ||\ 220 ((__ADCFLAG__) == ADC_FLAG_CAL_ERR) ||\ 221 ((__ADCFLAG__) == ADC_FLAG_CAL_DONE) ||\ 222 ((__ADCFLAG__) == ADC_FLAG_BUSY)) 223 224 #define ADC_FLAG_RCMsk (ADC_FLAG_CONV_ERR|ADC_FLAG_CAL_ERR) 225 #define IS_ADC_ADCFLAGC(__ADCFLAG__) ((((__ADCFLAG__) & ADC_FLAG_RCMsk) != 0U) &&\ 226 (((__ADCFLAG__) & ~ADC_FLAG_RCMsk) == 0U)) 227 228 //THDFlag 229 #define ADC_THDFLAG_UPPER3 (0x1U << ANA_ADCDATATHD_CH_UPPER_THD3_TRGED_Pos) 230 #define ADC_THDFLAG_LOWER3 (0x1U << ANA_ADCDATATHD_CH_LOWER_THD3_TRGED_Pos) 231 #define ADC_THDFLAG_UPPER2 (0x1U << ANA_ADCDATATHD_CH_UPPER_THD2_TRGED_Pos) 232 #define ADC_THDFLAG_LOWER2 (0x1U << ANA_ADCDATATHD_CH_LOWER_THD2_TRGED_Pos) 233 #define ADC_THDFLAG_UPPER1 (0x1U << ANA_ADCDATATHD_CH_UPPER_THD1_TRGED_Pos) 234 #define ADC_THDFLAG_LOWER1 (0x1U << ANA_ADCDATATHD_CH_LOWER_THD1_TRGED_Pos) 235 #define ADC_THDFLAG_UPPER0 (0x1U << ANA_ADCDATATHD_CH_UPPER_THD0_TRGED_Pos) 236 #define ADC_THDFLAG_LOWER0 (0x1U << ANA_ADCDATATHD_CH_LOWER_THD0_TRGED_Pos) 237 #define IS_ADC_THDFLAG(__THDFLAG__) (((__THDFLAG__) == ADC_THDFLAG_UPPER3) ||\ 238 ((__THDFLAG__) == ADC_THDFLAG_LOWER3) ||\ 239 ((__THDFLAG__) == ADC_THDFLAG_UPPER2) ||\ 240 ((__THDFLAG__) == ADC_THDFLAG_LOWER2) ||\ 241 ((__THDFLAG__) == ADC_THDFLAG_UPPER1) ||\ 242 ((__THDFLAG__) == ADC_THDFLAG_LOWER1) ||\ 243 ((__THDFLAG__) == ADC_THDFLAG_UPPER0) ||\ 244 ((__THDFLAG__) == ADC_THDFLAG_LOWER0)) 245 246 #define IS_ADC_BATDIV(__BATDIV__) (((__BATDIV__) == ADC_BAT_CAPDIV) ||\ 247 ((__BATDIV__) == ADC_BAT_RESDIV)) 248 249 /* ADC_GetVoltage */ 250 //Mode 251 #define ADC_3V_ADCCHx_NODIV (0x000UL) // Power supply: 3.3V; Channel: External; Divider modeL: None 252 #define ADC_3V_ADCCHx_RESDIV (0x001UL) // Power supply: 3.3V; Channel: External; Divider modeL: Resistive 253 #define ADC_3V_BAT1_RESDIV (0x002UL) // Power supply: 3.3V; Channel: VDD; Divider modeL: Resistive 254 #define ADC_3V_BATRTC_RESDIV (0x003UL) // Power supply: 3.3V; Channel: BATRTC; Divider modeL: Resistive 255 #define ADC_5V_ADCCHx_NODIV (0x100UL) // Power supply: 5V; Channel: External; Divider modeL: None 256 #define ADC_5V_ADCCHx_RESDIV (0x101UL) // Power supply: 5V; Channel: External; Divider modeL: Resistive 257 #define ADC_5V_BAT1_RESDIV (0x102UL) // Power supply: 5V; Channel: VDD; Divider modeL: Resistive 258 #define ADC_5V_BATRTC_RESDIV (0x103UL) // Power supply: 5V; Channel: BATRTC; Divider modeL: Resistive 259 #define ADC_TEMP (0x1000UL) // Temperature ; Channel: ADC_CHANNEL_TEMP 260 #define IS_ADCVOL_MODE(__MODE__) (((__MODE__) == ADC_3V_ADCCHx_NODIV) ||\ 261 ((__MODE__) == ADC_3V_ADCCHx_RESDIV) ||\ 262 ((__MODE__) == ADC_3V_BAT1_RESDIV) ||\ 263 ((__MODE__) == ADC_3V_BATRTC_RESDIV) ||\ 264 ((__MODE__) == ADC_5V_ADCCHx_NODIV) ||\ 265 ((__MODE__) == ADC_5V_ADCCHx_RESDIV) ||\ 266 ((__MODE__) == ADC_5V_BAT1_RESDIV) ||\ 267 ((__MODE__) == ADC_5V_BATRTC_RESDIV) ||\ 268 ((__MODE__) == ADC_TEMP)) 269 270 /* Exported Functions ------------------------------------------------------- */ 271 /* ADC Exported Functions Group1: 272 (De)Initialization -------------------------*/ 273 void ADC_DeInit(void); 274 void ADC_StructInit(ADC_InitType* ADC_InitStruct); 275 void ADC_Init(ADC_InitType* ADC_InitStruct); 276 /* ADC Exported Functions Group2: 277 ADC Configuration --------------*/ 278 void ADC_THDInit(ADCTHD_InitType* ADC_THDStruct); 279 void ADC_THDStructInit(ADCTHD_InitType* ADC_THDStruct); 280 void ADC_Calibration(void); 281 /* ADC Exported Functions Group3: 282 Get NVR Info, Calculate datas --------------*/ 283 uint32_t ADC_CalculateValue(uint32_t Mode, int16_t adc_data, int16_t *value); 284 /* ADC Exported Functions Group4: 285 Interrupt (flag) ---------------------------*/ 286 int16_t ADC_GetADCConversionValue(uint32_t Channel); 287 void ADC_INTConfig(uint32_t INTMask, uint32_t NewState); 288 uint8_t ADC_GetFlag(uint32_t FlagMask); 289 void ADC_ClearFlag(uint32_t FlagMask); 290 uint8_t ADC_GetINTStatus(uint32_t INTMask); 291 void ADC_ClearINTStatus(uint32_t INTMask); 292 uint8_t ADC_GetTHDFlag(uint32_t THDFlagMask); 293 294 /* ADC Exported Functions Group5: 295 MISC Configuration -------------------------*/ 296 void ADC_Cmd(uint32_t NewState); 297 void ADC_LowerTHDCmd(uint32_t THDChannel,uint32_t NewState); 298 void ADC_UpperTHDCmd(uint32_t THDChannel,uint32_t NewState); 299 void ADC_StartManual(void); 300 void ADC_WaitForManual(void); 301 302 #ifdef __cplusplus 303 } 304 #endif 305 306 #endif /* __LIB_ADC_H */ 307 308 /*********************************** END OF FILE ******************************/ 309