1 /** 2 ****************************************************************************** 3 * @file lib_clk.c 4 * @author Application Team 5 * @version V1.1.0 6 * @date 2019-10-28 7 * @brief Clock library. 8 ****************************************************************************** 9 * @attention 10 * 11 ****************************************************************************** 12 */ 13 #ifndef __LIB_CLK_H 14 #define __LIB_CLK_H 15 16 #ifdef __cplusplus 17 extern "C" { 18 #endif 19 20 #include "target.h" 21 22 /* PLLL Configure */ 23 typedef struct 24 { 25 uint32_t Source; 26 uint32_t State; 27 uint32_t Frequency; 28 } PLLL_ConfTypeDef; 29 30 /* PLLH Configure */ 31 typedef struct 32 { 33 uint32_t Source; 34 uint32_t State; 35 uint32_t Frequency; 36 } PLLH_ConfTypeDef; 37 38 /* RCH Configure */ 39 typedef struct 40 { 41 uint32_t State; 42 } RCH_ConfTypeDef; 43 44 /* XTALH Configure */ 45 typedef struct 46 { 47 uint32_t State; 48 } XTALH_ConfTypeDef; 49 50 /* RTCCLK Configure */ 51 typedef struct 52 { 53 uint32_t Source; 54 uint32_t Divider; 55 } RTCCLK_ConfTypeDef; 56 57 /* HCLK Configure */ 58 typedef struct 59 { 60 uint32_t Divider; /* 1 ~ 256 */ 61 } HCLK_ConfTypeDef; 62 63 /* PCLK Configure */ 64 typedef struct 65 { 66 uint32_t Divider; /* 1 ~ 256 */ 67 } PCLK_ConfTypeDef; 68 69 /* Clock Configure */ 70 typedef struct 71 { 72 uint32_t ClockType; /* The clock to be configured */ 73 74 uint32_t AHBSource; 75 76 PLLL_ConfTypeDef PLLL; 77 78 PLLH_ConfTypeDef PLLH; 79 80 XTALH_ConfTypeDef XTALH; 81 82 RTCCLK_ConfTypeDef RTCCLK; 83 84 HCLK_ConfTypeDef HCLK; 85 86 PCLK_ConfTypeDef PCLK; 87 88 } CLK_InitTypeDef; 89 90 /************** Bits definition for ANA_REG9 register ******************/ 91 #define ANA_REG9_PLLLSEL_26M (0x0U << ANA_REG9_PLLLSEL_Pos) 92 #define ANA_REG9_PLLLSEL_13M (0x1U << ANA_REG9_PLLLSEL_Pos) 93 #define ANA_REG9_PLLLSEL_6_5M (0x2U << ANA_REG9_PLLLSEL_Pos) 94 #define ANA_REG9_PLLLSEL_3_2M (0x3U << ANA_REG9_PLLLSEL_Pos) 95 #define ANA_REG9_PLLLSEL_1_6M (0x4U << ANA_REG9_PLLLSEL_Pos) 96 #define ANA_REG9_PLLLSEL_800K (0x5U << ANA_REG9_PLLLSEL_Pos) 97 #define ANA_REG9_PLLLSEL_400K (0x6U << ANA_REG9_PLLLSEL_Pos) 98 #define ANA_REG9_PLLLSEL_200K (0x7U << ANA_REG9_PLLLSEL_Pos) 99 #define ANA_REG9_PLLHSEL_X2 (0xCU << ANA_REG9_PLLHSEL_Pos) 100 #define ANA_REG9_PLLHSEL_X2_5 (0xDU << ANA_REG9_PLLHSEL_Pos) 101 #define ANA_REG9_PLLHSEL_X3 (0xEU << ANA_REG9_PLLHSEL_Pos) 102 #define ANA_REG9_PLLHSEL_X3_5 (0xFU << ANA_REG9_PLLHSEL_Pos) 103 #define ANA_REG9_PLLHSEL_X4 (0x0U << ANA_REG9_PLLHSEL_Pos) 104 #define ANA_REG9_PLLHSEL_X4_5 (0x1U << ANA_REG9_PLLHSEL_Pos) 105 #define ANA_REG9_PLLHSEL_X5 (0x2U << ANA_REG9_PLLHSEL_Pos) 106 #define ANA_REG9_PLLHSEL_X5_5 (0x3U << ANA_REG9_PLLHSEL_Pos) 107 #define ANA_REG9_PLLHSEL_X6 (0x4U << ANA_REG9_PLLHSEL_Pos) 108 #define ANA_REG9_PLLHSEL_X6_5 (0x5U << ANA_REG9_PLLHSEL_Pos) 109 #define ANA_REG9_PLLHSEL_X7 (0x6U << ANA_REG9_PLLHSEL_Pos) 110 #define ANA_REG9_PLLHSEL_X7_5 (0x7U << ANA_REG9_PLLHSEL_Pos) 111 112 /************** Bits definition for MISC2_CLKSEL register ******************/ 113 #define MISC2_CLKSEL_CLKSEL_RCOH (0x0U << MISC2_CLKSEL_CLKSEL_Pos) /*!< 0x00000000 */ 114 #define MISC2_CLKSEL_CLKSEL_XOH (0x1U << MISC2_CLKSEL_CLKSEL_Pos) /*!< 0x00000001 */ 115 #define MISC2_CLKSEL_CLKSEL_PLLH (0x2U << MISC2_CLKSEL_CLKSEL_Pos) /*!< 0x00000002 */ 116 #define MISC2_CLKSEL_CLKSEL_RTCCLK (0x3U << MISC2_CLKSEL_CLKSEL_Pos) /*!< 0x00000003 */ 117 #define MISC2_CLKSEL_CLKSEL_PLLL (0x4U << MISC2_CLKSEL_CLKSEL_Pos) /*!< 0x00000004 */ 118 119 /***** ClockType *****/ 120 #define CLK_TYPE_MSk (0xFFUL) 121 #define CLK_TYPE_ALL CLK_TYPE_MSk 122 #define CLK_TYPE_AHBSRC (0x01UL) /* AHB Clock source to configure */ 123 #define CLK_TYPE_PLLL (0x02UL) /* PLLL to configure */ 124 #define CLK_TYPE_PLLH (0x04UL) /* PLLH to configure */ 125 #define CLK_TYPE_XTALH (0x08UL) /* XTALH to configure */ 126 #define CLK_TYPE_RTCCLK (0x20UL) /* RTCCLK to configure */ 127 #define CLK_TYPE_HCLK (0x40UL) /* AHB Clock to configure */ 128 #define CLK_TYPE_PCLK (0x80UL) /* APB Clock to configure */ 129 130 /***** AHBSource *****/ 131 #define CLK_AHBSEL_6_5MRC (0x0U << MISC2_CLKSEL_CLKSEL_Pos) 132 #define CLK_AHBSEL_6_5MXTAL (0x1U << MISC2_CLKSEL_CLKSEL_Pos) 133 #define CLK_AHBSEL_HSPLL (0x2U << MISC2_CLKSEL_CLKSEL_Pos) 134 #define CLK_AHBSEL_RTCCLK (0x3U << MISC2_CLKSEL_CLKSEL_Pos) 135 #define CLK_AHBSEL_LSPLL (0x4U << MISC2_CLKSEL_CLKSEL_Pos) 136 137 /***** PLLL_ConfTypeDef PLLL *****/ 138 /* PLLL.Source */ 139 #define CLK_PLLLSRC_RCL PMU_CONTROL_PLLL_SEL 140 #define CLK_PLLLSRC_XTALL (0) 141 /* PLLL.State */ 142 #define CLK_PLLL_ON ANA_REG3_PLLLPDN 143 #define CLK_PLLL_OFF (0) 144 /* PLLL.Frequency */ 145 #define CLK_PLLL_26_2144MHz ANA_REG9_PLLLSEL_26M 146 #define CLK_PLLL_13_1072MHz ANA_REG9_PLLLSEL_13M 147 #define CLK_PLLL_6_5536MHz ANA_REG9_PLLLSEL_6_5M 148 #define CLK_PLLL_3_2768MHz ANA_REG9_PLLLSEL_3_2M 149 #define CLK_PLLL_1_6384MHz ANA_REG9_PLLLSEL_1_6M 150 #define CLK_PLLL_0_8192MHz ANA_REG9_PLLLSEL_800K 151 #define CLK_PLLL_0_4096MHz ANA_REG9_PLLLSEL_400K 152 #define CLK_PLLL_0_2048MHz ANA_REG9_PLLLSEL_200K 153 154 /***** PLLH_ConfTypeDef PLLH *****/ 155 /* PLLH.Source */ 156 #define CLK_PLLHSRC_RCH (0) 157 #define CLK_PLLHSRC_XTALH PMU_CONTROL_PLLH_SEL 158 /* PLLH.State */ 159 #define CLK_PLLH_ON ANA_REG3_PLLHPDN 160 #define CLK_PLLH_OFF (0) 161 /* PLLH.Frequency */ 162 #define CLK_PLLH_13_1072MHz ANA_REG9_PLLHSEL_X2 163 #define CLK_PLLH_16_384MHz ANA_REG9_PLLHSEL_X2_5 164 #define CLK_PLLH_19_6608MHz ANA_REG9_PLLHSEL_X3 165 #define CLK_PLLH_22_9376MHz ANA_REG9_PLLHSEL_X3_5 166 #define CLK_PLLH_26_2144MHz ANA_REG9_PLLHSEL_X4 167 #define CLK_PLLH_29_4912MHz ANA_REG9_PLLHSEL_X4_5 168 #define CLK_PLLH_32_768MHz ANA_REG9_PLLHSEL_X5 169 #define CLK_PLLH_36_0448MHz ANA_REG9_PLLHSEL_X5_5 170 #define CLK_PLLH_39_3216MHz ANA_REG9_PLLHSEL_X6 171 #define CLK_PLLH_42_5984MHz ANA_REG9_PLLHSEL_X6_5 172 #define CLK_PLLH_45_8752MHz ANA_REG9_PLLHSEL_X7 173 #define CLK_PLLH_49_152MHz ANA_REG9_PLLHSEL_X7_5 174 175 /* XTALH_ConfTypeDef XTALH */ 176 /* XTALH.State */ 177 #define CLK_XTALH_ON ANA_REG3_XOHPDN 178 #define CLK_XTALH_OFF (0) 179 180 /* RTCCLK Configure */ 181 /* RTCCLK.Source */ 182 #define CLK_RTCCLKSRC_XTALL (0) 183 #define CLK_RTCCLKSRC_RCL (PMU_CONTROL_RTCCLK_SEL) 184 /* RTCCLK.Divider */ 185 #define CLK_RTCCLKDIV_1 (RTC_PSCA_PSCA_0) 186 #define CLK_RTCCLKDIV_4 (RTC_PSCA_PSCA_1) 187 188 //AHB Periphral 189 #define CLK_AHBPERIPHRAL_DMA MISC2_HCLKEN_DMA 190 #define CLK_AHBPERIPHRAL_GPIO MISC2_HCLKEN_GPIO 191 #define CLK_AHBPERIPHRAL_LCD MISC2_HCLKEN_LCD 192 #define CLK_AHBPERIPHRAL_CRYPT MISC2_HCLKEN_CRYPT 193 #define CLK_AHBPERIPHRAL_ALL (MISC2_HCLKEN_DMA \ 194 |MISC2_HCLKEN_GPIO \ 195 |MISC2_HCLKEN_LCD \ 196 |MISC2_HCLKEN_CRYPT) 197 198 //APB Periphral 199 #define CLK_APBPERIPHRAL_DMA MISC2_PCLKEN_DMA 200 #define CLK_APBPERIPHRAL_I2C MISC2_PCLKEN_I2C 201 #define CLK_APBPERIPHRAL_SPI1 MISC2_PCLKEN_SPI1 202 #define CLK_APBPERIPHRAL_UART0 MISC2_PCLKEN_UART0 203 #define CLK_APBPERIPHRAL_UART1 MISC2_PCLKEN_UART1 204 #define CLK_APBPERIPHRAL_UART2 MISC2_PCLKEN_UART2 205 #define CLK_APBPERIPHRAL_UART3 MISC2_PCLKEN_UART3 206 #define CLK_APBPERIPHRAL_UART4 MISC2_PCLKEN_UART4 207 #define CLK_APBPERIPHRAL_UART5 MISC2_PCLKEN_UART5 208 #define CLK_APBPERIPHRAL_ISO78160 MISC2_PCLKEN_ISO78160 209 #define CLK_APBPERIPHRAL_ISO78161 MISC2_PCLKEN_ISO78161 210 #define CLK_APBPERIPHRAL_TIMER MISC2_PCLKEN_TIMER 211 #define CLK_APBPERIPHRAL_MISC MISC2_PCLKEN_MISC 212 #define CLK_APBPERIPHRAL_MISC2 MISC2_PCLKEN_MISC2 213 #define CLK_APBPERIPHRAL_PMU MISC2_PCLKEN_PMU 214 #define CLK_APBPERIPHRAL_RTC MISC2_PCLKEN_RTC 215 #define CLK_APBPERIPHRAL_ANA MISC2_PCLKEN_ANA 216 #define CLK_APBPERIPHRAL_U32K0 MISC2_PCLKEN_U32K0 217 #define CLK_APBPERIPHRAL_U32K1 MISC2_PCLKEN_U32K1 218 #define CLK_APBPERIPHRAL_SPI2 MISC2_PCLKEN_SPI2 219 #define CLK_APBPERIPHRAL_ALL (MISC2_PCLKEN_DMA \ 220 |MISC2_PCLKEN_I2C \ 221 |MISC2_PCLKEN_SPI1 \ 222 |MISC2_PCLKEN_UART0 \ 223 |MISC2_PCLKEN_UART1 \ 224 |MISC2_PCLKEN_UART2 \ 225 |MISC2_PCLKEN_UART3 \ 226 |MISC2_PCLKEN_UART4 \ 227 |MISC2_PCLKEN_UART5 \ 228 |MISC2_PCLKEN_ISO78160 \ 229 |MISC2_PCLKEN_ISO78161 \ 230 |MISC2_PCLKEN_TIMER \ 231 |MISC2_PCLKEN_MISC1 \ 232 |MISC2_PCLKEN_MISC2 \ 233 |MISC2_PCLKEN_PMU \ 234 |MISC2_PCLKEN_RTC \ 235 |MISC2_PCLKEN_ANA \ 236 |MISC2_PCLKEN_U32K0 \ 237 |MISC2_PCLKEN_U32K1 \ 238 |MISC2_PCLKEN_SPI2 \ 239 |MISC2_PCLKEN_SPI3) 240 241 /***** PLLStatus (CLK_GetPLLLockStatus) *****/ 242 #define CLK_STATUS_LOCKL ANA_CMPOUT_LOCKL 243 #define CLK_STATUS_LOCKH ANA_CMPOUT_LOCKH 244 245 246 /* Private macros ------------------------------------------------------------*/ 247 #define IS_CLK_TYPE(__TYPE__) ((((__TYPE__) & CLK_TYPE_MSk) != 0UL) &&\ 248 (((__TYPE__) & ~CLK_TYPE_MSk) == 0UL)) 249 250 #define IS_CLK_AHBSRC(__AHBSRC__) (((__AHBSRC__) == CLK_AHBSEL_6_5MRC) ||\ 251 ((__AHBSRC__) == CLK_AHBSEL_6_5MXTAL) ||\ 252 ((__AHBSRC__) == CLK_AHBSEL_HSPLL) ||\ 253 ((__AHBSRC__) == CLK_AHBSEL_RTCCLK) ||\ 254 ((__AHBSRC__) == CLK_AHBSEL_LSPLL)) 255 256 #define IS_CLK_PLLLSRC(__PLLLSRC__) (((__PLLLSRC__) == CLK_PLLLSRC_RCL) ||\ 257 ((__PLLLSRC__) == CLK_PLLLSRC_XTALL)) 258 259 #define IS_CLK_PLLLSTA(__PLLLSTA__) (((__PLLLSTA__) == CLK_PLLL_ON) ||\ 260 ((__PLLLSTA__) == CLK_PLLL_OFF)) 261 262 #define IS_CLK_PLLLFRQ(__PLLLFRQ__) (((__PLLLFRQ__) == CLK_PLLL_26_2144MHz) ||\ 263 ((__PLLLFRQ__) == CLK_PLLL_13_1072MHz) ||\ 264 ((__PLLLFRQ__) == CLK_PLLL_6_5536MHz) ||\ 265 ((__PLLLFRQ__) == CLK_PLLL_3_2768MHz) ||\ 266 ((__PLLLFRQ__) == CLK_PLLL_1_6384MHz) ||\ 267 ((__PLLLFRQ__) == CLK_PLLL_0_8192MHz) ||\ 268 ((__PLLLFRQ__) == CLK_PLLL_0_4096MHz) ||\ 269 ((__PLLLFRQ__) == CLK_PLLL_0_2048MHz)) 270 271 #define IS_CLK_PLLHSRC(__PLLHSRC__) (((__PLLHSRC__) == CLK_PLLHSRC_RCH) ||\ 272 ((__PLLHSRC__) == CLK_PLLHSRC_XTALH)) 273 274 #define IS_CLK_PLLHSTA(__PLLHSTA__) (((__PLLHSTA__) == CLK_PLLH_ON) ||\ 275 ((__PLLHSTA__) == CLK_PLLH_OFF)) 276 277 #define IS_CLK_PLLHFRQ(__PLLHSRC__) (((__PLLHSRC__) == CLK_PLLH_13_1072MHz) ||\ 278 ((__PLLHSRC__) == CLK_PLLH_16_384MHz) ||\ 279 ((__PLLHSRC__) == CLK_PLLH_19_6608MHz) ||\ 280 ((__PLLHSRC__) == CLK_PLLH_22_9376MHz) ||\ 281 ((__PLLHSRC__) == CLK_PLLH_26_2144MHz) ||\ 282 ((__PLLHSRC__) == CLK_PLLH_29_4912MHz) ||\ 283 ((__PLLHSRC__) == CLK_PLLH_32_768MHz) ||\ 284 ((__PLLHSRC__) == CLK_PLLH_36_0448MHz) ||\ 285 ((__PLLHSRC__) == CLK_PLLH_39_3216MHz) ||\ 286 ((__PLLHSRC__) == CLK_PLLH_42_5984MHz) ||\ 287 ((__PLLHSRC__) == CLK_PLLH_45_8752MHz) ||\ 288 ((__PLLHSRC__) == CLK_PLLH_49_152MHz)) 289 290 #define IS_CLK_XTALHSTA(__XTALHSTA__) (((__XTALHSTA__) == CLK_XTALH_ON) ||\ 291 ((__XTALHSTA__) == CLK_XTALH_OFF)) 292 293 #define IS_CLK_RTCSRC(__RTCSRC__) (((__RTCSRC__) == CLK_RTCCLKSRC_XTALL) ||\ 294 ((__RTCSRC__) == CLK_RTCCLKSRC_RCL)) 295 296 #define IS_CLK_RTCDIV(__RTCDIV__) (((__RTCDIV__) == CLK_RTCCLKDIV_1) ||\ 297 ((__RTCDIV__) == CLK_RTCCLKDIV_4)) 298 299 #define IS_CLK_HCLKDIV(__HCLKDIV__) (((__HCLKDIV__) > 0UL) &&\ 300 ((__HCLKDIV__) < 257UL)) 301 302 #define IS_CLK_PCLKDIV(__PCLKDIV__) (((__PCLKDIV__) > 0UL) &&\ 303 ((__PCLKDIV__) < 257UL)) 304 305 #define IS_CLK_AHBPERIPHRAL(__AHBPERIPHRAL__) ((((__AHBPERIPHRAL__) & CLK_AHBPERIPHRAL_ALL) != 0UL) &&\ 306 (((__AHBPERIPHRAL__) & ~CLK_AHBPERIPHRAL_ALL) == 0UL)) 307 308 #define IS_CLK_APBPERIPHRAL(__APBPERIPHRAL__) ((((__APBPERIPHRAL__) & CLK_APBPERIPHRAL_ALL) != 0UL) &&\ 309 (((__APBPERIPHRAL__) & ~CLK_APBPERIPHRAL_ALL) == 0UL)) 310 311 #define IS_CLK_PLLLOCK(__PLLLOCK__) (((__PLLLOCK__) == ANA_CMPOUT_LOCKL) ||\ 312 ((__PLLLOCK__) == ANA_CMPOUT_LOCKH)) 313 /* Exported Functions ------------------------------------------------------- */ 314 /* CLK Exported Functions Group1: 315 Initialization and functions ---------------*/ 316 void CLK_ClockConfig(CLK_InitTypeDef *CLK_ClkInitStruct); 317 318 /* CLK Exported Functions Group2: 319 Peripheral Control -------------------------*/ 320 void CLK_AHBPeriphralCmd(uint32_t Periphral, uint32_t NewState); 321 void CLK_APBPeriphralCmd(uint32_t Periphral, uint32_t NewState); 322 /* CLK Exported Functions Group3: 323 Get clock/configuration information --------*/ 324 uint32_t CLK_GetHCLKFreq(void); 325 uint32_t CLK_GetPCLKFreq(void); 326 uint32_t CLK_GetPLLLFreq(void); 327 void CLK_GetClockConfig(CLK_InitTypeDef *CLK_ClkInitStruct); 328 uint8_t CLK_GetXTALHStatus(void); 329 uint8_t CLK_GetXTALLStatus(void); 330 uint8_t CLK_GetPLLLockStatus(uint32_t PLLStatus); 331 332 #ifdef __cplusplus 333 } 334 #endif 335 336 #endif /* __LIB_CLK_H */ 337 338 /*********************************** END OF FILE ******************************/ 339