1 /** 2 ****************************************************************************** 3 * @file lib_dma.h 4 * @author Application Team 5 * @version V1.1.0 6 * @date 2019-10-28 7 * @brief DMA library. 8 ****************************************************************************** 9 * @attention 10 * 11 ****************************************************************************** 12 */ 13 #ifndef __LIB_DMA_H 14 #define __LIB_DMA_H 15 16 #ifdef __cplusplus 17 extern "C" { 18 #endif 19 20 #include "target.h" 21 22 //Channel 23 #define DMA_CHANNEL_0 (0) 24 #define DMA_CHANNEL_1 (1) 25 #define DMA_CHANNEL_2 (2) 26 #define DMA_CHANNEL_3 (3) 27 28 typedef struct 29 { 30 uint32_t DestAddr; /* destination address */ 31 uint32_t SrcAddr; /* source address */ 32 uint8_t FrameLen; /* Frame length */ 33 uint8_t PackLen; /* Package length */ 34 uint32_t ContMode; /* Continuous mode */ 35 uint32_t TransMode; /* Transfer mode */ 36 uint32_t ReqSrc; /* DMA request source */ 37 uint32_t DestAddrMode; /* Destination address mode */ 38 uint32_t SrcAddrMode; /* Source address mode */ 39 uint32_t TransSize; /* Transfer size mode */ 40 } DMA_InitType; 41 42 /************** Bits definition for DMA_CxCTL register ******************/ 43 44 45 46 /************** Bits definition for DMA_AESCTL register ******************/ 47 /****************************** DMA Instances *********************************/ 48 #define IS_DMA_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DMA) 49 50 //ContMode 51 #define DMA_CONTMODE_ENABLE DMA_CCTL_CONT 52 #define DMA_CONTMODE_DISABLE 0 53 #define IS_DMA_CONTMOD(__CONTMOD__) (((__CONTMOD__) == DMA_CONTMODE_ENABLE) ||\ 54 ((__CONTMOD__) == DMA_CONTMODE_DISABLE)) 55 56 //TransMode 57 #define DMA_TRANSMODE_SINGLE 0 58 #define DMA_TRANSMODE_PACK DMA_CCTL_TMODE 59 #define IS_DMA_TRANSMOD(__TRANSMOD__) (((__TRANSMOD__) == DMA_TRANSMODE_SINGLE) ||\ 60 ((__TRANSMOD__) == DMA_TRANSMODE_PACK)) 61 62 //ReqSrc 63 #define DMA_REQSRC_SOFT (0x0U << DMA_CCTL_DMASEL_Pos) /*!< 0x00000000 */ 64 #define DMA_REQSRC_ADC (0x1U << DMA_CCTL_DMASEL_Pos) /*!< 0x00000080 */ 65 #define DMA_REQSRC_UART0TX (0x2U << DMA_CCTL_DMASEL_Pos) /*!< 0x00000100 */ 66 #define DMA_REQSRC_UART0RX (0x3U << DMA_CCTL_DMASEL_Pos) /*!< 0x00000180 */ 67 #define DMA_REQSRC_UART1TX (0x4U << DMA_CCTL_DMASEL_Pos) /*!< 0x00000200 */ 68 #define DMA_REQSRC_UART1RX (0x5U << DMA_CCTL_DMASEL_Pos) /*!< 0x00000280 */ 69 #define DMA_REQSRC_UART2TX (0x6U << DMA_CCTL_DMASEL_Pos) /*!< 0x00000300 */ 70 #define DMA_REQSRC_UART2RX (0x7U << DMA_CCTL_DMASEL_Pos) /*!< 0x00000380 */ 71 #define DMA_REQSRC_UART3TX (0x8U << DMA_CCTL_DMASEL_Pos) /*!< 0x00000400 */ 72 #define DMA_REQSRC_UART3RX (0x9U << DMA_CCTL_DMASEL_Pos) /*!< 0x00000480 */ 73 #define DMA_REQSRC_UART4TX (0xAU << DMA_CCTL_DMASEL_Pos) /*!< 0x00000500 */ 74 #define DMA_REQSRC_UART4RX (0xBU << DMA_CCTL_DMASEL_Pos) /*!< 0x00000580 */ 75 #define DMA_REQSRC_UART5TX (0xCU << DMA_CCTL_DMASEL_Pos) /*!< 0x00000600 */ 76 #define DMA_REQSRC_UART5RX (0xDU << DMA_CCTL_DMASEL_Pos) /*!< 0x00000680 */ 77 #define DMA_REQSRC_ISO78160TX (0xEU << DMA_CCTL_DMASEL_Pos) /*!< 0x00000700 */ 78 #define DMA_REQSRC_ISO78160RX (0xFU << DMA_CCTL_DMASEL_Pos) /*!< 0x00000780 */ 79 #define DMA_REQSRC_ISO78161TX (0x10U << DMA_CCTL_DMASEL_Pos) /*!< 0x00000800 */ 80 #define DMA_REQSRC_ISO78161RX (0x11U << DMA_CCTL_DMASEL_Pos) /*!< 0x00000880 */ 81 #define DMA_REQSRC_TIMER0 (0x12U << DMA_CCTL_DMASEL_Pos) /*!< 0x00000900 */ 82 #define DMA_REQSRC_TIMER1 (0x13U << DMA_CCTL_DMASEL_Pos) /*!< 0x00000980 */ 83 #define DMA_REQSRC_TIMER2 (0x14U << DMA_CCTL_DMASEL_Pos) /*!< 0x00000A00 */ 84 #define DMA_REQSRC_TIMER3 (0x15U << DMA_CCTL_DMASEL_Pos) /*!< 0x00000A80 */ 85 #define DMA_REQSRC_SPI1TX (0x16U << DMA_CCTL_DMASEL_Pos) /*!< 0x00000B00 */ 86 #define DMA_REQSRC_SPI1RX (0x17U << DMA_CCTL_DMASEL_Pos) /*!< 0x00000B80 */ 87 #define DMA_REQSRC_U32K0 (0x18U << DMA_CCTL_DMASEL_Pos) /*!< 0x00000C00 */ 88 #define DMA_REQSRC_U32K1 (0x19U << DMA_CCTL_DMASEL_Pos) /*!< 0x00000C80 */ 89 #define DMA_REQSRC_CMP1 (0x1AU << DMA_CCTL_DMASEL_Pos) /*!< 0x00000D00 */ 90 #define DMA_REQSRC_CMP2 (0x1BU << DMA_CCTL_DMASEL_Pos) /*!< 0x00000D80 */ 91 #define DMA_REQSRC_SPI3TX (0x1CU << DMA_CCTL_DMASEL_Pos) /*!< 0x00000E00 */ 92 #define DMA_REQSRC_SPI3RX (0x1DU << DMA_CCTL_DMASEL_Pos) /*!< 0x00000E80 */ 93 #define DMA_REQSRC_SPI2TX (0x1EU << DMA_CCTL_DMASEL_Pos) /*!< 0x00000F00 */ 94 #define DMA_REQSRC_SPI2RX (0x1FU << DMA_CCTL_DMASEL_Pos) /*!< 0x00000F80 */ 95 96 #define IS_DMA_REQSRC(__REQSRC__) (((__REQSRC__) == DMA_REQSRC_SOFT) ||\ 97 ((__REQSRC__) == DMA_REQSRC_ADC) ||\ 98 ((__REQSRC__) == DMA_REQSRC_UART0TX) ||\ 99 ((__REQSRC__) == DMA_REQSRC_UART0RX) ||\ 100 ((__REQSRC__) == DMA_REQSRC_UART1TX) ||\ 101 ((__REQSRC__) == DMA_REQSRC_UART1RX) ||\ 102 ((__REQSRC__) == DMA_REQSRC_UART2TX) ||\ 103 ((__REQSRC__) == DMA_REQSRC_UART2RX) ||\ 104 ((__REQSRC__) == DMA_REQSRC_UART3TX) ||\ 105 ((__REQSRC__) == DMA_REQSRC_UART3RX) ||\ 106 ((__REQSRC__) == DMA_REQSRC_UART4TX) ||\ 107 ((__REQSRC__) == DMA_REQSRC_UART4RX) ||\ 108 ((__REQSRC__) == DMA_REQSRC_UART5TX) ||\ 109 ((__REQSRC__) == DMA_REQSRC_UART5RX) ||\ 110 ((__REQSRC__) == DMA_REQSRC_ISO78160TX) ||\ 111 ((__REQSRC__) == DMA_REQSRC_ISO78160RX) ||\ 112 ((__REQSRC__) == DMA_REQSRC_ISO78161TX) ||\ 113 ((__REQSRC__) == DMA_REQSRC_ISO78161RX) ||\ 114 ((__REQSRC__) == DMA_REQSRC_TIMER0) ||\ 115 ((__REQSRC__) == DMA_REQSRC_TIMER1) ||\ 116 ((__REQSRC__) == DMA_REQSRC_TIMER2) ||\ 117 ((__REQSRC__) == DMA_REQSRC_TIMER3) ||\ 118 ((__REQSRC__) == DMA_REQSRC_SPI1TX) ||\ 119 ((__REQSRC__) == DMA_REQSRC_SPI1RX) ||\ 120 ((__REQSRC__) == DMA_REQSRC_U32K0) ||\ 121 ((__REQSRC__) == DMA_REQSRC_U32K1) ||\ 122 ((__REQSRC__) == DMA_REQSRC_CMP1) ||\ 123 ((__REQSRC__) == DMA_REQSRC_CMP2) ||\ 124 ((__REQSRC__) == DMA_REQSRC_SPI3TX) ||\ 125 ((__REQSRC__) == DMA_REQSRC_SPI3RX) ||\ 126 ((__REQSRC__) == DMA_REQSRC_SPI2TX) ||\ 127 ((__REQSRC__) == DMA_REQSRC_SPI2RX)) 128 129 130 //DestAddrMode 131 #define DMA_DESTADDRMODE_FIX (0x0U << DMA_CCTL_DMODE_Pos) /*!< 0x00000000 */ 132 #define DMA_DESTADDRMODE_PEND (0x1U << DMA_CCTL_DMODE_Pos) /*!< 0x00000020 */ 133 #define DMA_DESTADDRMODE_FEND (0x2U << DMA_CCTL_DMODE_Pos) /*!< 0x00000040 */ 134 #define IS_DMA_DESTADDRMOD(__DAM__) (((__DAM__) == DMA_DESTADDRMODE_FIX) ||\ 135 ((__DAM__) == DMA_DESTADDRMODE_PEND) ||\ 136 ((__DAM__) == DMA_DESTADDRMODE_FEND)) 137 138 //SrcAddrMode 139 #define DMA_SRCADDRMODE_FIX (0x0U << DMA_CCTL_SMODE_Pos) /*!< 0x00000000 */ 140 #define DMA_SRCADDRMODE_PEND (0x1U << DMA_CCTL_SMODE_Pos) /*!< 0x00000008 */ 141 #define DMA_SRCADDRMODE_FEND (0x2U << DMA_CCTL_SMODE_Pos) /*!< 0x00000010 */ 142 #define IS_DMA_SRCADDRMOD(__SAM__) (((__SAM__) == DMA_SRCADDRMODE_FIX) ||\ 143 ((__SAM__) == DMA_SRCADDRMODE_PEND) ||\ 144 ((__SAM__) == DMA_SRCADDRMODE_FEND)) 145 146 //TransSize 147 #define DMA_TRANSSIZE_BYTE (0x0U << DMA_CCTL_SIZE_Pos) 148 #define DMA_TRANSSIZE_HWORD (0x1U << DMA_CCTL_SIZE_Pos) 149 #define DMA_TRANSSIZE_WORD (0x2U << DMA_CCTL_SIZE_Pos) 150 #define IS_DMA_TRANSSIZE(__TSIZE__) (((__TSIZE__) == DMA_TRANSSIZE_BYTE) ||\ 151 ((__TSIZE__) == DMA_TRANSSIZE_HWORD) ||\ 152 ((__TSIZE__) == DMA_TRANSSIZE_WORD)) 153 154 #define IS_DMA_ALIGNEDADDR_WORD(__ADDRW__) (((__ADDRW__) & 0x3U) == 0U) 155 #define IS_DMA_ALIGNEDADDR_HWORD(__ADDRHW__) (((__ADDRHW__) & 0x1U) == 0U) 156 157 typedef struct 158 { 159 uint32_t Mode; /* AES mode */ 160 uint32_t Direction; /* Direction */ 161 uint32_t *KeyStr; /* AES key */ 162 } DMA_AESInitType; 163 164 //AES MODE 165 #define DMA_AESMODE_128 (0x0U << DMA_AESCTL_MODE_Pos) /*!< 0x00000000 */ 166 #define DMA_AESMODE_192 (0x1U << DMA_AESCTL_MODE_Pos) /*!< 0x00000004 */ 167 #define DMA_AESMODE_256 (0x2U << DMA_AESCTL_MODE_Pos) /*!< 0x00000008 */ 168 #define IS_DMA_AESMOD(__AESMOD__) (((__AESMOD__) == DMA_AESMODE_128) ||\ 169 ((__AESMOD__) == DMA_AESMODE_192) ||\ 170 ((__AESMOD__) == DMA_AESMODE_256)) 171 172 //AES Direction 173 #define DMA_AESDIRECTION_ENCODE DMA_AESCTL_ENC 174 #define DMA_AESDIRECTION_DECODE 0 175 #define IS_DMA_AESDIR(__AESDIR__) (((__AESDIR__) == DMA_AESDIRECTION_ENCODE) ||\ 176 ((__AESDIR__) == DMA_AESDIRECTION_DECODE)) 177 178 //INT 179 #define DMA_INT_C3DA DMA_IE_C3DAIE 180 #define DMA_INT_C2DA DMA_IE_C2DAIE 181 #define DMA_INT_C1DA DMA_IE_C1DAIE 182 #define DMA_INT_C0DA DMA_IE_C0DAIE 183 #define DMA_INT_C3FE DMA_IE_C3FEIE 184 #define DMA_INT_C2FE DMA_IE_C2FEIE 185 #define DMA_INT_C1FE DMA_IE_C1FEIE 186 #define DMA_INT_C0FE DMA_IE_C0FEIE 187 #define DMA_INT_C3PE DMA_IE_C3PEIE 188 #define DMA_INT_C2PE DMA_IE_C2PEIE 189 #define DMA_INT_C1PE DMA_IE_C1PEIE 190 #define DMA_INT_C0PE DMA_IE_C0PEIE 191 #define DMA_INT_Msk (0xFFFUL) 192 #define IS_DMA_INT(__INT__) ((((__INT__) & DMA_INT_Msk) != 0U) &&\ 193 (((__INT__) & ~DMA_INT_Msk) == 0U)) 194 195 //INTSTS 196 #define DMA_INTSTS_C3DA DMA_STS_C3DA 197 #define DMA_INTSTS_C2DA DMA_STS_C2DA 198 #define DMA_INTSTS_C1DA DMA_STS_C1DA 199 #define DMA_INTSTS_C0DA DMA_STS_C0DA 200 #define DMA_INTSTS_C3FE DMA_STS_C3FE 201 #define DMA_INTSTS_C2FE DMA_STS_C2FE 202 #define DMA_INTSTS_C1FE DMA_STS_C1FE 203 #define DMA_INTSTS_C0FE DMA_STS_C0FE 204 #define DMA_INTSTS_C3PE DMA_STS_C3PE 205 #define DMA_INTSTS_C2PE DMA_STS_C2PE 206 #define DMA_INTSTS_C1PE DMA_STS_C1PE 207 #define DMA_INTSTS_C0PE DMA_STS_C0PE 208 #define DMA_INTSTS_C3BUSY DMA_STS_C3BUSY 209 #define DMA_INTSTS_C2BUSY DMA_STS_C2BUSY 210 #define DMA_INTSTS_C1BUSY DMA_STS_C1BUSY 211 #define DMA_INTSTS_C0BUSY DMA_STS_C0BUSY 212 #define DMA_INTSTS_Msk (0xFFF0UL) 213 214 #define IS_DMA_INTFLAGR(__INTFLAGR__) (((__INTFLAGR__) == DMA_INTSTS_C3DA) ||\ 215 ((__INTFLAGR__) == DMA_INTSTS_C2DA) ||\ 216 ((__INTFLAGR__) == DMA_INTSTS_C1DA) ||\ 217 ((__INTFLAGR__) == DMA_INTSTS_C0DA) ||\ 218 ((__INTFLAGR__) == DMA_INTSTS_C3FE) ||\ 219 ((__INTFLAGR__) == DMA_INTSTS_C2FE) ||\ 220 ((__INTFLAGR__) == DMA_INTSTS_C1FE) ||\ 221 ((__INTFLAGR__) == DMA_INTSTS_C0FE) ||\ 222 ((__INTFLAGR__) == DMA_INTSTS_C3PE) ||\ 223 ((__INTFLAGR__) == DMA_INTSTS_C2PE) ||\ 224 ((__INTFLAGR__) == DMA_INTSTS_C1PE) ||\ 225 ((__INTFLAGR__) == DMA_INTSTS_C0PE) ||\ 226 ((__INTFLAGR__) == DMA_INTSTS_C3BUSY) ||\ 227 ((__INTFLAGR__) == DMA_INTSTS_C2BUSY) ||\ 228 ((__INTFLAGR__) == DMA_INTSTS_C1BUSY) ||\ 229 ((__INTFLAGR__) == DMA_INTSTS_C0BUSY)) 230 231 #define IS_DMA_INTFLAGC(__INTFLAGC__) ((((__INTFLAGC__) & DMA_INTSTS_Msk) != 0U) &&\ 232 (((__INTFLAGC__) & ~DMA_INTSTS_Msk) == 0U)) 233 234 #define IS_DMA_CHANNEL(__CH__) (((__CH__) == DMA_CHANNEL_0) ||\ 235 ((__CH__) == DMA_CHANNEL_1) ||\ 236 ((__CH__) == DMA_CHANNEL_2) ||\ 237 ((__CH__) == DMA_CHANNEL_3)) 238 239 /* Exported Functions ------------------------------------------------------- */ 240 /* DMA Exported Functions Group1: 241 (De)Initialization ------------------------*/ 242 void DMA_DeInit(uint32_t Channel); 243 void DMA_Init(DMA_InitType *InitStruct, uint32_t Channel); 244 void DMA_StructInit(DMA_InitType *InitStruct); 245 void DMA_ASEDeInit(void); 246 void DMA_AESInit(DMA_AESInitType *InitStruct); 247 /* DMA Exported Functions Group2: 248 Interrupt (flag) --------------------------*/ 249 void DMA_INTConfig(uint32_t INTMask, uint32_t NewState); 250 uint8_t DMA_GetINTStatus(uint32_t INTMask); 251 void DMA_ClearINTStatus(uint32_t INTMask); 252 /* DMA Exported Functions Group3: 253 MISC Configuration ------------------------*/ 254 void DMA_Cmd(uint32_t Channel, uint32_t NewState); 255 void DMA_AESCmd(uint32_t NewState); 256 void DMA_StopTransmit(uint32_t Channel, uint32_t NewState); 257 uint8_t DMA_GetFrameLenTransferred(uint32_t Channel); 258 uint8_t DMA_GetPackLenTransferred(uint32_t Channel); 259 260 261 #ifdef __cplusplus 262 } 263 #endif 264 265 #endif /* __LIB_DMA_H */ 266 267 /*********************************** END OF FILE ******************************/ 268