1 /** 2 ****************************************************************************** 3 * @file lib_pmu.h 4 * @author Application Team 5 * @version V1.1.0 6 * @date 2019-10-28 7 * @brief PMU library. 8 ****************************************************************************** 9 * @attention 10 * 11 ****************************************************************************** 12 */ 13 #ifndef __LIB_PMU_H 14 #define __LIB_PMU_H 15 16 #ifdef __cplusplus 17 extern "C" { 18 #endif 19 20 #include "target.h" 21 22 /** 23 * Deep-sleep low-power configuration 24 */ 25 typedef struct 26 { 27 uint32_t COMP1Power; /* Comparator 1 power control */ 28 uint32_t COMP2Power; /* Comparator 2 power control */ 29 uint32_t TADCPower; /* Tiny ADC power control */ 30 uint32_t BGPPower; /* BGP power control */ 31 uint32_t AVCCPower; /* AVCC power control */ 32 // uint32_t LCDPower; /* LCD controller power control */ 33 uint32_t VDCINDetector; /* VDCIN detector control */ 34 uint32_t VDDDetector; /* VDD detector control */ 35 uint32_t AHBPeriphralDisable; /* AHB Periphral clock disable selection */ 36 uint32_t APBPeriphralDisable; /* APB Periphral clock disable selection */ 37 } PMU_LowPWRTypeDef; 38 39 /************** Bits definition for ANA_REG8 register ******************/ 40 #define ANA_REG8_VDDPVDSEL_0 (0x0UL << ANA_REG8_VDDPVDSEL_Pos) 41 #define ANA_REG8_VDDPVDSEL_1 (0x1UL << ANA_REG8_VDDPVDSEL_Pos) 42 #define ANA_REG8_VDDPVDSEL_2 (0x2UL << ANA_REG8_VDDPVDSEL_Pos) 43 #define ANA_REG8_VDDPVDSEL_3 (0x3UL << ANA_REG8_VDDPVDSEL_Pos) 44 #define ANA_REG8_VDDPVDSEL_4 (0x4UL << ANA_REG8_VDDPVDSEL_Pos) 45 #define ANA_REG8_VDDPVDSEL_5 (0x5UL << ANA_REG8_VDDPVDSEL_Pos) 46 #define ANA_REG8_VDDPVDSEL_6 (0x6UL << ANA_REG8_VDDPVDSEL_Pos) 47 #define ANA_REG8_VDDPVDSEL_7 (0x7UL << ANA_REG8_VDDPVDSEL_Pos) 48 49 /****************************** PMU Instances *********************************/ 50 #define IS_PMU_ALL_INSTANCE(INSTANCE) ((INSTANCE) == PMU) 51 52 /****************************** PMU_RETRAM Instances **************************/ 53 #define IS_PMU_RETRAM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == PMU_RETRAM) 54 55 /* COMP1Power */ 56 #define PMU_COMP1PWR_ON (ANA_REG3_CMP1PDN) 57 #define PMU_COMP1PWR_OFF (0UL) 58 #define IS_PMU_COMP1PWR(__COMP1PWR__) (((__COMP1PWR__) == PMU_COMP1PWR_ON) ||\ 59 ((__COMP1PWR__) == PMU_COMP1PWR_OFF)) 60 /* COMP2Power */ 61 #define PMU_COMP2PWR_ON (ANA_REG3_CMP2PDN) 62 #define PMU_COMP2PWR_OFF (0UL) 63 #define IS_PMU_COMP2PWR(__COMP2PWR__) (((__COMP2PWR__) == PMU_COMP2PWR_ON) ||\ 64 ((__COMP2PWR__) == PMU_COMP2PWR_OFF)) 65 /* TADCPower */ 66 #define PMU_TADCPWR_ON (ANA_REGF_ADTPDN) 67 #define PMU_TADCPWR_OFF (0UL) 68 #define IS_PMU_TADCPWR(__TADCPWR__) (((__TADCPWR__) == PMU_TADCPWR_ON) ||\ 69 ((__TADCPWR__) == PMU_TADCPWR_OFF)) 70 /* BGPPower */ 71 #define PMU_BGPPWR_ON (0UL) 72 #define PMU_BGPPWR_OFF (ANA_REG3_BGPPD) 73 #define IS_PMU_BGPPWR(__BGPPWR__) (((__BGPPWR__) == PMU_BGPPWR_ON) ||\ 74 ((__BGPPWR__) == PMU_BGPPWR_OFF)) 75 /* AVCCPower */ 76 #define PMU_AVCCPWR_ON (0UL) 77 #define PMU_AVCCPWR_OFF (ANA_REG8_AVCCLDOPD) 78 #define IS_PMU_AVCCPWR(__AVCCPWR__) (((__AVCCPWR__) == PMU_AVCCPWR_ON) ||\ 79 ((__AVCCPWR__) == PMU_AVCCPWR_OFF)) 80 81 /* VDCINDetector */ 82 #define PMU_VDCINDET_ENABLE (0UL) 83 #define PMU_VDCINDET_DISABLE (ANA_REGA_VDCINDETPD) 84 #define IS_PMU_VDCINDET(__VDCINDET__) (((__VDCINDET__) == PMU_VDCINDET_ENABLE) ||\ 85 ((__VDCINDET__) == PMU_VDCINDET_DISABLE)) 86 87 /* VDDDetector */ 88 #define PMU_VDDDET_ENABLE (0UL) 89 #define PMU_VDDDET_DISABLE (ANA_REG9_VDDDETPD) 90 #define IS_PMU_VDDDET(__VDDDET__) (((__VDDDET__) == PMU_VDDDET_ENABLE) ||\ 91 ((__VDDDET__) == PMU_VDDDET_DISABLE)) 92 93 #define PMU_APB_ALL (MISC2_PCLKEN_DMA \ 94 |MISC2_PCLKEN_I2C \ 95 |MISC2_PCLKEN_SPI1 \ 96 |MISC2_PCLKEN_UART0 \ 97 |MISC2_PCLKEN_UART1 \ 98 |MISC2_PCLKEN_UART2 \ 99 |MISC2_PCLKEN_UART3 \ 100 |MISC2_PCLKEN_UART4 \ 101 |MISC2_PCLKEN_UART5 \ 102 |MISC2_PCLKEN_ISO78160 \ 103 |MISC2_PCLKEN_ISO78161 \ 104 |MISC2_PCLKEN_TIMER \ 105 |MISC2_PCLKEN_MISC1 \ 106 |MISC2_PCLKEN_MISC2 \ 107 |MISC2_PCLKEN_U32K0 \ 108 |MISC2_PCLKEN_U32K1 \ 109 |MISC2_PCLKEN_SPI2 \ 110 |MISC2_PCLKEN_SPI3) 111 #define PMU_APB_DMA MISC2_PCLKEN_DMA 112 #define PMU_APB_I2C MISC2_PCLKEN_I2C 113 #define PMU_APB_SPI1 MISC2_PCLKEN_SPI1 114 #define PMU_APB_UART0 MISC2_PCLKEN_UART0 115 #define PMU_APB_UART1 MISC2_PCLKEN_UART1 116 #define PMU_APB_UART2 MISC2_PCLKEN_UART2 117 #define PMU_APB_UART3 MISC2_PCLKEN_UART3 118 #define PMU_APB_UART4 MISC2_PCLKEN_UART4 119 #define PMU_APB_UART5 MISC2_PCLKEN_UART5 120 #define PMU_APB_ISO78160 MISC2_PCLKEN_ISO78160 121 #define PMU_APB_ISO78161 MISC2_PCLKEN_ISO78161 122 #define PMU_APB_TIMER MISC2_PCLKEN_TIMER 123 #define PMU_APB_MISC1 MISC2_PCLKEN_MISC1 124 #define PMU_APB_U32K0 MISC2_PCLKEN_U32K0 125 #define PMU_APB_U32K1 MISC2_PCLKEN_U32K1 126 #define PMU_APB_SPI2 MISC2_PCLKEN_SPI2 127 #define PMU_APB_SPI3 MISC2_PCLKEN_SPI3 128 129 #define PMU_AHB_ALL (MISC2_HCLKEN_DMA \ 130 |MISC2_HCLKEN_GPIO \ 131 |MISC2_HCLKEN_CRYPT) 132 // |MISC2_HCLKEN_LCD 133 #define PMU_AHB_DMA MISC2_HCLKEN_DMA 134 #define PMU_AHB_GPIO MISC2_HCLKEN_GPIO 135 //#define PMU_AHB_LCD MISC2_HCLKEN_LCD 136 #define PMU_AHB_CRYPT MISC2_HCLKEN_CRYPT 137 138 //PMU interrupt 139 #define PMU_INT_IOAEN PMU_CONTROL_INT_IOA_EN 140 #define PMU_INT_32K PMU_CONTROL_INT_32K_EN 141 #define PMU_INT_6M PMU_CONTROL_INT_6M_EN 142 #define PMU_INT_Msk (PMU_INT_IOAEN \ 143 |PMU_INT_32K \ 144 |PMU_INT_6M) 145 #define IS_PMU_INT(__INT__) ((((__INT__)&PMU_INT_Msk) != 0UL) &&\ 146 (((__INT__)&(~PMU_INT_Msk)) == 0UL)) 147 148 //INTStatus 149 #define PMU_INTSTS_32K PMU_STS_INT_32K 150 #define PMU_INTSTS_6M PMU_STS_INT_6M 151 #define PMU_INTSTS_Msk (PMU_INTSTS_32K \ 152 |PMU_INTSTS_6M) 153 #define IS_PMU_INTFLAGR(__INTFLAG__) (((__INTFLAG__) == PMU_INTSTS_32K) ||\ 154 ((__INTFLAG__) == PMU_INTSTS_6M)) 155 156 #define IS_PMU_INTFLAGC(__INTFLAG__) ((((__INTFLAG__)&PMU_INTSTS_Msk) != 0UL) &&\ 157 (((__INTFLAG__)&(~PMU_INTSTS_Msk)) == 0UL)) 158 159 /***** Reset Source Status *****/ 160 #define PMU_RSTSRC_EXTRST PMU_STS_EXTRST 161 #define PMU_RSTSRC_PORST PMU_STS_PORST 162 #define PMU_RSTSRC_DPORST PMU_STS_DPORST 163 #define PMU_RSTSRC_WDTRST PMU_STS_WDTRST 164 #define PMU_RSTSRC_SFTRST PMU_STS_SFTRST 165 #define PMU_RSTSRC_MODERST PMU_STS_MODERST 166 #define PMU_RSTSRC_Msk (PMU_RSTSRC_EXTRST |\ 167 PMU_RSTSRC_PORST |\ 168 PMU_RSTSRC_DPORST |\ 169 PMU_RSTSRC_WDTRST |\ 170 PMU_RSTSRC_SFTRST |\ 171 PMU_RSTSRC_MODERST) 172 #define PMU_RSTSRC_ALL PMU_RSTSRC_Msk 173 #define PMU_RESETSRC(__RSTSRC__) (((__RSTSRC__) == PMU_RSTSRC_EXTRST) ||\ 174 ((__RSTSRC__) == PMU_RSTSRC_PORST) ||\ 175 ((__RSTSRC__) == PMU_RSTSRC_DPORST) ||\ 176 ((__RSTSRC__) == PMU_RSTSRC_WDTRST) ||\ 177 ((__RSTSRC__) == PMU_RSTSRC_SFTRST) ||\ 178 ((__RSTSRC__) == PMU_RSTSRC_MODERST)) 179 #define PMU_RESETSRC_CLR(__RSTSRC__) ((((__RSTSRC__) & PMU_RSTSRC_Msk) != 0UL) &&\ 180 (((__RSTSRC__) & (~PMU_RSTSRC_Msk)) == 0UL)) 181 182 /***** DeepSleep wakeup Source Status *****/ 183 #define PMU_DSLEEPWKUSRC_MODE PMU_STS_WKUMODE 184 #define PMU_DSLEEPWKUSRC_XTAL PMU_STS_WKUXTAL 185 #define PMU_DSLEEPWKUSRC_U32K PMU_STS_WKUU32K 186 #define PMU_DSLEEPWKUSRC_ANA PMU_STS_WKUANA 187 #define PMU_DSLEEPWKUSRC_RTC PMU_STS_WKURTC 188 #define PMU_DSLEEPWKUSRC_IOA PMU_STS_WKUIOA 189 #define PMU_DSLEEPWKUSRC_Msk (PMU_DSLEEPWKUSRC_MODE |\ 190 PMU_DSLEEPWKUSRC_XTAL |\ 191 PMU_DSLEEPWKUSRC_U32K |\ 192 PMU_DSLEEPWKUSRC_ANA |\ 193 PMU_DSLEEPWKUSRC_RTC |\ 194 PMU_DSLEEPWKUSRC_IOA) 195 #define IS_PMU_DSLEEPWKUSRC(__SRC__) (((__SRC__) == PMU_DSLEEPWKUSRC_MODE) ||\ 196 ((__SRC__) == PMU_DSLEEPWKUSRC_XTAL) ||\ 197 ((__SRC__) == PMU_DSLEEPWKUSRC_U32K) ||\ 198 ((__SRC__) == PMU_DSLEEPWKUSRC_ANA) ||\ 199 ((__SRC__) == PMU_DSLEEPWKUSRC_RTC) ||\ 200 ((__SRC__) == PMU_DSLEEPWKUSRC_IOA)) 201 202 203 //Status 204 #define PMU_STS_32K PMU_STS_EXIST_32K 205 #define PMU_STS_6M PMU_STS_EXIST_6M 206 #define IS_PMU_FLAG(__FLAG__) (((__FLAG__) == PMU_STS_32K) || ((__FLAG__) == PMU_STS_6M)) 207 208 //Wakeup_Event 209 #define IOA_DISABLE (0UL) 210 #define IOA_RISING (1UL) 211 #define IOA_FALLING (2UL) 212 #define IOA_HIGH (3UL) 213 #define IOA_LOW (4UL) 214 #define IOA_EDGEBOTH (5UL) 215 #define IS_PMU_WAKEUP(__WAKEUP__) (((__WAKEUP__) == IOA_DISABLE) ||\ 216 ((__WAKEUP__) == IOA_RISING) ||\ 217 ((__WAKEUP__) == IOA_FALLING) ||\ 218 ((__WAKEUP__) == IOA_HIGH) ||\ 219 ((__WAKEUP__) == IOA_LOW) ||\ 220 ((__WAKEUP__) == IOA_EDGEBOTH)) 221 222 /***** Wakeup_Event (PMU_SleepWKUSRCConfig_RTC) *****/ 223 #define PMU_RTCEVT_ALARM RTC_INTSTS_INTSTS10 224 #define PMU_RTCEVT_WKUCNT RTC_INTSTS_INTSTS6 225 #define PMU_RTCEVT_MIDNIGHT RTC_INTSTS_INTSTS5 226 #define PMU_RTCEVT_WKUHOUR RTC_INTSTS_INTSTS4 227 #define PMU_RTCEVT_WKUMIN RTC_INTSTS_INTSTS3 228 #define PMU_RTCEVT_WKUSEC RTC_INTSTS_INTSTS2 229 #define PMU_RTCEVT_TIMEILLE RTC_INTSTS_INTSTS1 230 #define PMU_RTCEVT_ITVSITV RTC_INTSTS_INTSTS0 231 #define PMU_RTCEVT_Msk (PMU_RTCEVT_WKUCNT \ 232 |PMU_RTCEVT_MIDNIGHT \ 233 |PMU_RTCEVT_WKUHOUR \ 234 |PMU_RTCEVT_WKUMIN \ 235 |PMU_RTCEVT_WKUSEC \ 236 |PMU_RTCEVT_TIMEILLE \ 237 |PMU_RTCEVT_ITVSITV \ 238 |PMU_RTCEVT_ALARM) 239 #define IS_PMU_RTCEVT(__RTCEVT__) ((((__RTCEVT__)&PMU_RTCEVT_Msk) != 0UL) &&\ 240 (((__RTCEVT__)&(~PMU_RTCEVT_Msk)) == 0UL)) 241 242 243 /***** BATRTCDisc (PMU_BATDischargeConfig) *****/ 244 #define PMU_BAT1 ANA_REG6_BAT1DISC 245 #define PMU_BATRTC ANA_REG6_BATRTCDISC 246 #define IS_PMU_BATRTCDISC(__BATRTCDISC__) (((__BATRTCDISC__) == PMU_BAT1) || ((__BATRTCDISC__) == PMU_BATRTC)) 247 248 /***** PowerThreshold (PMU_PowerAlarmTHConfig) *****/ 249 #define PMU_VDDALARM_4_5V ANA_REG8_VDDPVDSEL_0 250 #define PMU_VDDALARM_4_2V ANA_REG8_VDDPVDSEL_1 251 #define PMU_VDDALARM_3_9V ANA_REG8_VDDPVDSEL_2 252 #define PMU_VDDALARM_3_6V ANA_REG8_VDDPVDSEL_3 253 #define PMU_VDDALARM_3_2V ANA_REG8_VDDPVDSEL_4 254 #define PMU_VDDALARM_2_9V ANA_REG8_VDDPVDSEL_5 255 #define PMU_VDDALARM_2_6V ANA_REG8_VDDPVDSEL_6 256 #define PMU_VDDALARM_2_3V ANA_REG8_VDDPVDSEL_7 257 258 #define IS_PMU_VDDALARM_THR(__VDDALARM__) (((__VDDALARM__) == PMU_VDDALARM_4_5V) ||\ 259 ((__VDDALARM__) == PMU_VDDALARM_4_2V) ||\ 260 ((__VDDALARM__) == PMU_VDDALARM_3_9V) ||\ 261 ((__VDDALARM__) == PMU_VDDALARM_3_6V) ||\ 262 ((__VDDALARM__) == PMU_VDDALARM_3_2V) ||\ 263 ((__VDDALARM__) == PMU_VDDALARM_2_9V) ||\ 264 ((__VDDALARM__) == PMU_VDDALARM_2_6V) ||\ 265 ((__VDDALARM__) == PMU_VDDALARM_2_3V)) 266 267 /***** RTCLDOSel (PMU_RTCLDOConfig) *****/ 268 #define PMU_RTCLDO_1_5 (0UL) 269 #define PMU_RTCLDO_1_2 ANA_REGA_RTCVSEL 270 271 /***** StatusMask (PMU_GetPowerStatus) *****/ 272 #define PMU_PWRSTS_AVCCLV ANA_COMPOUT_AVCCLV 273 #define PMU_PWRSTS_VDCINDROP ANA_CMPOUT_VDCINDROP 274 #define PMU_PWRSTS_VDDALARM ANA_CMPOUT_VDDALARM 275 276 /***** PMU_PDNDSleepConfig *****/ 277 //VDCIN_PDNS 278 #define PMU_VDCINPDNS_0 (0UL) 279 #define PMU_VDCINPDNS_1 (ANA_CTRL_PDNS) 280 #define IS_PMU_VDCINPDNS(__VDCINPDNS__) (((__VDCINPDNS__) == PMU_VDCINPDNS_0) ||\ 281 ((__VDCINPDNS__) == PMU_VDCINPDNS_1)) 282 //VDD_PDNS 283 #define PMU_VDDPDNS_0 (0UL) 284 #define PMU_VDDPDNS_1 (ANA_CTRL_PDNS2) 285 #define IS_PMU_VDDPDNS(__VDDPDNS__) (((__VDDPDNS__) == PMU_VDDPDNS_0) ||\ 286 ((__VDDPDNS__) == PMU_VDDPDNS_1)) 287 288 #define PMU_VDDALARM_CHKFRE_NOCHECK (0x0UL << ANA_CMPCTL_VDDALARM_CHK_FRQ_SEL_Pos) 289 #define PMU_VDDALARM_CHKFRE_30US (0x1UL << ANA_CMPCTL_VDDALARM_CHK_FRQ_SEL_Pos) 290 #define IS_PMU_VDDALARM_CHKFRE(__CHKFRE__) (((__CHKFRE__) == PMU_VDDALARM_CHKFRE_NOCHECK) ||\ 291 ((__CHKFRE__) == PMU_VDDALARM_CHKFRE_30US)) 292 293 #define IS_PMU_PWR_DEBSEL(__DEBSEL__) ((__DEBSEL__) < 256UL) 294 295 /* Exported Functions ------------------------------------------------------- */ 296 297 uint32_t PMU_EnterDSleepMode(void); 298 void PMU_EnterIdleMode(void); 299 uint32_t PMU_EnterSleepMode(void); 300 301 void PMU_INTConfig(uint32_t INTMask, uint32_t NewState); 302 uint8_t PMU_GetINTStatus(uint32_t INTMask); 303 void PMU_ClearINTStatus(uint32_t INTMask); 304 305 uint8_t PMU_GetCrystalStatus(uint32_t Mask); 306 uint16_t PMU_GetIOAAllINTStatus(void); 307 uint8_t PMU_GetIOAINTStatus(uint16_t INTMask); 308 void PMU_ClearIOAINTStatus(uint16_t INTMask); 309 310 void PMU_WakeUpPinConfig(uint32_t IOAx, uint32_t Wakeup_Event); 311 312 uint8_t PMU_EnterDSleep_LowPower(PMU_LowPWRTypeDef *InitStruct); 313 uint8_t PMU_EnterSleep_LowPower(PMU_LowPWRTypeDef *InitStruct); 314 #ifndef __GNUC__ 315 void PMU_EnterIdle_LowPower(void); 316 #endif 317 void PMU_SleepWKUSRCConfig_IOA(uint16_t IOAx, uint32_t Wakeup_Event, uint32_t Priority); 318 void PMU_SleepWKUSRCConfig_RTC(uint32_t Wakeup_Event, uint32_t Priority); 319 void PMU_DeepSleepWKUSRCConfig_IOA(uint16_t IOAx, uint32_t Wakeup_Event); 320 void PMU_DeepSleepWKUSRCConfig_RTC(uint32_t Wakeup_Event); 321 void PMU_PDNDSleepConfig(uint32_t VDCIN_PDNS, uint32_t VDD_PDNS); 322 323 /***** BGP functions *****/ 324 void PMU_BGPCmd(uint32_t NewState); 325 326 /***** VDD functions *****/ 327 void PMU_VDDAlarmConfig(uint32_t CheckTHR, uint32_t CheckFrequency); 328 uint8_t PMU_GetVDDAlarmStatus(void); 329 330 /***** AVCC functions *****/ 331 void PMU_AVCCCmd(uint32_t NewState); 332 void PMU_AVCCOutputCmd(uint32_t NewState); 333 void PMU_AVCCLVDetectorCmd(uint32_t NewState); 334 uint8_t PMU_GetAVCCLVStatus(void); 335 336 /***** VDCIN functions *****/ 337 void PMU_VDCINDetectorCmd(uint32_t NewState); 338 uint8_t PMU_GetVDCINDropStatus(void); 339 340 void PMU_PWRDEBSel(uint32_t DEBSel); 341 342 /***** BAT functions *****/ 343 void PMU_BATDischargeConfig(uint32_t BATDisc, uint32_t NewState); 344 345 /***** Other functions *****/ 346 uint8_t PMU_GetModeStatus(void); 347 uint8_t PMU_GetPowerStatus(uint32_t StatusMask); 348 349 uint8_t PMU_GetResetSource(uint32_t Mask); 350 void PMU_ClearResetSource(uint32_t Mask); 351 uint32_t PMU_GetAllResetSource(void); 352 353 uint8_t PMU_GetDSleepWKUSource(uint32_t Mask); 354 uint32_t PMU_GetAllDSleepWKUSource(void); 355 356 #ifdef __cplusplus 357 } 358 #endif 359 360 #endif /* __LIB_PMU_H */ 361 362 /*********************************** END OF FILE ******************************/ 363