1 /**
2 ******************************************************************************
3 * @file lib_adc.c
4 * @author Application Team
5 * @version V1.1.0
6 * @date 2019-10-28
7 * @brief ADC library.
8 ******************************************************************************
9 * @attention
10 *
11 ******************************************************************************
12 */
13 #include "lib_adc.h"
14
15 #define ANA_INTEN_ADCMsk (0x3FC003U)
16 #define ANA_INTSTS_ADCMsk (0x3FC003U)
17 #define ANA_ADCCTRL0_RSTValue (0x300000U)
18 #define ANA_ADCCTRL1_RSTValue (0xC2U)
19 #define ANA_ADCCTRL2_RSTValue (0x8014U)
20 #define ANA_ADCDATATHD1_0_RSTValue (0U)
21 #define ANA_ADCDATATHD3_2_RSTValue (0U)
22 #define ANA_ADCDATATHD_CH_RSTValue (0U)
23 #define RTC_ADCUCALK_RSTValue (0x599A599AU)
24 #define RTC_ADCMACTL_RSTValue (0x78000000U)
25 #define RTC_ADCDTCTL_RSTValue (0x80000000)
26
27 #define ADC_SYNC_WR(); {__NOP(); __NOP(); __NOP(); __NOP();}
28 /**
29 * @brief Initializes ADC peripheral registers to their default reset values.
30 * @note 1. Disable ADC
31 2. Disable resistor division.
32 3. Disable ADC auto/manual done interrupt.
33 4. The ADC correlation (register) is written to the default value.
34 * @param None
35 * @retval None
36 */
ADC_DeInit(void)37 void ADC_DeInit(void)
38 {
39 uint32_t tmp[3];
40
41 if((ANA->ADCSTATE&0x07)!=0)
42 {
43 ADC_Cmd(DISABLE);
44 }
45
46 /* 6.5MHz clock. */
47 ANA->REG0 &= ~ANA_REG0_ADCFRQSEL;
48 /* ADC mode */
49 ANA->REG1 &= ~ANA_REG1_ADCMODESEL;
50 /* Power up VINBUF and REFBUF. */
51 ANA->REG11 &= ~(ANA_REG11_REFBUFPD|ANA_REG11_VINBUFPD);
52 /* Power down ADC */
53 ANA->ADCCTRL2 &= ~ANA_ADCCTRL2_ADC_EN;
54 /* Disable interrupt, Clear interrupt flag */
55 ANA->INTEN &= ~ANA_INTEN_ADCMsk;
56 ANA->INTSTS = ANA_INTSTS_ADCMsk;
57 while (ANA->ADCCTRL0 & ANA_ADCCTRL0_MTRIG);
58 ANA->ADCCTRL0 = ANA_ADCCTRL0_RSTValue;
59 while (ANA->ADCCTRL0 & ANA_ADCCTRL0_MTRIG);
60 ANA->ADCCTRL1 = ANA_ADCCTRL1_RSTValue;
61 ANA->ADCCTRL2 = ANA_ADCCTRL2_RSTValue|ANA_ADCCTRL2_CONV_ERR_CLR|ANA_ADCCTRL2_CAL_ERR_CLR;
62
63 ANA->ADCDATATHD1_0= ANA_ADCDATATHD1_0_RSTValue;
64 ANA->ADCDATATHD3_2 = ANA_ADCDATATHD3_2_RSTValue;
65 ANA->ADCDATATHD_CH = ANA_ADCDATATHD_CH_RSTValue;
66 tmp[0] = RTC_ADCUCALK_RSTValue;
67 tmp[1] = RTC_ADCMACTL_RSTValue;
68 tmp[2] = RTC_ADCDTCTL_RSTValue;
69 RTC_WriteRegisters((uint32_t)&RTC->ADCUCALK, tmp, 3);
70
71 ANA->ADCCTRL2 = ANA_ADCCTRL2_RSTValue;
72 }
73
74 /**
75 * @brief Fills each ADC_InitStruct member with its default value.
76 * @param ADC_InitStruct: pointer to an ADC_InitType structure which will be initialized.
77 * @retval None
78 */
ADC_StructInit(ADC_InitType * ADC_InitStruct)79 void ADC_StructInit(ADC_InitType* ADC_InitStruct)
80 {
81 /*------ Reset ADC init structure parameters values ------*/
82 ADC_InitStruct->Mode = ADC_MODE_DC;
83 ADC_InitStruct->ClockSource = ADC_CLKSRC_RCH;
84 ADC_InitStruct->ClockFrq = ADC_CLKFRQ_HIGH;
85 ADC_InitStruct->SkipSample = ADC_SKIP_0;
86 ADC_InitStruct->AverageSample = ADC_AVERAGE_2;
87 ADC_InitStruct->TriggerSource = ADC_TRIGSOURCE_OFF;
88 ADC_InitStruct->Channel = ADC_CHANNEL_GND0;
89 ADC_InitStruct->ResDivEnable = 0;
90 ADC_InitStruct->AverageEnable = 0;
91 }
92
93 /**
94 * @brief Initializes ADC.
95 * @param ADC_InitStruct: pointer to an ADC_InitType structure which will be initialized.
96 Mode:
97 ADC_MODE_DC (Not include ADC_CHANNEL_TEMP)
98 ADC_MODE_AC (Only ADC_CHANNEL_CHx be valid)
99 ADC_MODE_TEMP (Only ADC_CHANNEL_TEMP be valid)
100 ClockSource: \n
101 ADC_CLKSRC_RCH \n
102 ADC_CLKSRC_PLLL \n
103 ClockFrq: \n
104 ADC_CLKFRQ_HIGH \n
105 ADC_CLKFRQ_LOW \n
106 SkipSample: \n
107 ADC_SKIP_0 \n
108 ADC_SKIP_4 \n
109 ADC_SKIP_8 \n
110 ADC_SKIP_12 \n
111 AverageSample: \n
112 ADC_AVERAGE_2 \n
113 ADC_AVERAGE_4 \n
114 ADC_AVERAGE_8 \n
115 ADC_AVERAGE_16 \n
116 ADC_AVERAGE_32 \n
117 ADC_AVERAGE_64 \n
118 TriggerSource: \n
119 ADC_TRIGSOURCE_OFF \n
120 ADC_TRIGSOURCE_ITVSITV \n
121 ADC_TRIGSOURCE_WKUSEC \n
122 ADC_TRIGSOURCE_ALARM \n
123 ADC_TRIGSOURCE_TMR0 \n
124 ADC_TRIGSOURCE_TMR1 \n
125 ADC_TRIGSOURCE_TMR2 \n
126 ADC_TRIGSOURCE_TMR3 \n
127 Channel:
128 ResDivEnable: (also can be ADC_CHANNEL_NONE)
129 AverageEnable: (also can be ADC_CHANNEL_NONE)
130 ADC_CHANNEL_GND0
131 ADC_CHANNEL_BAT1
132 ADC_CHANNEL_BATRTC
133 ADC_CHANNEL_CH3
134 ADC_CHANNEL_CH4
135 ADC_CHANNEL_CH5
136 ADC_CHANNEL_CH6
137 ADC_CHANNEL_CH7
138 ADC_CHANNEL_CH8
139 ADC_CHANNEL_CH9
140 ADC_CHANNEL_TEMP
141 ADC_CHANNEL_CH11
142 ADC_CHANNEL_DVCC
143 ADC_CHANNEL_GND13
144 ADC_CHANNEL_GND14
145 ADC_CHANNEL_GND15
146 ADC_CHANNEL_DC_ALL
147 ADC_CHANNEL_AC_ALL
148 * @retval None
149 */
ADC_Init(ADC_InitType * ADC_InitStruct)150 void ADC_Init(ADC_InitType *ADC_InitStruct)
151 {
152 uint32_t tmp_anareg0, tmp_anareg1, tmp_anareg3, tmp_anareg11;
153 uint32_t tmp_adcctrl0, tmp_adcctrl1, tmp_adcctrl2;
154 uint32_t tmp_rtcadcmactl;
155
156 /* Check parameters */
157 assert_parameters(IS_ADC_MODE(ADC_InitStruct->Mode));
158 assert_parameters(IS_ADC_CLKSRC(ADC_InitStruct->ClockSource));
159 assert_parameters(IS_ADC_CLKFRQ(ADC_InitStruct->ClockFrq));
160 assert_parameters(IS_ADC_SKIP(ADC_InitStruct->SkipSample));
161 assert_parameters(IS_ADC_AVERAG(ADC_InitStruct->AverageSample));
162 assert_parameters(IS_ADC_TRIGSOURCE(ADC_InitStruct->TriggerSource));
163
164 while (ANA->ADCCTRL0 & ANA_ADCCTRL0_MTRIG);
165 ANA->ADCCTRL2 &= ~ANA_ADCCTRL2_ADC_EN;
166
167 tmp_adcctrl0 = ANA->ADCCTRL0;
168 tmp_adcctrl1 = ANA->ADCCTRL1;
169 tmp_adcctrl2 = ANA->ADCCTRL2;
170 tmp_anareg0 = ANA->REG0;
171 tmp_anareg1 = ANA->REG1;
172 tmp_anareg3 = ANA->REG3;
173 tmp_anareg11 = 0;
174 tmp_rtcadcmactl = RTC->ADCMACTL;
175
176 /* Configure clock source and trigger source */
177 tmp_adcctrl0 &= ~(ANA_ADCCTRL0_AEN | ANA_ADCCTRL0_CLKSRCSEL);
178 tmp_adcctrl0 |= (ADC_InitStruct->TriggerSource | ADC_InitStruct->ClockSource);
179
180 /* Configure ClockFrq */
181 if (ADC_InitStruct->ClockFrq == ADC_CLKFRQ_HIGH)
182 {
183 tmp_anareg0 &= ~ANA_REG0_ADCFRQSEL;
184 tmp_adcctrl2 &= ~ANA_ADCCTRL2_ADCCR;
185 }
186 else
187 {
188 tmp_anareg0 |= ANA_REG0_ADCFRQSEL;
189 tmp_adcctrl2 |= ANA_ADCCTRL2_ADCCR;
190 }
191
192 /* Configure skip samples and average samples */
193 tmp_rtcadcmactl &= ~(RTC_ADCMACTL_SKIP_SAMPLE | RTC_ADCMACTL_AVERAGE_SAMPLE);
194 tmp_rtcadcmactl |= (ADC_InitStruct->SkipSample | ADC_InitStruct->AverageSample);
195
196 /* Mode: DC */
197 if (ADC_InitStruct->Mode == ADC_MODE_DC)
198 {
199 /* Check parameters */
200 assert_parameters(IS_ADC_CHANNEL_DC(ADC_InitStruct->Channel));
201 assert_parameters(IS_ADC_CHANNEL_EN_DC(ADC_InitStruct->AverageEnable));
202 assert_parameters(IS_ADC_CHANNEL_EN_DC(ADC_InitStruct->ResDivEnable));
203
204 /* Enable or disable Channels */
205 tmp_adcctrl2 &= ~ANA_ADCCTRL2_SCAN_CHx;
206 tmp_adcctrl2 |= (ADC_InitStruct->Channel << ADC_CHANNEL_SHIFT);
207 /* Enable or disable average */
208 tmp_rtcadcmactl &= ~RTC_ADCMACTL_AVERAGE_CHx;
209 tmp_rtcadcmactl |= (ADC_InitStruct->AverageEnable << ADC_AVERAGECH_SHIFT);
210 /* Enable or disable RESDIV */
211 tmp_adcctrl1 &= ~ANA_ADCCTRL1_RESDIV_CHx;
212 tmp_adcctrl1 |= (ADC_InitStruct->ResDivEnable << ADC_RESDIVCH_SHIFT);
213 /* Others */
214 tmp_anareg1 &= ~ANA_REG1_ADCMODESEL;
215 }
216 /* Mode: AC */
217 else if (ADC_InitStruct->Mode == ADC_MODE_AC)
218 {
219 /* Check parameters */
220 assert_parameters(IS_ADC_CHANNEL_AC(ADC_InitStruct->Channel));
221 assert_parameters(IS_ADC_CHANNEL_EN_AC(ADC_InitStruct->AverageEnable));
222
223 /* Enable or disable Channels */
224 tmp_adcctrl2 &= ~ANA_ADCCTRL2_SCAN_CHx;
225 tmp_adcctrl2 |= (ADC_InitStruct->Channel << ADC_CHANNEL_SHIFT);
226 /* Enable or disable average */
227 tmp_rtcadcmactl &= ~RTC_ADCMACTL_AVERAGE_CHx;
228 tmp_rtcadcmactl |= (ADC_InitStruct->AverageEnable << ADC_AVERAGECH_SHIFT);
229 /* Enable or disable RESDIV */
230 tmp_adcctrl1 &= ~ANA_ADCCTRL1_RESDIV_CHx;
231 tmp_adcctrl1 |= (ADC_InitStruct->Channel << ADC_RESDIVCH_SHIFT);
232 /* Others */
233 tmp_anareg1 |= ANA_REG1_ADCMODESEL;
234 }
235 /* Mode: TEMP */
236 else
237 {
238 /* Check parameters */
239 assert_parameters(IS_ADC_CHANNEL_TEMP(ADC_InitStruct->Channel));
240
241 /* Enable ADC_CHANNEL_TEMP */
242 tmp_adcctrl2 &= ~ANA_ADCCTRL2_SCAN_CHx;
243 tmp_adcctrl2 |= (ADC_CHANNEL_TEMP << ADC_CHANNEL_SHIFT);
244 /* Enable average */
245 tmp_rtcadcmactl &= ~RTC_ADCMACTL_AVERAGE_CHx;
246 tmp_rtcadcmactl |= (ADC_CHANNEL_TEMP << ADC_AVERAGECH_SHIFT);
247 /* Disable RESDIV */
248 tmp_adcctrl1 &= ~ANA_ADCCTRL1_RESDIV_CHx;
249 /* Others */
250 tmp_anareg1 &= ~ANA_REG1_ADCMODESEL;
251 if(ADC_InitStruct->ClockFrq == ADC_CLKFRQ_LOW)
252 {
253 /* It can improve the accuracy of temperature measurement */
254 tmp_anareg11 |= (ANA_REG11_VINBUFPD | ANA_REG11_REFBUFPD);
255 }
256 }
257
258 ANA->ADCCTRL0 = tmp_adcctrl0&(~ANA_ADCCTRL0_MTRIG);
259 ANA->ADCCTRL1 = tmp_adcctrl1;
260 ANA->ADCCTRL2 = tmp_adcctrl2;
261 ANA->REG0 = tmp_anareg0;
262 ANA->REG1 = tmp_anareg1;
263 ANA->REG3 = tmp_anareg3;
264 ANA->REG11 = tmp_anareg11;
265 RTC_WriteRegisters((uint32_t)&RTC->ADCMACTL, &tmp_rtcadcmactl, 1);
266 }
267
268 /**
269 * @brief Fills each ADCTHD_InitType member with its default value.
270 * @param ADC_THDStruct: pointer to an ADC_THDStruct structure which will be initialized.
271 * @retval None
272 */
ADC_THDStructInit(ADCTHD_InitType * ADC_THDStruct)273 void ADC_THDStructInit(ADCTHD_InitType* ADC_THDStruct)
274 {
275 ADC_THDStruct->THDChannel = ADC_THDCHANNEL0;
276 ADC_THDStruct->UpperTHD = 0x0000;
277 ADC_THDStruct->LowerTHD = 0x0000;
278 ADC_THDStruct->TriggerSel = ADC_THDSEL_HIGH;
279 ADC_THDStruct->THDSource = ADC_CHANNEL_GND0;
280 }
281
282 /**
283 * @brief Initializes ADC threshold.
284 * @param ADC_THDStruct:
285 * THDChannel:
286 * ADC_THDCHANNEL0
287 * ADC_THDCHANNEL1
288 * ADC_THDCHANNEL2
289 * ADC_THDCHANNEL3
290 * UpperTHD:
291 * 0~0xFF
292 * LowerTHD:
293 * 0~0xFF
294 * TriggerSel:
295 * ADC_THDSEL_HIGH
296 * ADC_THDSEL_RISING
297 * ADC_THDSEL_FALLING
298 * ADC_THDSEL_BOTH
299 * THDSource:
300 * ADC_CHANNEL_GND0
301 * ADC_CHANNEL_BAT1
302 * ADC_CHANNEL_BATRTC
303 * ADC_CHANNEL_CH3
304 * ADC_CHANNEL_CH4
305 * ADC_CHANNEL_CH5
306 * ADC_CHANNEL_CH6
307 * ADC_CHANNEL_CH7
308 * ADC_CHANNEL_CH8
309 * ADC_CHANNEL_CH9
310 * ADC_CHANNEL_TEMP
311 * ADC_CHANNEL_CH11
312 * ADC_CHANNEL_DVCC
313 * ADC_CHANNEL_GND13
314 * ADC_CHANNEL_GND14
315 * ADC_CHANNEL_GND15
316 * @retval None
317 */
ADC_THDInit(ADCTHD_InitType * ADC_THDStruct)318 void ADC_THDInit(ADCTHD_InitType* ADC_THDStruct)
319 {
320 uint32_t tmp = 0;
321 uint32_t position = 0x00U;
322 uint32_t currentch = 0x00U;
323
324 /* Check parameters */
325 assert_parameters(IS_ADC_THDCHANNEL(ADC_THDStruct->THDChannel));
326 assert_parameters(IS_ADC_THDSEL(ADC_THDStruct->TriggerSel));
327 assert_parameters(IS_ADC_CHANNEL_GETDATA(ADC_THDStruct->THDSource));
328
329 while ((ADC_THDStruct->THDSource >> position) != 0U)
330 {
331 /* Get current ch position */
332 currentch = ADC_THDStruct->THDSource & (0x01U << position);
333
334 if (currentch)
335 {
336 break;
337 }
338 position++;
339 }
340
341 if ((ADC_THDStruct->THDChannel == ADC_THDCHANNEL0) || (ADC_THDStruct->THDChannel == ADC_THDCHANNEL1))
342 {
343 ANA->ADCDATATHD1_0 &= ~((ANA_ADCDATATHD1_0_LOWER_THD0|ANA_ADCDATATHD1_0_UPPER_THD0) << (16*ADC_THDStruct->THDChannel));
344 ANA->ADCDATATHD1_0 |= (((ADC_THDStruct->UpperTHD<<8)|ADC_THDStruct->LowerTHD) << (16*ADC_THDStruct->THDChannel));
345 }
346 else
347 {
348 ANA->ADCDATATHD3_2 &= ~((ANA_ADCDATATHD3_2_LOWER_THD2|ANA_ADCDATATHD3_2_UPPER_THD2) << (16*(ADC_THDStruct->THDChannel - 2)));
349 ANA->ADCDATATHD3_2 |= (((ADC_THDStruct->UpperTHD<<8)|ADC_THDStruct->LowerTHD) << (16*(ADC_THDStruct->THDChannel - 2)));
350 }
351
352 tmp = ANA->ADCDATATHD_CH;
353 tmp &= ~(ANA_ADCDATATHD_CH_THD0_SEL << (ADC_THDStruct->THDChannel*2));
354 tmp |= (ADC_THDStruct->TriggerSel << (ADC_THDStruct->THDChannel*2 + ANA_ADCDATATHD_CH_THD0_SEL_Pos));
355
356 tmp &= ~(ANA_ADCDATATHD_CH_THD0_CH << (ADC_THDStruct->THDChannel*4));
357 tmp |= (position << (ADC_THDStruct->THDChannel*4+ANA_ADCDATATHD_CH_THD0_CH_Pos));
358
359 ANA->ADCDATATHD_CH = tmp;
360 }
361
362 /**
363 * @brief Starts a ADC calibration (ADC calibration is implemented when DPORST or ADC RESET happened).
364 * @param None
365 * @retval None
366 */
ADC_Calibration(void)367 void ADC_Calibration(void)
368 {
369 volatile uint32_t i;
370
371 // if ((ANA->ADCCTRL2 & ANA_ADCCTRL2_RTC_CAL_DONE) && (ANA->ADCDOS != 0))
372 // return;
373 //Disable ADC
374 ADCCALSTART:
375 ANA->ADCCTRL2 &= ~ANA_ADCCTRL2_ADC_EN;
376 ANA->ADCCTRL2 |= ANA_ADCCTRL2_CAL_ERR_CLR;
377 ADC_SYNC_WR();
378 //Set 6.5M ADC clock
379 ANA->REG0 &= ~ANA_REG0_ADCFRQSEL;
380 ADC_SYNC_WR();
381 while (ANA->ADCCTRL0 & ANA_ADCCTRL0_MTRIG);
382 //ADC STOP
383 ANA->ADCCTRL0 = ANA_ADCCTRL0_RSTValue|ANA_ADCCTRL0_STOP;
384 ADC_SYNC_WR();
385 ANA->ADCCTRL0 = ANA_ADCCTRL0_RSTValue;
386 ADC_SYNC_WR();
387 //Reset ADC
388 ANA->ADCCTRL2 = ANA_ADCCTRL2_RSTValue | ANA_ADCCTRL2_RESET;
389 ADC_SYNC_WR();
390 ANA->ADCCTRL2 = ANA_ADCCTRL2_RSTValue;
391 ADC_SYNC_WR();
392 //Enable ADC TRG_CAL
393 ANA->ADCCTRL2 |= ANA_ADCCTRL2_ADC_EN_TRG_CAL;
394 ADC_SYNC_WR();
395 ANA->ADCCTRL2 |= ANA_ADCCTRL2_ADC_EN;
396 ADC_SYNC_WR();
397 /* while loop until ADC calibration is done */
398 ADC_SYNC_WR();
399 while (!(ANA->ADCCTRL2 & ANA_ADCCTRL2_RTC_CAL_DONE))
400 {
401 }
402 if(ANA->ADCCTRL2 & ANA_ADCCTRL2_CAL_ERR)
403 {
404 goto ADCCALSTART;
405 }
406 ANA->ADCCTRL2 &= ~ANA_ADCCTRL2_ADC_EN_TRG_CAL;
407 ADC_SYNC_WR();
408 ANA->ADCCTRL2 &= ~ANA_ADCCTRL2_ADC_EN;
409 ADC_SYNC_WR();
410
411 }
412
413 /**
414 * @brief Calculates ADC value via ADC original data.
415 * @param [in]Mode:
416 ADC_3V_ADCCHx_NODIV
417 ADC_3V_ADCCHx_RESDIV
418 ADC_3V_BAT1_RESDIV
419 ADC_3V_BATRTC_RESDIV
420 ADC_5V_ADCCHx_NODIV
421 ADC_5V_ADCCHx_RESDIV
422 ADC_5V_BAT1_RESDIV
423 ADC_5V_BATRTC_RESDIV
424 ADC_TEMP
425 * @param [in]adc_data: The ADC original data
426 * @param [out]value: The pointer of value calculated by this function
427 * @retval 1 NVR checksum error.
428 0 Function successed.
429 */
ADC_CalculateValue(uint32_t Mode,int16_t adc_data,int16_t * value)430 uint32_t ADC_CalculateValue(uint32_t Mode, int16_t adc_data, int16_t *value)
431 {
432 NVR_ADCVOLPARA parameter;
433 NVR_TempParams TempParams;
434
435 /* Check parameters */
436 assert_parameters(IS_ADCVOL_MODE(Mode));
437
438 if (Mode == ADC_TEMP)
439 {
440 if (NVR_GetTempParameters(&TempParams))
441 {
442 return 1;
443 }
444 else
445 {
446 /* Calculate temperature */
447 *value = ((TempParams.RTCTempP0 * ((adc_data*adc_data)>>16)) + TempParams.RTCTempP1*adc_data + TempParams.RTCTempP2) >> 8;
448 }
449 }
450 else
451 {
452 if (NVR_GetVoltageParameters(Mode, ¶meter))
453 {
454 return 1;
455 }
456 else
457 {
458 *value = (int16_t)((parameter.aParameter*(float)adc_data + parameter.bParameter) + parameter.OffsetParameter);
459 }
460 }
461
462 return 0;
463 }
464
465 /**
466 * @brief Enables or disables ADC.
467 * @note None
468 * @param NewState
469 ENABLE
470 DISABLE
471 * @retval None
472 */
ADC_Cmd(uint32_t NewState)473 void ADC_Cmd(uint32_t NewState)
474 {
475 __IO uint32_t dly = 400UL;
476
477 /* Check parameters */
478 assert_parameters(IS_FUNCTIONAL_STATE(NewState));
479 while (ANA->ADCCTRL0 & ANA_ADCCTRL0_MTRIG);
480 if (NewState == DISABLE)
481 {
482 if(ANA->ADCSTATE & ANA_ADCSTATE_ADCSTATE)
483 {
484 ANA->ADCCTRL0 |= ANA_ADCCTRL0_STOP;
485 if ((MISC2->CLKSEL&MISC2_CLKSEL_CLKSEL) == MISC2_CLKSEL_CLKSEL_RTCCLK)
486 {
487 __NOP();
488 __NOP();
489 }
490 else
491 {
492 while (dly--)
493 __NOP();
494 }
495 ANA->ADCCTRL0 &= ~ANA_ADCCTRL0_STOP;
496 }
497 ANA->ADCCTRL2 &= ~ANA_ADCCTRL2_ADC_EN;
498 }
499 else
500 {
501 ANA->ADCCTRL0 &= ~ANA_ADCCTRL0_STOP;
502 ANA->ADCCTRL2 |= ANA_ADCCTRL2_ADC_EN;
503
504 if ((MISC2->CLKSEL&MISC2_CLKSEL_CLKSEL) == MISC2_CLKSEL_CLKSEL_RTCCLK)
505 {
506 __NOP();
507 __NOP();
508 }
509 else
510 {
511 while (dly--)
512 __NOP();
513 }
514 /* Start Manual ADC conversion */
515 ADC_StartManual();
516 /* Waiting Manual ADC conversion done */
517 ADC_WaitForManual();
518 }
519 }
520
521 /**
522 * @brief Enables or disables ADC lower threshold detect function.
523 * @note None
524 * @param THDChannel:
525 ADC_THDCHANNEL0~ADC_THDCHANNEL3
526 NewState
527 ENABLE
528 DISABLE
529 * @retval None
530 */
ADC_LowerTHDCmd(uint32_t THDChannel,uint32_t NewState)531 void ADC_LowerTHDCmd(uint32_t THDChannel,uint32_t NewState)
532 {
533 /* Check parameters */
534 assert_parameters(IS_ADC_THDCHANNEL(THDChannel));
535 assert_parameters(IS_FUNCTIONAL_STATE(NewState));
536
537 if (NewState == DISABLE)
538 {
539 ANA->ADCCTRL1 &= ~(ANA_ADCCTRL1_LOWER_THD0_EN << (THDChannel*2));
540 }
541 else
542 {
543 ANA->ADCCTRL1 |= (ANA_ADCCTRL1_LOWER_THD0_EN << (THDChannel*2));
544 }
545 }
546
547 /**
548 * @brief Enables or disables ADC upper threshold detect function.
549 * @note None
550 * @param THDChannel:
551 IS_ADC_THDCHANNEL0~IS_ADC_THDCHANNEL3
552 NewState
553 ENABLE
554 DISABLE
555 * @retval None
556 */
ADC_UpperTHDCmd(uint32_t THDChannel,uint32_t NewState)557 void ADC_UpperTHDCmd(uint32_t THDChannel,uint32_t NewState)
558 {
559 /* Check parameters */
560 assert_parameters(IS_ADC_THDCHANNEL(THDChannel));
561 assert_parameters(IS_FUNCTIONAL_STATE(NewState));
562
563 if (NewState == DISABLE)
564 {
565 ANA->ADCCTRL1 &= ~(ANA_ADCCTRL1_UPPER_THD0_EN << (THDChannel*2));
566 }
567 else
568 {
569 ANA->ADCCTRL1 |= (ANA_ADCCTRL1_UPPER_THD0_EN << (THDChannel*2));
570 }
571 }
572
573 /**
574 * @brief Starts a ADC manual-trigger.
575 * @param None
576 * @retval None
577 */
ADC_StartManual(void)578 void ADC_StartManual(void)
579 {
580 while (ANA->ADCCTRL0 & ANA_ADCCTRL0_MTRIG);
581 ANA->ADCCTRL0 |= ANA_ADCCTRL0_MTRIG;
582 }
583
584 /**
585 * @brief Waits until the last Manual ADC conversion done.
586 * @param None
587 * @retval None
588 */
ADC_WaitForManual(void)589 void ADC_WaitForManual(void)
590 {
591 while (ANA->ADCCTRL0 & ANA_ADCCTRL0_MTRIG)
592 {
593 }
594 }
595
596 /**
597 * @brief Gets ADC vonversion value.
598 * @param Channel:
599 * ADC_CHANNEL_GND0
600 * ADC_CHANNEL_BAT1
601 * ADC_CHANNEL_BATRTC
602 * ADC_CHANNEL_CH3
603 * ADC_CHANNEL_CH4
604 * ADC_CHANNEL_CH5
605 * ADC_CHANNEL_CH6
606 * ADC_CHANNEL_CH7
607 * ADC_CHANNEL_CH8
608 * ADC_CHANNEL_CH9
609 * ADC_CHANNEL_TEMP
610 * ADC_CHANNEL_CH11
611 * ADC_CHANNEL_DVCC
612 * ADC_CHANNEL_GND13
613 * ADC_CHANNEL_GND14
614 * ADC_CHANNEL_GND15
615 * @retval ADC conversion value.
616 */
ADC_GetADCConversionValue(uint32_t Channel)617 int16_t ADC_GetADCConversionValue(uint32_t Channel)
618 {
619 uint32_t position = 0x0000UL;
620 uint32_t chcurrent = 0x0000UL;
621
622 /* Check parameters */
623 assert_parameters(IS_ADC_CHANNEL_GETDATA(Channel));
624
625 while ((Channel >> position) != 0UL)
626 {
627 chcurrent = Channel & (0x01U << position);
628 if (chcurrent)
629 break;
630 position++;
631 }
632 return (ANA->ADCDATA[position]);
633 }
634
635 /**
636 * @brief Enables or disables ADC interrupt.
637 * @param INTMask: can use the '|' operator
638 ADC_INT_UPPER_TH3
639 ADC_INT_LOWER_TH3
640 ADC_INT_UPPER_TH2
641 ADC_INT_LOWER_TH2
642 ADC_INT_UPPER_TH1
643 ADC_INT_LOWER_TH1
644 ADC_INT_UPPER_TH0
645 ADC_INT_LOWER_TH0
646 ADC_INT_AUTODONE
647 ADC_INT_MANUALDONE
648 NewState
649 ENABLE
650 DISABLE
651 * @retval None
652 */
ADC_INTConfig(uint32_t INTMask,uint32_t NewState)653 void ADC_INTConfig(uint32_t INTMask, uint32_t NewState)
654 {
655 /* Check parameters */
656 assert_parameters(IS_FUNCTIONAL_STATE(NewState));
657 assert_parameters(IS_ADC_INT(INTMask));
658
659 if (NewState == ENABLE)
660 ANA->INTEN |= INTMask;
661 else
662 ANA->INTEN &= ~INTMask;
663 }
664
665 /**
666 * @brief Clears ADC interrupt status.
667 * @param INTMask: can use the '|' operator
668 ADC_INTSTS_UPPER_TH3
669 ADC_INTSTS_LOWER_TH3
670 ADC_INTSTS_UPPER_TH2
671 ADC_INTSTS_LOWER_TH2
672 ADC_INTSTS_UPPER_TH1
673 ADC_INTSTS_LOWER_TH1
674 ADC_INTSTS_UPPER_TH0
675 ADC_INTSTS_LOWER_TH0
676 ADC_INTSTS_AUTODONE
677 ADC_INTSTS_MANUALDONE
678 * @retval None
679 */
ADC_ClearINTStatus(uint32_t INTMask)680 void ADC_ClearINTStatus(uint32_t INTMask)
681 {
682 /* Parameter check */
683 assert_parameters(IS_ADC_INTFLAGC(INTMask));
684
685 ANA->INTSTS = INTMask;
686 }
687
688 /**
689 * @brief Gets ADC interrupt status.
690 * @param INTMask:
691 ADC_INTSTS_UPPER_TH3
692 ADC_INTSTS_LOWER_TH3
693 ADC_INTSTS_UPPER_TH2
694 ADC_INTSTS_LOWER_TH2
695 ADC_INTSTS_UPPER_TH1
696 ADC_INTSTS_LOWER_TH1
697 ADC_INTSTS_UPPER_TH0
698 ADC_INTSTS_LOWER_TH0
699 ADC_INTSTS_AUTODONE
700 ADC_INTSTS_MANUALDONE
701 * @retval 1: status set
702 0: status reset.
703 */
ADC_GetINTStatus(uint32_t INTMask)704 uint8_t ADC_GetINTStatus(uint32_t INTMask)
705 {
706 /* Parameter check */
707 assert_parameters(IS_ADC_INTFLAGR(INTMask));
708
709 if (ANA->INTSTS & INTMask)
710 {
711 return 1;
712 }
713 else
714 {
715 return 0;
716 }
717 }
718
719 /**
720 * @brief Gets ADC flag
721 * @param FlagMask
722 ADC_FLAG_CONV_ERR
723 ADC_FLAG_CAL_ERR
724 ADC_FLAG_CAL_DONE
725 ADC_FLAG_BUSY
726 * @retval 1 flag set
727 * 0 flag reset.
728 */
ADC_GetFlag(uint32_t FlagMask)729 uint8_t ADC_GetFlag(uint32_t FlagMask)
730 {
731 /* Parameter check */
732 assert_parameters(IS_ADC_ADCFLAG(FlagMask));
733
734 if (ANA->ADCCTRL2 & FlagMask)
735 return 1;
736 else
737 return 0;
738 }
739
740 /**
741 * @brief Clears ADC flag
742 * @param FlagMask: status to clear, can use the '|' operator.
743 ADC_FLAG_CONV_ERR
744 ADC_FLAG_CAL_ERR
745 * @retval None
746 */
ADC_ClearFlag(uint32_t FlagMask)747 void ADC_ClearFlag(uint32_t FlagMask)
748 {
749 uint32_t tmp;
750
751 /* Parameter check */
752 assert_parameters(IS_ADC_ADCFLAGC(FlagMask));
753
754 if (FlagMask == ADC_FLAG_CONV_ERR)
755 {
756 tmp = ANA->ADCCTRL2;
757 tmp &= ~ANA_ADCCTRL2_CAL_ERR_CLR;
758 tmp |= ANA_ADCCTRL2_CONV_ERR_CLR;
759 }
760 else if (FlagMask == ADC_FLAG_CAL_ERR)
761 {
762 tmp = ANA->ADCCTRL2;
763 tmp &= ~ANA_ADCCTRL2_CONV_ERR_CLR;
764 tmp |= ANA_ADCCTRL2_CAL_ERR_CLR;
765 }
766 else
767 {
768 tmp = ANA->ADCCTRL2;
769 tmp |= (ANA_ADCCTRL2_CAL_ERR_CLR | ANA_ADCCTRL2_CONV_ERR_CLR);
770 }
771 ANA->ADCCTRL2 = tmp;
772 }
773
774 /**
775 * @brief Gets threshold flag
776 * @param THDFlagMask
777 ADC_THDFLAG_UPPER3
778 ADC_THDFLAG_LOWER3
779 ADC_THDFLAG_UPPER2
780 ADC_THDFLAG_LOWER2
781 ADC_THDFLAG_UPPER1
782 ADC_THDFLAG_LOWER1
783 ADC_THDFLAG_UPPER0
784 ADC_THDFLAG_LOWER0
785 * @retval 1 flag set
786 * 0 flag reset.
787 */
ADC_GetTHDFlag(uint32_t THDFlagMask)788 uint8_t ADC_GetTHDFlag(uint32_t THDFlagMask)
789 {
790 /* Parameter check */
791 assert_parameters(IS_ADC_THDFLAG(THDFlagMask));
792
793 if(ANA->ADCDATATHD_CH & THDFlagMask)
794 return 1;
795 else
796 return 0;
797 }
798
799 /*********************************** END OF FILE ******************************/
800