1 /**
2 ******************************************************************************
3 * @file lib_clk.c
4 * @author Application Team
5 * @version V1.1.0
6 * @date 2019-10-28
7 * @brief Clock library.
8 ******************************************************************************
9 * @attention
10 *
11 ******************************************************************************
12 */
13 #include "lib_clk.h"
14
15 /**
16 * @brief Initializes the CPU, AHB and APB buses clocks according to the specified
17 * parameters in the CLK_ClkInitStruct.
18 *
19 * @note This function performs the following:
20 * 1. If want to switch AHB clock source, enable BGP, enable 6.5M RC,
21 * AHB clock source switch to RCH first.
22 * 2. configure clock (except AHB clock source configuration). - optional
23 * 3. configure AHB clock source. - optional
24 * 4. HCLK/PCLK divider configuration. - optional
25 *
26 * @note CLK_InitTypeDef *CLK_ClkInitStruct
27 * [in]CLK_ClkInitStruct->ClockType, can use the '|' operator, the selection of parameters is as follows
28 * CLK_TYPE_ALL
29 * CLK_TYPE_AHBSRC
30 * CLK_TYPE_PLLL
31 * CLK_TYPE_PLLH
32 * CLK_TYPE_XTALH
33 * CLK_TYPE_RTCCLK
34 * CLK_TYPE_HCLK
35 * CLK_TYPE_PCLK
36 *
37 * CLK_TYPE_ALL All clocks' configurations is valid
38 * CLK_TYPE_AHBSRC CLK_ClkInitStruct->AHBSource(AHB Clock source configuration) is valid
39 * [in]CLK_ClkInitStruct->AHBSource:
40 * CLK_AHBSEL_6_5MRC
41 * CLK_AHBSEL_6_5MXTAL
42 * CLK_AHBSEL_HSPLL
43 * CLK_AHBSEL_RTCCLK
44 * CLK_AHBSEL_LSPLL
45 * CLK_TYPE_PLLL CLK_ClkInitStruct->PLLL(PLLL configuration) is valid
46 * [in]CLK_ClkInitStruct->PLLL.State:
47 * CLK_PLLL_ON (PLLL.Source/Frequency configuration is valid)
48 * CLK_PLLL_OFF (PLLL.Source/Frequency configuration is not valid)
49 * [in]CLK_ClkInitStruct->PLLL.Source:
50 * CLK_PLLLSRC_RCL
51 * CLK_PLLLSRC_XTALL
52 * [in]CLK_ClkInitStruct->PLLL.Frequency:
53 * CLK_PLLL_26_2144MHz
54 * CLK_PLLL_13_1072MHz
55 * CLK_PLLL_6_5536MHz
56 * CLK_PLLL_3_2768MHz
57 * CLK_PLLL_1_6384MHz
58 * CLK_PLLL_0_8192MHz
59 * CLK_PLLL_0_4096MHz
60 * CLK_PLLL_0_2048MHz
61 * CLK_TYPE_PLLH CLK_ClkInitStruct->PLLH(PLLH configuration) is valid
62 * [in]CLK_ClkInitStruct->PLLH.State:
63 * CLK_PLLH_ON (PLLH.Source/Frequency configuration is valid)
64 * CLK_PLLH_OFF (PLLH.Source/Frequency configuration is not valid)
65 * [in]CLK_ClkInitStruct->PLLH.Source:
66 * CLK_PLLHSRC_RCH
67 * CLK_PLLHSRC_XTALH
68 * [in]CLK_ClkInitStruct->PLLH.Frequency:
69 * CLK_PLLH_13_1072MHz
70 * CLK_PLLH_16_384MHz
71 * CLK_PLLH_19_6608MHz
72 * CLK_PLLH_22_9376MHz
73 * CLK_PLLH_26_2144MHz
74 * CLK_PLLH_29_4912MHz
75 * CLK_PLLH_32_768MHz
76 * CLK_PLLH_36_0448MHz
77 * CLK_PLLH_39_3216MHz
78 * CLK_PLLH_42_5984MHz
79 * CLK_PLLH_45_8752MHz
80 * CLK_PLLH_49_152MHz
81 * CLK_TYPE_XTALH CLK_ClkInitStruct->XTALH(XTALH configuration) is valid
82 * [in]CLK_ClkInitStruct->XTALH.State:
83 * CLK_XTALH_ON
84 * CLK_XTALH_OFF
85 * CLK_TYPE_RTCCLK CLK_ClkInitStruct->RTCCLK(RTCCLK configuration) is valid
86 * [in]CLK_ClkInitStruct->RTCCLK.Source:
87 * CLK_RTCCLKSRC_XTALL
88 * CLK_RTCCLKSRC_RCL
89 * [in]CLK_ClkInitStruct->RTCCLK.Divider:
90 * CLK_RTCCLKDIV_1
91 * CLK_RTCCLKDIV_4
92 * CLK_TYPE_HCLK CLK_ClkInitStruct->HCLK(AHB Clock(divider) configuration) is valid
93 * [in]CLK_ClkInitStruct->HCLK.Divider:
94 * 1 ~ 256
95 * CLK_TYPE_PCLK CLK_ClkInitStruct->PCLK(APB Clock(divider) configuration) is valid
96 * [in]CLK_ClkInitStruct->PCLK.Divider:
97 * 1 ~ 256
98 *
99 * @param CLK_ClkInitStruct pointer to an CLK_InitTypeDef structure that
100 * contains the configuration information for the clocks.
101 *
102 * @retval None
103 */
CLK_ClockConfig(CLK_InitTypeDef * CLK_ClkInitStruct)104 void CLK_ClockConfig(CLK_InitTypeDef *CLK_ClkInitStruct)
105 {
106 uint32_t tmp;
107
108 assert_parameters(IS_CLK_TYPE(CLK_ClkInitStruct->ClockType));
109
110 if (CLK_ClkInitStruct->ClockType & CLK_TYPE_AHBSRC)
111 {
112 /* Enable BGP */
113 ANA->REG3 &= ~ANA_REG3_BGPPD;
114 /* Enable 6.5M RC */
115 ANA->REG3 &= ~ANA_REG3_RCHPD;
116
117 /* AHB clock source switch to RCH */
118 MISC2->CLKSEL = 0;
119 }
120
121 ANA->REGA &= ~BIT6;
122
123 /*---------- XTALH configuration ----------*/
124 if ((CLK_ClkInitStruct->ClockType) & CLK_TYPE_XTALH)
125 {
126 assert_parameters(IS_CLK_XTALHSTA(CLK_ClkInitStruct->XTALH.State));
127
128 /* XTALH state configure */
129 ANA->REG3 &= ~ANA_REG3_XOHPDN;
130 ANA->REG3 |= CLK_ClkInitStruct->XTALH.State;
131
132 }
133
134 /*-------------------- PLLL configuration --------------------*/
135 if ((CLK_ClkInitStruct->ClockType) & CLK_TYPE_PLLL)
136 {
137 assert_parameters(IS_CLK_PLLLSRC(CLK_ClkInitStruct->PLLL.Source));
138 assert_parameters(IS_CLK_PLLLSTA(CLK_ClkInitStruct->PLLL.State));
139 assert_parameters(IS_CLK_PLLLFRQ(CLK_ClkInitStruct->PLLL.Frequency));
140
141 /* PLLL state configure */
142 if (CLK_ClkInitStruct->PLLL.State == CLK_PLLL_ON)
143 {
144 /* power up PLLL */
145 ANA->REG3 |= ANA_REG3_PLLLPDN;
146
147 /* Configure PLLL frequency */
148 tmp = ANA->REG9;
149 tmp &= ~ANA_REG9_PLLLSEL;
150 tmp |= CLK_ClkInitStruct->PLLL.Frequency;
151 ANA->REG9 = tmp;
152
153 /* Configure PLLL input clock selection */
154 tmp = PMU->CONTROL;
155 tmp &= ~PMU_CONTROL_PLLL_SEL;
156 tmp |= CLK_ClkInitStruct->PLLL.Source;
157 PMU->CONTROL = tmp;
158 }
159 else
160 {
161 /* power down PLLL */
162 ANA->REG3 &= ~ANA_REG3_PLLLPDN;
163 }
164 }
165
166 /*-------------------- PLLH configuration --------------------*/
167 if ((CLK_ClkInitStruct->ClockType) & CLK_TYPE_PLLH)
168 {
169 assert_parameters(IS_CLK_PLLHSRC(CLK_ClkInitStruct->PLLH.Source));
170 assert_parameters(IS_CLK_PLLHSTA(CLK_ClkInitStruct->PLLH.State));
171 assert_parameters(IS_CLK_PLLHFRQ(CLK_ClkInitStruct->PLLH.Frequency));
172
173 /* PLLH state configure */
174 if (CLK_ClkInitStruct->PLLH.State == CLK_PLLH_ON)
175 {
176 /* Power up PLLH */
177 ANA->REG3 |= ANA_REG3_PLLHPDN;
178
179 /* Configure PLLH frequency */
180 tmp = ANA->REG9;
181 tmp &= ~ANA_REG9_PLLHSEL;
182 tmp |= CLK_ClkInitStruct->PLLH.Frequency;
183 ANA->REG9 = tmp;
184
185 /* Clock input source, XTALH, XOH power on*/
186 if (CLK_ClkInitStruct->PLLH.Source == CLK_PLLHSRC_XTALH)
187 {
188 ANA->REG3 |= ANA_REG3_XOHPDN;
189 }
190
191 /* Configure PLLH input clock selection */
192 tmp = PMU->CONTROL;
193 tmp &= ~PMU_CONTROL_PLLH_SEL;
194 tmp |= CLK_ClkInitStruct->PLLH.Source;
195 PMU->CONTROL = tmp;
196 }
197 else
198 {
199 /* Power down PLLH */
200 ANA->REG3 &= ~ANA_REG3_PLLHPDN;
201 }
202 }
203
204 /*---------- RTCCLK configuration ----------*/
205 if ((CLK_ClkInitStruct->ClockType) & CLK_TYPE_RTCCLK)
206 {
207 assert_parameters(IS_CLK_RTCSRC(CLK_ClkInitStruct->RTCCLK.Source));
208 assert_parameters(IS_CLK_RTCDIV(CLK_ClkInitStruct->RTCCLK.Divider));
209
210 /* RTCCLK source(optional) */
211 tmp = PMU->CONTROL;
212 tmp &= ~PMU_CONTROL_RTCCLK_SEL;
213 tmp |= CLK_ClkInitStruct->RTCCLK.Source;
214 PMU->CONTROL = tmp;
215
216 /*----- RTCCLK Divider -----*/
217 RTC_PrescalerConfig(CLK_ClkInitStruct->RTCCLK.Divider);
218 }
219
220 /*---------- AHB clock source configuration ----------*/
221 if ((CLK_ClkInitStruct->ClockType) & CLK_TYPE_AHBSRC)
222 {
223 assert_parameters(IS_CLK_AHBSRC(CLK_ClkInitStruct->AHBSource));
224
225 /* clock source: 6.5M RC */
226 if (CLK_ClkInitStruct->AHBSource == CLK_AHBSEL_6_5MRC)
227 {
228 /* clock source configuration */
229 MISC2->CLKSEL = CLK_ClkInitStruct->AHBSource;
230 }
231
232 /* clock source: 6_5MXTAL */
233 else if (CLK_ClkInitStruct->AHBSource == CLK_AHBSEL_6_5MXTAL)
234 {
235 /* Power up 6.5M xtal */
236 ANA->REG3 |= ANA_REG3_XOHPDN;
237 /* clock source configuration */
238 MISC2->CLKSEL = CLK_ClkInitStruct->AHBSource;
239 }
240
241 /* clock source: PLLH */
242 else if (CLK_ClkInitStruct->AHBSource == CLK_AHBSEL_HSPLL)
243 {
244 /* Power up PLLH */
245 ANA->REG3 |= ANA_REG3_PLLHPDN;
246 /* while loop until PLLL is lock */
247 while (!(ANA->CMPOUT & ANA_CMPOUT_LOCKH))
248 {
249 }
250 /* clock source configuration */
251 MISC2->CLKSEL = CLK_ClkInitStruct->AHBSource;
252 }
253
254 /* clock source: PLLL */
255 else if (CLK_ClkInitStruct->AHBSource == CLK_AHBSEL_LSPLL)
256 {
257 /* Power up PLLL */
258 ANA->REG3 |= ANA_REG3_PLLLPDN;
259 /* while loop until PLLL is lock */
260 while (!(ANA->CMPOUT & ANA_CMPOUT_LOCKL))
261 {
262 }
263 /* clock source configuration */
264 MISC2->CLKSEL = CLK_ClkInitStruct->AHBSource;
265 }
266 /* clock source: RTCCLK */
267 else
268 {
269 /* clock source configuration */
270 MISC2->CLKSEL = CLK_ClkInitStruct->AHBSource;
271 }
272 }
273
274 /*---------- HCLK configuration ----------*/
275 if ((CLK_ClkInitStruct->ClockType) & CLK_TYPE_HCLK)
276 {
277 assert_parameters(IS_CLK_HCLKDIV(CLK_ClkInitStruct->HCLK.Divider));
278
279 MISC2->CLKDIVH = (CLK_ClkInitStruct->HCLK.Divider) - 1;
280 }
281
282 /*---------- PCLK configuration ----------*/
283 if ((CLK_ClkInitStruct->ClockType) & CLK_TYPE_PCLK)
284 {
285 assert_parameters(IS_CLK_PCLKDIV(CLK_ClkInitStruct->PCLK.Divider));
286
287 MISC2->CLKDIVP = (CLK_ClkInitStruct->PCLK.Divider) - 1;
288 }
289 }
290
291 /**
292 * @brief Enables or disables AHB Periphral clock.
293 * @param Periphral: can use the '|' operator
294 CLK_AHBPERIPHRAL_DMA
295 CLK_AHBPERIPHRAL_GPIO
296 CLK_AHBPERIPHRAL_LCD
297 CLK_AHBPERIPHRAL_CRYPT
298 NewState:
299 ENABLE
300 DISABLE
301 * @retval None.
302 */
CLK_AHBPeriphralCmd(uint32_t Periphral,uint32_t NewState)303 void CLK_AHBPeriphralCmd(uint32_t Periphral, uint32_t NewState)
304 {
305 /* Check parameters */
306 assert_parameters(IS_CLK_AHBPERIPHRAL(Periphral));
307 assert_parameters(IS_FUNCTIONAL_STATE(NewState));
308
309 if (NewState == ENABLE)
310 {
311 MISC2->HCLKEN |= Periphral;
312 }
313 else
314 {
315 MISC2->HCLKEN &= ~Periphral;
316 }
317 }
318
319 /**
320 * @brief Enables or disables APB Periphral clock.
321 * @param Periphral: can use the '|' operator
322 CLK_APBPERIPHRAL_DMA
323 CLK_APBPERIPHRAL_I2C
324 CLK_APBPERIPHRAL_SPI1
325 CLK_APBPERIPHRAL_SPI2
326 CLK_APBPERIPHRAL_UART0
327 CLK_APBPERIPHRAL_UART1
328 CLK_APBPERIPHRAL_UART2
329 CLK_APBPERIPHRAL_UART3
330 CLK_APBPERIPHRAL_UART4
331 CLK_APBPERIPHRAL_UART5
332 CLK_APBPERIPHRAL_ISO78160
333 CLK_APBPERIPHRAL_ISO78161
334 CLK_APBPERIPHRAL_TIMER
335 CLK_APBPERIPHRAL_MISC
336 CLK_APBPERIPHRAL_MISC2
337 CLK_APBPERIPHRAL_PMU
338 CLK_APBPERIPHRAL_RTC
339 CLK_APBPERIPHRAL_ANA
340 CLK_APBPERIPHRAL_U32K0
341 CLK_APBPERIPHRAL_U32K1
342 NewState:
343 ENABLE
344 DISABLE
345 * @retval None.
346 */
CLK_APBPeriphralCmd(uint32_t Periphral,uint32_t NewState)347 void CLK_APBPeriphralCmd(uint32_t Periphral, uint32_t NewState)
348 {
349 /* Check parameters */
350 assert_parameters(IS_CLK_APBPERIPHRAL(Periphral));
351 assert_parameters(IS_FUNCTIONAL_STATE(NewState));
352
353 if (NewState == ENABLE)
354 {
355 MISC2->PCLKEN |= Periphral;
356 }
357 else
358 {
359 MISC2->PCLKEN &= ~Periphral;
360 }
361 }
362
363 /**
364 * @brief Returns the HCLK frequency
365 * @param None
366 * @retval HCLK frequency
367 */
CLK_GetHCLKFreq(void)368 uint32_t CLK_GetHCLKFreq(void)
369 {
370 uint32_t ahb_clksrc;
371 uint32_t ahb_div;
372 uint32_t pllh_frq;
373 uint32_t plll_frq;
374 uint32_t rtcclk_div;
375 uint32_t hclk;
376
377 /* Get current AHB clock source */
378 ahb_clksrc = MISC2->CLKSEL & MISC2_CLKSEL_CLKSEL;
379 /* Get AHB clock divider */
380 ahb_div = (MISC2->CLKDIVH & MISC2_CLKDIVH_CLKDIVH) + 1;
381
382 switch (ahb_clksrc)
383 {
384 /* AHB Clock source : 6.5M RC */
385 case MISC2_CLKSEL_CLKSEL_RCOH:
386 hclk = 6553600 / ahb_div;
387 break;
388
389 /* AHB Clock source : 6.5M XTAL */
390 case MISC2_CLKSEL_CLKSEL_XOH:
391 hclk = 6553600 / ahb_div;
392 break;
393
394 /* AHB Clock source : PLLH */
395 case MISC2_CLKSEL_CLKSEL_PLLH:
396 /* Get PLLH Frequency */
397 pllh_frq = ANA->REG9 & ANA_REG9_PLLHSEL;
398 switch (pllh_frq)
399 {
400 case ANA_REG9_PLLHSEL_X2:
401 hclk = 13107200 / ahb_div;
402 break;
403
404 case ANA_REG9_PLLHSEL_X2_5:
405 hclk = 16384000 / ahb_div;
406 break;
407
408 case ANA_REG9_PLLHSEL_X3:
409 hclk = 19660800 / ahb_div;
410 break;
411
412 case ANA_REG9_PLLHSEL_X3_5:
413 hclk = 22937600 / ahb_div;
414 break;
415
416 case ANA_REG9_PLLHSEL_X4:
417 hclk = 26214400 / ahb_div;
418 break;
419
420 case ANA_REG9_PLLHSEL_X4_5:
421 hclk = 29491200 / ahb_div;
422 break;
423
424 case ANA_REG9_PLLHSEL_X5:
425 hclk = 32768000 / ahb_div;
426 break;
427
428 case ANA_REG9_PLLHSEL_X5_5:
429 hclk = 36044800 / ahb_div;
430 break;
431
432 case ANA_REG9_PLLHSEL_X6:
433 hclk = 39321600 / ahb_div;
434 break;
435
436 case ANA_REG9_PLLHSEL_X6_5:
437 hclk = 42598400 / ahb_div;
438 break;
439
440 case ANA_REG9_PLLHSEL_X7:
441 hclk = 45875200 / ahb_div;
442 break;
443
444 case ANA_REG9_PLLHSEL_X7_5:
445 hclk = 49152000 / ahb_div;
446 break;
447
448 default:
449 hclk = 0;
450 break;
451 }
452 break;
453
454 /* AHB Clock source : RTCCLK */
455 case MISC2_CLKSEL_CLKSEL_RTCCLK:
456 /* Get current RTC clock divider */
457 rtcclk_div = RTC->PSCA & RTC_PSCA_PSCA;
458 if (rtcclk_div == RTC_PSCA_PSCA_0)
459 {
460 hclk = 32768 / ahb_div;
461 }
462 else if (rtcclk_div == RTC_PSCA_PSCA_1)
463 {
464 hclk = 8192 / ahb_div;
465 }
466 else
467 {
468 hclk = 0;
469 }
470 break;
471
472 /* AHB Clock source : PLLL */
473 case MISC2_CLKSEL_CLKSEL_PLLL:
474 /* Get PLLL Frequency */
475 plll_frq = ANA->REG9 & ANA_REG9_PLLLSEL;
476 switch (plll_frq)
477 {
478 case ANA_REG9_PLLLSEL_26M:
479 hclk = 26214400 / ahb_div;
480 break;
481
482 case ANA_REG9_PLLLSEL_13M:
483 hclk = 13107200 / ahb_div;
484 break;
485
486 case ANA_REG9_PLLLSEL_6_5M:
487 hclk = 6553600 / ahb_div;
488 break;
489
490 case ANA_REG9_PLLLSEL_3_2M:
491 hclk = 3276800 / ahb_div;
492 break;
493
494 case ANA_REG9_PLLLSEL_1_6M:
495 hclk = 1638400 / ahb_div;
496 break;
497
498 case ANA_REG9_PLLLSEL_800K:
499 hclk = 819200 / ahb_div;
500 break;
501
502 case ANA_REG9_PLLLSEL_400K:
503 hclk = 409600 / ahb_div;
504 break;
505
506 case ANA_REG9_PLLLSEL_200K:
507 hclk = 204800 / ahb_div;
508 break;
509
510 default:
511 hclk = 0;
512 break;
513 }
514 break;
515
516 default:
517 hclk = 0;
518 break;
519 }
520
521 return (hclk);
522 }
523
524 /**
525 * @brief Returns the PLLL frequency
526 * @param None
527 * @retval PLLL frequency
528 */
CLK_GetPLLLFreq(void)529 uint32_t CLK_GetPLLLFreq(void)
530 {
531 uint32_t plll_frq;
532
533 if (!(ANA->REG3 & ANA_REG3_PLLLPDN))
534 return 0;
535 /* Get PLLL Frequency */
536 plll_frq = ANA->REG9 & ANA_REG9_PLLLSEL;
537 switch (plll_frq)
538 {
539 case ANA_REG9_PLLLSEL_26M:
540 plll_frq = 26214400;
541 break;
542
543 case ANA_REG9_PLLLSEL_13M:
544 plll_frq = 13107200;
545 break;
546
547 case ANA_REG9_PLLLSEL_6_5M:
548 plll_frq = 6553600;
549 break;
550
551 case ANA_REG9_PLLLSEL_3_2M:
552 plll_frq = 3276800;
553 break;
554
555 case ANA_REG9_PLLLSEL_1_6M:
556 plll_frq = 1638400;
557 break;
558
559 case ANA_REG9_PLLLSEL_800K:
560 plll_frq = 819200;
561 break;
562
563 case ANA_REG9_PLLLSEL_400K:
564 plll_frq = 409600;
565 break;
566
567 case ANA_REG9_PLLLSEL_200K:
568 plll_frq = 204800;
569 break;
570
571 default:
572 plll_frq = 0;
573 break;
574 }
575
576 return (plll_frq);
577 }
578
579 /**
580 * @brief Returns the PCLK frequency
581 * @param None
582 * @retval PCLK frequency
583 */
CLK_GetPCLKFreq(void)584 uint32_t CLK_GetPCLKFreq(void)
585 {
586 return ((CLK_GetHCLKFreq()) / ((MISC2->CLKDIVP & MISC2_CLKDIVP_CLKDIVP) + 1));
587 }
588
589 /**
590 * @brief Get the CLK_ClkInitStruct according to the internal
591 * Clock configuration registers.
592 *
593 * @param CLK_ClkInitStruct pointer to an CLK_ClkInitStruct structure that
594 * contains the current clock configuration.
595 *
596 * @retval None
597 */
CLK_GetClockConfig(CLK_InitTypeDef * CLK_ClkInitStruct)598 void CLK_GetClockConfig(CLK_InitTypeDef *CLK_ClkInitStruct)
599 {
600 /* Set all possible values for the Clock type parameter --------------------*/
601 CLK_ClkInitStruct->ClockType = CLK_TYPE_ALL;
602
603 /* Get AHB clock source ----------------------------------------------------*/
604 CLK_ClkInitStruct->AHBSource = (uint32_t)(MISC2->CLKSEL & MISC2_CLKSEL_CLKSEL);
605 /* Get PLLL clock configration ---------------------------------------------*/
606 CLK_ClkInitStruct->PLLL.Source = (uint32_t)(PMU->CONTROL & PMU_CONTROL_PLLL_SEL);
607 CLK_ClkInitStruct->PLLL.Frequency = (uint32_t)(ANA->REG9 & ANA_REG9_PLLLSEL);
608 CLK_ClkInitStruct->PLLL.State = (uint32_t)(ANA->REG3 & ANA_REG3_PLLLPDN);
609 /* Get PLLH clock configuration --------------------------------------------*/
610 CLK_ClkInitStruct->PLLH.Source = (uint32_t)(PMU->CONTROL & PMU_CONTROL_PLLH_SEL);
611 CLK_ClkInitStruct->PLLH.Frequency = (uint32_t)(ANA->REG9 & ANA_REG9_PLLHSEL);
612 CLK_ClkInitStruct->PLLH.State = (uint32_t)(ANA->REG3 & ANA_REG3_PLLHPDN);
613 /* Get XTALH configuration -------------------------------------------------*/
614 CLK_ClkInitStruct->XTALH.State = (uint32_t)(ANA->REG3 & ANA_REG3_XOHPDN);
615 /* Get HCLK(Divider) configuration -----------------------------------------*/
616 CLK_ClkInitStruct->HCLK.Divider = (uint32_t)((MISC2->CLKDIVH & MISC2_CLKDIVH_CLKDIVH) + 1);
617 /* Get PCLK((Divider) configuration ----------------------------------------*/
618 CLK_ClkInitStruct->PCLK.Divider = (uint32_t)((MISC2->CLKDIVP & MISC2_CLKDIVP_CLKDIVP) + 1);
619 }
620
621 /**
622 * @brief Gets current external 6.5M crystal status.
623 *
624 * @param None
625 *
626 * @retval 6.5M crystal status
627 * 0: 6.5536M crystal is absent.
628 * 1: 6.5536M crystal is present.
629 */
CLK_GetXTALHStatus(void)630 uint8_t CLK_GetXTALHStatus(void)
631 {
632 if (PMU->STS & PMU_STS_EXIST_6M)
633 return (1);
634 else
635 return (0);
636 }
637
638 /**
639 * @brief Gets current external 32K crystal status.
640 *
641 * @param None
642 *
643 * @retval 32K crystal status
644 * 0: 32K crystal is absent
645 * 1: 32K crystal is present.
646 */
CLK_GetXTALLStatus(void)647 uint8_t CLK_GetXTALLStatus(void)
648 {
649 if (PMU->STS & PMU_STS_EXIST_32K)
650 return (1);
651 else
652 return (0);
653 }
654
655 /**
656 * @brief Gets PLL lock status.
657 * @param PLLStatus:
658 * CLK_STATUS_LOCKL
659 * CLK_STATUS_LOCKH
660 * @retval PLL lock status
661 * 0 PLL is not locked.
662 * 1 PLL is locked.
663 */
CLK_GetPLLLockStatus(uint32_t PLLStatus)664 uint8_t CLK_GetPLLLockStatus(uint32_t PLLStatus)
665 {
666 /* Check parameters */
667 assert_parameters(IS_CLK_PLLLOCK(PLLStatus));
668
669 if (ANA->CMPOUT & PLLStatus)
670 return 1;
671 else
672 return 0;
673 }
674
675 /*********************************** END OF FILE ******************************/
676