1 /**
2 ******************************************************************************
3 * @file lib_dma.c
4 * @author Application Team
5 * @version V1.1.0
6 * @date 2019-10-28
7 * @brief DMA library.
8 ******************************************************************************
9 * @attention
10 *
11 ******************************************************************************
12 */
13 #include "lib_dma.h"
14
15 //registers default reset values
16 #define DMA_CxCTL_RSTValue (0UL)
17 #define DMA_CxSRC_RSTValue (0UL)
18 #define DMA_CxDST_RSTValue (0UL)
19 #define DMA_AESCTL_RSTValue (0UL)
20 #define DMA_AESKEY_RSTValue (0UL)
21
22 /**
23 * @brief Initializes the DMA channel peripheral registers to their default reset values.
24 * @param Channel: DMA_CHANNEL_0~DMA_CHANNEL_3
25 * @retval None
26 */
DMA_DeInit(uint32_t Channel)27 void DMA_DeInit(uint32_t Channel)
28 {
29 __IO uint32_t *addr;
30
31 /* Check parameters */
32 assert_parameters(IS_DMA_CHANNEL(Channel));
33
34 /* channel x disable, clear stop */
35 addr = &DMA->C0CTL + Channel*4;
36 *addr &= ~(DMA_CCTL_EN | DMA_CCTL_STOP);
37
38 /* interrupt disable */
39 DMA->IE &= ~((1<<(Channel))\
40 |(1<<(Channel+4))\
41 |(1<<(Channel+8)));
42
43 /* interrupt state clear */
44 DMA->STS = (1<<(Channel+4))\
45 |(1<<(Channel+8))\
46 |(1<<(Channel+12));
47
48 /* DMA_CxCTL */
49 addr = &DMA->C0CTL + Channel*4;
50 *addr = DMA_CxCTL_RSTValue;
51
52 /* DMA_CxSRC */
53 addr = &DMA->C0SRC + Channel*4;
54 *addr = DMA_CxSRC_RSTValue;
55
56 /* DMA_CxDST */
57 addr = &DMA->C0DST + Channel*4;
58 *addr = DMA_CxDST_RSTValue;
59 }
60 /**
61 * @brief Fills each DMA_InitType member with its default value.
62 * @param InitStruct: pointer to an DMA_InitType structure which will be initialized.
63 * @retval None
64 */
DMA_StructInit(DMA_InitType * InitStruct)65 void DMA_StructInit(DMA_InitType *InitStruct)
66 {
67 /*-------------- Reset DMA init structure parameters values ---------------*/
68 /* Initialize the DestAddr member */
69 InitStruct->DestAddr = 0;
70 /* Initialize the SrcAddr member */
71 InitStruct->SrcAddr = 0;
72 /* Initialize the FrameLen member */
73 InitStruct->FrameLen = 0;
74 /* Initialize the PackLen member */
75 InitStruct->PackLen = 0;
76 /* Initialize the ContMode member */
77 InitStruct->ContMode = DMA_CONTMODE_DISABLE;
78 /* Initialize the TransMode member */
79 InitStruct->TransMode = DMA_TRANSMODE_SINGLE;
80 /* Initialize the ReqSrc member */
81 InitStruct->ReqSrc = DMA_REQSRC_SOFT;
82 /* Initialize the DestAddrMode member */
83 InitStruct->DestAddrMode = DMA_DESTADDRMODE_FIX;
84 /* Initialize the SrcAddrMode member */
85 InitStruct->SrcAddrMode = DMA_SRCADDRMODE_FIX;
86 /* Initialize the TransSize member */
87 InitStruct->TransSize = DMA_TRANSSIZE_BYTE;
88 }
89 /**
90 * @brief Initializes DMA channel.
91 * @param InitStruct: DMA configuration.
92 DestAddr : destination address
93 SrcAddr : source address
94 FrameLen : Frame length (Ranges 0~255, actual length FrameLen+1)
95 PackLen : Package length (Ranges 0~255, actual length PackLen+1)
96 ContMode:
97 DMA_CONTMODE_ENABLE
98 DMA_CONTMODE_DISABLE
99 TransMode:
100 DMA_TRANSMODE_SINGLE
101 DMA_TRANSMODE_PACK
102 ReqSrc:
103 DMA_REQSRC_SOFT
104 DMA_REQSRC_ADC
105 DMA_REQSRC_UART0TX
106 DMA_REQSRC_UART0RX
107 DMA_REQSRC_UART1TX
108 DMA_REQSRC_UART1RX
109 DMA_REQSRC_UART2TX
110 DMA_REQSRC_UART2RX
111 DMA_REQSRC_UART3TX
112 DMA_REQSRC_UART3RX
113 DMA_REQSRC_UART4TX
114 DMA_REQSRC_UART4RX
115 DMA_REQSRC_UART5TX
116 DMA_REQSRC_UART5RX
117 DMA_REQSRC_ISO78160TX
118 DMA_REQSRC_ISO78160RX
119 DMA_REQSRC_ISO78161TX
120 DMA_REQSRC_ISO78161RX
121 DMA_REQSRC_TIMER0
122 DMA_REQSRC_TIMER1
123 DMA_REQSRC_TIMER2
124 DMA_REQSRC_TIMER3
125 DMA_REQSRC_SPI1TX
126 DMA_REQSRC_SPI1RX
127 DMA_REQSRC_U32K0
128 DMA_REQSRC_U32K1
129 DMA_REQSRC_CMP1
130 DMA_REQSRC_CMP2
131 DMA_REQSRC_SPI2TX
132 DMA_REQSRC_SPI2RX
133 DMA_REQSRC_SPI3TX
134 DMA_REQSRC_SPI3RX
135 DestAddrMode:
136 DMA_DESTADDRMODE_FIX
137 DMA_DESTADDRMODE_PEND
138 DMA_DESTADDRMODE_FEND
139 SrcAddrMode:
140 DMA_SRCADDRMODE_FIX
141 DMA_SRCADDRMODE_PEND
142 DMA_SRCADDRMODE_FEND
143 TransSize:
144 DMA_TRANSSIZE_BYTE
145 DMA_TRANSSIZE_HWORD
146 DMA_TRANSSIZE_WORD
147 Channel:
148 DMA_CHANNEL_0
149 DMA_CHANNEL_1
150 DMA_CHANNEL_2
151 DMA_CHANNEL_3
152 * @retval None
153 */
DMA_Init(DMA_InitType * InitStruct,uint32_t Channel)154 void DMA_Init(DMA_InitType *InitStruct, uint32_t Channel)
155 {
156 uint32_t tmp;
157 __IO uint32_t *addr;
158
159 /* Check parameters */
160 assert_parameters(IS_DMA_CHANNEL(Channel));
161 assert_parameters(IS_DMA_CONTMOD(InitStruct->ContMode));
162 assert_parameters(IS_DMA_TRANSMOD(InitStruct->TransMode));
163 assert_parameters(IS_DMA_REQSRC(InitStruct->ReqSrc));
164 assert_parameters(IS_DMA_DESTADDRMOD(InitStruct->DestAddrMode));
165 assert_parameters(IS_DMA_SRCADDRMOD(InitStruct->SrcAddrMode));
166 assert_parameters(IS_DMA_TRANSSIZE(InitStruct->TransSize));
167
168 if (InitStruct->TransSize == DMA_TRANSSIZE_HWORD)
169 {
170 assert_parameters(IS_DMA_ALIGNEDADDR_HWORD(InitStruct->SrcAddr));
171 assert_parameters(IS_DMA_ALIGNEDADDR_HWORD(InitStruct->DestAddr));
172 }
173 if (InitStruct->TransSize == DMA_TRANSSIZE_WORD)
174 {
175 assert_parameters(IS_DMA_ALIGNEDADDR_WORD(InitStruct->SrcAddr));
176 assert_parameters(IS_DMA_ALIGNEDADDR_WORD(InitStruct->DestAddr));
177 }
178
179 addr = &DMA->C0DST + Channel*4;
180 *addr = InitStruct->DestAddr;
181
182 addr = &DMA->C0SRC + Channel*4;
183 *addr = InitStruct->SrcAddr;
184
185 addr = &DMA->C0CTL + Channel*4;
186
187 tmp = *addr;
188 tmp &= ~(DMA_CCTL_FLEN\
189 |DMA_CCTL_PLEN\
190 |DMA_CCTL_CONT\
191 |DMA_CCTL_TMODE\
192 |DMA_CCTL_DMASEL\
193 |DMA_CCTL_DMODE\
194 |DMA_CCTL_SMODE\
195 |DMA_CCTL_SIZE);
196 tmp |= ((InitStruct->FrameLen<<DMA_CCTL_FLEN_Pos)\
197 |(InitStruct->PackLen<<DMA_CCTL_PLEN_Pos)\
198 |(InitStruct->ContMode)\
199 |(InitStruct->TransMode)\
200 |(InitStruct->ReqSrc)\
201 |(InitStruct->DestAddrMode)\
202 |(InitStruct->SrcAddrMode)\
203 |(InitStruct->TransSize));
204 *addr = tmp;
205 }
206
207 /**
208 * @brief Initializes the DMA AES channel3 registers to their default reset values.
209 * @param None
210 * @retval None
211 */
DMA_ASEDeInit(void)212 void DMA_ASEDeInit(void)
213 {
214 DMA->AESCTL = DMA_AESCTL_RSTValue;
215 DMA->AESKEY[0] = DMA_AESKEY_RSTValue;
216 DMA->AESKEY[1] = DMA_AESKEY_RSTValue;
217 DMA->AESKEY[2] = DMA_AESKEY_RSTValue;
218 DMA->AESKEY[3] = DMA_AESKEY_RSTValue;
219 DMA->AESKEY[4] = DMA_AESKEY_RSTValue;
220 DMA->AESKEY[5] = DMA_AESKEY_RSTValue;
221 DMA->AESKEY[6] = DMA_AESKEY_RSTValue;
222 DMA->AESKEY[7] = DMA_AESKEY_RSTValue;
223 }
224
225 /**
226 * @brief Initializes AES.
227 * @param InitStruct: AES configuration.
228 Mode:
229 DMA_AESMODE_128
230 DMA_AESMODE_192
231 DMA_AESMODE_256
232 Direction:
233 DMA_AESDIRECTION_ENCODE
234 DMA_AESDIRECTION_DECODE
235 KeyStr: the pointer to DMA_AESKEYx register
236 * @retval None
237 */
DMA_AESInit(DMA_AESInitType * InitStruct)238 void DMA_AESInit(DMA_AESInitType *InitStruct)
239 {
240 uint32_t tmp;
241
242 /* Check parameters */
243 assert_parameters(IS_DMA_AESMOD(InitStruct->Mode));
244 assert_parameters(IS_DMA_AESDIR(InitStruct->Direction));
245
246 tmp = DMA->AESCTL;
247 tmp &= ~(DMA_AESCTL_MODE\
248 |DMA_AESCTL_ENC);
249 tmp |= (InitStruct->Mode\
250 |InitStruct->Direction);
251 DMA->AESCTL = tmp;
252 DMA->AESKEY[0] = InitStruct->KeyStr[0];
253 DMA->AESKEY[1] = InitStruct->KeyStr[1];
254 DMA->AESKEY[2] = InitStruct->KeyStr[2];
255 DMA->AESKEY[3] = InitStruct->KeyStr[3];
256
257 if ((InitStruct->Mode == DMA_AESMODE_192) ||\
258 (InitStruct->Mode == DMA_AESMODE_256))
259 {
260 DMA->AESKEY[4] = InitStruct->KeyStr[4];
261 DMA->AESKEY[5] = InitStruct->KeyStr[5];
262 }
263 if (InitStruct->Mode == DMA_AESMODE_256)
264 {
265 DMA->AESKEY[6] = InitStruct->KeyStr[6];
266 DMA->AESKEY[7] = InitStruct->KeyStr[7];
267 }
268 }
269
270 /**
271 * @brief Enables or disables DMA interrupt.
272 * @param INTMask: can use the '|' operator
273 DMA_INT_C3DA
274 DMA_INT_C2DA
275 DMA_INT_C1DA
276 DMA_INT_C0DA
277 DMA_INT_C3FE
278 DMA_INT_C2FE
279 DMA_INT_C1FE
280 DMA_INT_C0FE
281 DMA_INT_C3PE
282 DMA_INT_C2PE
283 DMA_INT_C1PE
284 DMA_INT_C0PE
285 NewState:
286 ENABLE
287 DISABLE
288 * @retval None
289 */
DMA_INTConfig(uint32_t INTMask,uint32_t NewState)290 void DMA_INTConfig(uint32_t INTMask, uint32_t NewState)
291 {
292 /* Check parameters */
293 assert_parameters(IS_DMA_INT(INTMask));
294 assert_parameters(IS_FUNCTIONAL_STATE(NewState));
295
296 if (NewState == ENABLE)
297 DMA->IE |= INTMask;
298 else
299 DMA->IE &= ~INTMask;
300 }
301
302 /**
303 * @brief Gets DMA interrupt status.
304 * @param INTMask:
305 DMA_INTSTS_C3DA
306 DMA_INTSTS_C2DA
307 DMA_INTSTS_C1DA
308 DMA_INTSTS_C0DA
309 DMA_INTSTS_C3FE
310 DMA_INTSTS_C2FE
311 DMA_INTSTS_C1FE
312 DMA_INTSTS_C0FE
313 DMA_INTSTS_C3PE
314 DMA_INTSTS_C2PE
315 DMA_INTSTS_C1PE
316 DMA_INTSTS_C0PE
317 DMA_INTSTS_C3BUSY
318 DMA_INTSTS_C2BUSY
319 DMA_INTSTS_C1BUSY
320 DMA_INTSTS_C0BUSY
321 * @retval interrupt status.
322 */
DMA_GetINTStatus(uint32_t INTMask)323 uint8_t DMA_GetINTStatus(uint32_t INTMask)
324 {
325 /* Check parameters */
326 assert_parameters(IS_DMA_INTFLAGR(INTMask));
327
328 if (DMA->STS&INTMask)
329 return 1;
330 else
331 return 0;
332 }
333
334 /**
335 * @brief Clears DMA interrupt status.
336 * @param INTMask: can use the '|' operator
337 DMA_INTSTS_C3DA
338 DMA_INTSTS_C2DA
339 DMA_INTSTS_C1DA
340 DMA_INTSTS_C0DA
341 DMA_INTSTS_C3FE
342 DMA_INTSTS_C2FE
343 DMA_INTSTS_C1FE
344 DMA_INTSTS_C0FE
345 DMA_INTSTS_C3PE
346 DMA_INTSTS_C2PE
347 DMA_INTSTS_C1PE
348 DMA_INTSTS_C0PE
349 * @retval None
350 */
DMA_ClearINTStatus(uint32_t INTMask)351 void DMA_ClearINTStatus(uint32_t INTMask)
352 {
353 /* Check parameters */
354 assert_parameters(IS_DMA_INTFLAGC(INTMask));
355
356 DMA->STS = INTMask;
357 }
358
359 /**
360 * @brief Enables or disables DMA channel.
361 * @param Channel:
362 DMA_CHANNEL_0
363 DMA_CHANNEL_1
364 DMA_CHANNEL_2
365 DMA_CHANNEL_3
366 NewState:
367 ENABLE
368 DISABLE
369 * @retval None
370 */
DMA_Cmd(uint32_t Channel,uint32_t NewState)371 void DMA_Cmd(uint32_t Channel, uint32_t NewState)
372 {
373 __IO uint32_t *addr;
374
375 /* Check parameters */
376 assert_parameters(IS_DMA_CHANNEL(Channel));
377 assert_parameters(IS_FUNCTIONAL_STATE(NewState));
378
379 addr = &DMA->C0CTL + Channel*4;
380
381 if (NewState == ENABLE)
382 *addr |= DMA_CCTL_EN;
383 else
384 *addr &= ~DMA_CCTL_EN;
385 }
386
387 /**
388 * @brief Enables or disables AES encrypt/decrypt function of DMA channel3.
389 * @param NewState:
390 ENABLE
391 DISABLE
392 * @retval None
393 */
DMA_AESCmd(uint32_t NewState)394 void DMA_AESCmd(uint32_t NewState)
395 {
396 /* Check parameters */
397 assert_parameters(IS_FUNCTIONAL_STATE(NewState));
398
399 if (NewState == ENABLE)
400 DMA->C3CTL |= DMA_CCTL_AESEN;
401 else
402 DMA->C3CTL &= ~DMA_CCTL_AESEN;
403 }
404
405 /**
406 * @brief Stops DMA transmit.
407 * @param Channel:
408 DMA_CHANNEL_0
409 DMA_CHANNEL_1
410 DMA_CHANNEL_2
411 DMA_CHANNEL_3
412 NewState:
413 ENABLE
414 DISABLE
415 * @retval None
416 */
DMA_StopTransmit(uint32_t Channel,uint32_t NewState)417 void DMA_StopTransmit(uint32_t Channel, uint32_t NewState)
418 {
419 __IO uint32_t *addr;
420
421 /* Check parameters */
422 assert_parameters(IS_DMA_CHANNEL(Channel));
423 assert_parameters(IS_FUNCTIONAL_STATE(NewState));
424
425 addr = &DMA->C0CTL + Channel*4;
426
427 if (NewState == ENABLE)
428 *addr |= DMA_CCTL_STOP;
429 else
430 *addr &= ~DMA_CCTL_STOP;
431 }
432
433 /**
434 * @brief Gets current frame transferred length.
435 * @param Channel:
436 DMA_CHANNEL_0
437 DMA_CHANNEL_1
438 DMA_CHANNEL_2
439 DMA_CHANNEL_3
440 * @retval Current frame transferred length.
441 */
DMA_GetFrameLenTransferred(uint32_t Channel)442 uint8_t DMA_GetFrameLenTransferred(uint32_t Channel)
443 {
444 __IO uint32_t *addr;
445
446 /* Check parameters */
447 assert_parameters(IS_DMA_CHANNEL(Channel));
448
449 addr = &DMA->C0LEN + Channel*4;
450 return ((*addr&0xFF00)>>8);
451 }
452
453 /**
454 * @brief Gets current package transferred length.
455 * @param Channel:
456 DMA_CHANNEL_0
457 DMA_CHANNEL_1
458 DMA_CHANNEL_2
459 DMA_CHANNEL_3
460 * @retval Current package transferred length.
461 */
DMA_GetPackLenTransferred(uint32_t Channel)462 uint8_t DMA_GetPackLenTransferred(uint32_t Channel)
463 {
464 __IO uint32_t *addr;
465
466 /* Check parameters */
467 assert_parameters(IS_DMA_CHANNEL(Channel));
468
469 addr = &DMA->C0LEN + Channel*4;
470 return (*addr&0xFF);
471 }
472
473 /*********************************** END OF FILE ******************************/
474