1 /** 2 ****************************************************************************** 3 * @file lib_misc.c 4 * @author Application Team 5 * @version V1.1.0 6 * @date 2019-10-28 7 * @brief MISC library. 8 ****************************************************************************** 9 * @attention 10 * 11 ****************************************************************************** 12 */ 13 #include "lib_misc.h" 14 15 /** 16 * @brief Gets MISC flag status. 17 * @param FlagMask: 18 MISC_FLAG_LOCKUP 19 MISC_FLAG_PIAC 20 MISC_FLAG_HIAC 21 MISC_FLAG_PERR 22 * @retval Flag status. 23 */ MISC_GetFlag(uint32_t FlagMask)24uint8_t MISC_GetFlag(uint32_t FlagMask) 25 { 26 /* Check parameters */ 27 assert_parameters(IS_MISC_FLAGR(FlagMask)); 28 29 if (MISC1->SRAMINT&FlagMask) 30 { 31 return 1; 32 } 33 else 34 { 35 return 0; 36 } 37 } 38 39 /** 40 * @brief Clears MISC flag status. 41 * @param FlagMask: can use the '|' operator 42 MISC_FLAG_LOCKUP 43 MISC_FLAG_PIAC 44 MISC_FLAG_HIAC 45 MISC_FLAG_PERR 46 * @retval None 47 */ MISC_ClearFlag(uint32_t FlagMask)48void MISC_ClearFlag(uint32_t FlagMask) 49 { 50 /* Check parameters */ 51 assert_parameters(IS_MISC_FLAGC(FlagMask)); 52 53 MISC1->SRAMINT = FlagMask; 54 } 55 56 /** 57 * @brief Enables or disables MISC interrupt. 58 * @param INTMask: can use the '|' operator 59 MISC_INT_LOCK 60 MISC_INT_PIAC 61 MISC_INT_HIAC 62 MISC_INT_PERR 63 NewState: 64 ENABLE 65 DISABLE 66 * @retval None 67 */ MISC_INTConfig(uint32_t INTMask,uint32_t NewState)68void MISC_INTConfig(uint32_t INTMask, uint32_t NewState) 69 { 70 uint32_t tmp; 71 72 /* Check parameters */ 73 assert_parameters(IS_MISC_INT(INTMask)); 74 assert_parameters(IS_FUNCTIONAL_STATE(NewState)); 75 76 tmp = MISC1->SRAMINIT; 77 if (NewState == ENABLE) 78 { 79 tmp |= INTMask; 80 } 81 else 82 { 83 tmp &= ~INTMask; 84 } 85 MISC1->SRAMINIT = tmp; 86 } 87 88 /** 89 * @brief Enables or disables SRAM parity. 90 * @param NewState: 91 ENABLE 92 DISABLE 93 * @retval None 94 */ MISC_SRAMParityCmd(uint32_t NewState)95void MISC_SRAMParityCmd(uint32_t NewState) 96 { 97 /* Check parameters */ 98 assert_parameters(IS_FUNCTIONAL_STATE(NewState)); 99 100 if (NewState == ENABLE) 101 { 102 MISC1->SRAMINIT |= MISC1_SRAMINIT_PEN; 103 } 104 else 105 { 106 MISC1->SRAMINIT &= ~MISC1_SRAMINIT_PEN; 107 } 108 } 109 110 /** 111 * @brief Gets SRAM parity error address. 112 * @param None 113 * @retval parity error address. 114 */ MISC_GetSRAMPEAddr(void)115uint32_t MISC_GetSRAMPEAddr(void) 116 { 117 uint32_t tmp; 118 119 tmp = MISC1->PARERR; 120 tmp = tmp*4 + 0x20000000; 121 return tmp; 122 } 123 124 /** 125 * @brief Gets APB error address. 126 * @param None 127 * @retval APB error address. 128 */ MISC_GetAPBErrAddr(void)129uint32_t MISC_GetAPBErrAddr(void) 130 { 131 uint32_t tmp; 132 133 tmp = MISC1->PIADDR; 134 tmp = tmp + 0x40000000; 135 return tmp; 136 } 137 138 /** 139 * @brief Gets AHB error address. 140 * @param None 141 * @retval AHB error address. 142 */ MISC_GetAHBErrAddr(void)143uint32_t MISC_GetAHBErrAddr(void) 144 { 145 return (MISC1->HIADDR); 146 } 147 148 /** 149 * @brief Enables or disables UART transmit IR function. 150 * @param IRx: 151 MISC_IREN_TX0 152 MISC_IREN_TX1 153 MISC_IREN_TX2 154 MISC_IREN_TX3 155 MISC_IREN_TX4 156 MISC_IREN_TX5 157 NewState: 158 ENABLE 159 DISABLE 160 * @retval None 161 */ MISC_IRCmd(uint32_t IRx,uint32_t NewState)162void MISC_IRCmd(uint32_t IRx, uint32_t NewState) 163 { 164 uint32_t tmp; 165 166 /* Check parameters */ 167 assert_parameters(IS_FUNCTIONAL_STATE(NewState)); 168 assert_parameters(IS_MISC_IREN(IRx)); 169 170 tmp = MISC1->IREN; 171 if (NewState == ENABLE) 172 { 173 tmp |= IRx; 174 } 175 else 176 { 177 tmp &= ~IRx; 178 } 179 MISC1->IREN = tmp; 180 } 181 182 /** 183 * @brief Configures SUART transmit IR duty. 184 * @param DutyHigh 185 The high pulse width will be (DUTYH + 1)*APBCLK period. 186 DutyLow 187 The low pulse width will be (DUTYL + 1)*APBCLK period. 188 * @retval None 189 */ MISC_IRDutyConfig(uint16_t DutyHigh,uint16_t DutyLow)190void MISC_IRDutyConfig(uint16_t DutyHigh, uint16_t DutyLow) 191 { 192 MISC1->DUTYH = DutyHigh; 193 MISC1->DUTYL = DutyLow; 194 } 195 196 /** 197 * @brief Enables or disables Hardfault generation. 198 * @param NewState: 199 ENABLE 200 DISABLE 201 * @retval None 202 */ MISC_HardFaultCmd(uint32_t NewState)203void MISC_HardFaultCmd(uint32_t NewState) 204 { 205 /* Check parameters */ 206 assert_parameters(IS_FUNCTIONAL_STATE(NewState)); 207 208 if (NewState == ENABLE) 209 { 210 MISC1->IRQLAT &= ~MISC1_IRQLAT_NOHARDFAULT; 211 } 212 else 213 { 214 MISC1->IRQLAT |= MISC1_IRQLAT_NOHARDFAULT; 215 } 216 } 217 218 /** 219 * @brief Enables or disables a system reset when the CM0 lockup happened. 220 * @param NewState: 221 ENABLE 222 DISABLE 223 * @retval None 224 */ MISC_LockResetCmd(uint32_t NewState)225void MISC_LockResetCmd(uint32_t NewState) 226 { 227 /* Check parameters */ 228 assert_parameters(IS_FUNCTIONAL_STATE(NewState)); 229 230 if (NewState == ENABLE) 231 { 232 MISC1->IRQLAT |= MISC1_IRQLAT_LOCKRESET; 233 } 234 else 235 { 236 MISC1->IRQLAT &= ~MISC1_IRQLAT_LOCKRESET; 237 } 238 } 239 240 /** 241 * @brief Configures IRQ latency. 242 * @param Latency:0~255 243 * @retval None 244 */ MISC_IRQLATConfig(uint8_t Latency)245void MISC_IRQLATConfig(uint8_t Latency) 246 { 247 uint32_t tmp; 248 249 tmp = MISC1->IRQLAT; 250 tmp &= ~MISC1_IRQLAT_IRQLAT; 251 tmp |= Latency; 252 MISC1->IRQLAT = tmp; 253 } 254 255 /*********************************** END OF FILE ******************************/ 256