1 /* 2 ****************************************************************************** 3 * @file HAL_DMA.h 4 * @version V1.0.0 5 * @date 2020 6 * @brief Header file of DMA HAL module. 7 ****************************************************************************** 8 */ 9 #ifndef __HAL_DMA_H__ 10 #define __HAL_DMA_H__ 11 12 #include "ACM32Fxx_HAL.h" 13 14 #define DMA_CHANNEL_NUM (5) 15 16 /** @defgroup DMA_DATA_FLOW 17 * @{ 18 */ 19 #define DMA_DATA_FLOW_M2M (0x00000000) 20 #define DMA_DATA_FLOW_M2P (0x00000800) 21 #define DMA_DATA_FLOW_P2M (0x00001000) 22 /** 23 * @} 24 */ 25 26 27 /** @defgroup REQUEST_ID 28 * @{ 29 */ 30 #define REG_M2M (0) 31 32 #define REQ0_ADC (0) 33 #define REQ1_SPI1_SEND (1) 34 #define REQ2_SPI1_RECV (2) 35 #define REQ3_SPI2_SEND (3) 36 #define REQ4_SPI2_RECV (4) 37 #define REQ5_UART1_SEND (5) 38 #define REQ6_UART1_RECV (6) 39 #define REQ7_UART2_SEND (7) 40 #define REQ8_UART2_RECV (8) 41 #define REQ9_I2C1_SEND (9) 42 #define REQ10_I2C1_RECV (10) 43 #define REQ11_I2C2_SEND (11) 44 #define REQ12_I2C2_RECV (12) 45 #define REQ13_TIM1_CH1 (13) 46 #define REQ14_TIM1_CH2 (14) 47 #define REQ15_TIM1_CH3 (15) 48 #define REQ16_TIM1_CH4 (16) 49 #define REQ17_TIM1_UP (17) 50 #define REQ18_TIM1_TRIG_COM (18) 51 #define REQ19_TIM3_CH3 (19) 52 #define REQ20_TIM3_CH4_OR_UP (20) 53 #define REQ21_TIM3_CH1_OR_TRIG (21) 54 #define REQ22_TIM3_CH2_LCDFRAME (22) 55 #define REQ23_TIM6_UP (23) 56 #define REQ24_TIM15_CH1_UP_TRIG_COM (24) 57 #define REQ25_TIM15_CH2 (25) 58 #define REQ26_TIM16_CH1_UP (26) 59 #define REQ27_UART3_SEND (27) 60 #define REQ28_TIM17_CH1_UP (28) 61 #define REQ29_UART3_RECV (29) 62 #define REQ30_LPUART_SEND (30) 63 #define REQ31_LPUART_RECV (31) 64 65 #define REQ_MAX_LIMIT (32) 66 /** 67 * @} 68 */ 69 70 71 /** @defgroup DMA_SOURCE_ADDR_INCREASE 72 * @{ 73 */ 74 #define DMA_SOURCE_ADDR_INCREASE_DISABLE (0x00000000) 75 #define DMA_SOURCE_ADDR_INCREASE_ENABLE (0x04000000) 76 /** 77 * @} 78 */ 79 80 81 /** @defgroup DMA_DST_ADDR_INCREASE 82 * @{ 83 */ 84 #define DMA_DST_ADDR_INCREASE_DISABLE (0x00000000) 85 #define DMA_DST_ADDR_INCREASE_ENABLE (0x08000000) 86 /** 87 * @} 88 */ 89 90 91 /** @defgroup DMA_SRC_WIDTH 92 * @{ 93 */ 94 #define DMA_SRC_WIDTH_BYTE (0x00000000) /* 8bit */ 95 #define DMA_SRC_WIDTH_HALF_WORD (0x00040000) /* 16bit */ 96 #define DMA_SRC_WIDTH_WORD (0x00080000) /* 36bit */ 97 /** 98 * @} 99 */ 100 101 /** @defgroup DMA_DST_WIDTH 102 * @{ 103 */ 104 #define DMA_DST_WIDTH_BYTE (0x00000000) /* 8bit */ 105 #define DMA_DST_WIDTH_HALF_WORD (0x00200000) /* 16bit */ 106 #define DMA_DST_WIDTH_WORD (0x00400000) /* 36bit */ 107 /** 108 * @} 109 */ 110 111 112 113 /** @defgroup DMA_MODE DMA MODE 114 * @{ 115 */ 116 #define DMA_NORMAL 0x00000000U /*!< Normal mode */ 117 #define DMA_CIRCULAR 0x00000001U /*!< Circular mode */ 118 /** 119 * @} 120 */ 121 122 /** 123 * @brief DMA burst length Structure definition 124 */ 125 typedef enum 126 { 127 DMA_BURST_LENGTH_1 = 0, 128 DMA_BURST_LENGTH_4 = 1, 129 DMA_BURST_LENGTH_8 = 2, 130 DMA_BURST_LENGTH_16 = 3, 131 DMA_BURST_LENGTH_32 = 4, 132 DMA_BURST_LENGTH_64 = 5, 133 DMA_BURST_LENGTH_128 = 6, 134 DMA_BURST_LENGTH_256 = 7, 135 }DMA_BURST_LENGTH; 136 137 138 /** 139 * @brief DMA Configuration Structure definition 140 */ 141 typedef struct 142 { 143 uint32_t Mode; /* This parameter can be a value of @ref DMA_MODE */ 144 145 uint32_t Data_Flow; /* This parameter can be a value of @ref DMA_DATA_FLOW */ 146 147 uint32_t Request_ID; /* This parameter can be a value of @ref REQUEST_ID */ 148 149 uint32_t Source_Inc; /* This parameter can be a value of @ref DMA_SOURCE_ADDR_INCREASE */ 150 151 uint32_t Desination_Inc; /* This parameter can be a value of @ref DMA_DST_ADDR_INCREASE */ 152 153 uint32_t Source_Width; /* This parameter can be a value of @ref DMA_SRC_WIDTH */ 154 155 uint32_t Desination_Width; /* This parameter can be a value of @ref DMA_DST_WIDTH */ 156 157 }DMA_InitParaTypeDef; 158 159 160 /** 161 * @brief DMA handle Structure definition 162 */ 163 typedef struct 164 { 165 DMA_Channel_TypeDef *Instance; /* DMA registers base address */ 166 167 DMA_InitParaTypeDef Init; /* DMA initialization parameters */ 168 169 void (*DMA_ITC_Callback)(void); /* DMA transfer complete callback */ 170 171 void (*DMA_IE_Callback)(void); /* DMA error complete callback */ 172 173 }DMA_HandleTypeDef; 174 175 /** 176 * @brief DMA Link List Item Structure 177 */ 178 typedef struct DMA_NextLink 179 { 180 uint32_t SrcAddr; /* source address */ 181 182 uint32_t DstAddr; /* desination address */ 183 184 struct DMA_NextLink *Next; /* Next Link */ 185 186 uint32_t Control; /* Control */ 187 188 }DMA_LLI_InitTypeDef; 189 190 191 /** @defgroup GPIO Private Macros 192 * @{ 193 */ 194 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ 195 ((MODE) == DMA_CIRCULAR)) 196 197 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA_Channel0) || \ 198 ((INSTANCE) == DMA_Channel1) || \ 199 ((INSTANCE) == DMA_Channel2) || \ 200 ((INSTANCE) == DMA_Channel3) || \ 201 ((INSTANCE) == DMA_Channel4)) 202 203 #define IS_DMA_DATA_FLOW(DATA_FLOW) (((DATA_FLOW) == DMA_DATA_FLOW_M2M) || \ 204 ((DATA_FLOW) == DMA_DATA_FLOW_M2P) || \ 205 ((DATA_FLOW) == DMA_DATA_FLOW_P2M)) 206 207 #define IS_DMA_REQUEST_ID(REQUEST_ID) ((REQUEST_ID < REQ_MAX_LIMIT) ? true : false) 208 209 #define IS_DMA_SRC_WIDTH(WIDTH) (((WIDTH) == DMA_SRC_WIDTH_BYTE) || \ 210 ((WIDTH) == DMA_SRC_WIDTH_HALF_WORD) || \ 211 ((WIDTH) == DMA_SRC_WIDTH_WORD)) 212 213 #define IS_DMA_DST_WIDTH(WIDTH) (((WIDTH) == DMA_DST_WIDTH_BYTE) || \ 214 ((WIDTH) == DMA_DST_WIDTH_HALF_WORD) || \ 215 ((WIDTH) == DMA_DST_WIDTH_WORD)) 216 /** 217 * @} 218 */ 219 220 /******************************************************************************/ 221 /* Peripheral Registers Bits Definition */ 222 /******************************************************************************/ 223 224 /******************************************************************************/ 225 /* (DMA) */ 226 /******************************************************************************/ 227 228 /**************** Bit definition for DMA CONFIG register ***********************/ 229 #define DMA_CONFIG_M2ENDIAN BIT2 230 #define DMA_CONFIG_M1ENDIAN BIT1 231 #define DMA_CONFIG_EN BIT0 232 233 /**************** Bit definition for DMA Channel CTRL register ***********************/ 234 #define DMA_CHANNEL_CTRL_ITC BIT31 235 #define DMA_CHANNEL_CTRL_DI BIT27 236 #define DMA_CHANNEL_CTRL_SI BIT26 237 238 239 /**************** Bit definition for DMA Channel CONFIG register ***********************/ 240 #define DMA_CHANNEL_CONFIG_HALT BIT18 241 #define DMA_CHANNEL_CONFIG_ACTIVE BIT17 242 #define DMA_CHANNEL_CONFIG_LOCK BIT16 243 #define DMA_CHANNEL_CONFIG_ITC BIT15 244 #define DMA_CHANNEL_CONFIG_IE BIT14 245 #define DMA_CHANNEL_CONFIG_FLOW_CTRL (BIT11|BIT12|BIT13) 246 #define DMA_CHANNEL_CONFIG_DEST_PERIPH (BIT6|BIT7|BIT8|BIT9|BIT10) 247 #define DMA_CHANNEL_CONFIG_DEST_PERIPH_POS (6) 248 #define DMA_CHANNEL_CONFIG_SRC_PERIPH (BIT1|BIT2|BIT3|BIT4|BIT5) 249 #define DMA_CHANNEL_CONFIG_SRC_PERIPH_POS (1) 250 #define DMA_CHANNEL_CONFIG_EN BIT0 251 252 253 /* Exported functions --------------------------------------------------------*/ 254 255 #define __HAL_LINK_DMA(_HANDLE_, _DMA_LINK_, _DMA_HANDLE_) (_HANDLE_._DMA_LINK_ = &_DMA_HANDLE_) 256 257 /* HAL_DMA_IRQHandler */ 258 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); 259 260 /* HAL_DMA_Init */ 261 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); 262 263 /* HAL_DMA_DeInit */ 264 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma); 265 266 /* HAL_DMA_Start */ 267 HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t fu32_SrcAddr, uint32_t fu32_DstAddr, uint32_t fu32_Size); 268 269 /* HAL_DMA_Start */ 270 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t fu32_SrcAddr, uint32_t fu32_DstAddr, uint32_t fu32_Size); 271 272 /* HAL_DMA_Abort */ 273 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); 274 275 /* HAL_DMA_GetState */ 276 HAL_StatusTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); 277 278 #endif 279