1 /*********************************************************************** 2 * Filename : hal_timer.h 3 * Description : timer driver header file 4 * Author(s) : Eric 5 * version : V1.0 6 * Modify date : 2016-03-24 7 ***********************************************************************/ 8 #ifndef __HAL_TIMER_H__ 9 #define __HAL_TIMER_H__ 10 11 #include "ACM32Fxx_HAL.h" 12 13 #define IS_TIMER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM3) \ 14 || ((INSTANCE) == TIM6) \ 15 || ((INSTANCE) == TIM14) || ((INSTANCE) == TIM15) || ((INSTANCE) == TIM16)\ 16 | ((INSTANCE) == TIM17) ) 17 18 /****************** TIM Instances : supporting the break function *************/ 19 #define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 20 ((INSTANCE) == TIM15) || \ 21 ((INSTANCE) == TIM16) || \ 22 ((INSTANCE) == TIM17)) 23 24 /************** TIM Instances : supporting Break source selection *************/ 25 #define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 26 ((INSTANCE) == TIM15) || \ 27 ((INSTANCE) == TIM16) || \ 28 ((INSTANCE) == TIM17)) 29 30 31 /************* TIM Instances : at least 1 capture/compare channel *************/ 32 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 33 ((INSTANCE) == TIM2) || \ 34 ((INSTANCE) == TIM3) || \ 35 ((INSTANCE) == TIM4) || \ 36 ((INSTANCE) == TIM14) || \ 37 ((INSTANCE) == TIM15) || \ 38 ((INSTANCE) == TIM16) || \ 39 ((INSTANCE) == TIM17)) 40 41 /************ TIM Instances : at least 2 capture/compare channels *************/ 42 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 43 ((INSTANCE) == TIM2) || \ 44 ((INSTANCE) == TIM3) || \ 45 ((INSTANCE) == TIM4) || \ 46 ((INSTANCE) == TIM15)) 47 48 /************ TIM Instances : at least 3 capture/compare channels *************/ 49 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 50 ((INSTANCE) == TIM2) || \ 51 ((INSTANCE) == TIM3) || \ 52 ((INSTANCE) == TIM4)) 53 54 /************ TIM Instances : at least 4 capture/compare channels *************/ 55 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 56 ((INSTANCE) == TIM2) || \ 57 ((INSTANCE) == TIM3) || \ 58 ((INSTANCE) == TIM4)) 59 60 61 /****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/ 62 #define IS_TIM_UDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 63 ((INSTANCE) == TIM3) || \ 64 ((INSTANCE) == TIM6) || \ 65 ((INSTANCE) == TIM7) || \ 66 ((INSTANCE) == TIM15) || \ 67 ((INSTANCE) == TIM16) || \ 68 ((INSTANCE) == TIM17)) 69 70 /******************* TIM Instances : output(s) available **********************/ 71 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \ 72 ( (((INSTANCE) == TIM1) && \ 73 (((CHANNEL) == TIM_CHANNEL_1) || \ 74 ((CHANNEL) == TIM_CHANNEL_2) || \ 75 ((CHANNEL) == TIM_CHANNEL_3) || \ 76 ((CHANNEL) == TIM_CHANNEL_4) ) ) \ 77 || \ 78 (((INSTANCE) == TIM3) && \ 79 (((CHANNEL) == TIM_CHANNEL_1) || \ 80 ((CHANNEL) == TIM_CHANNEL_2) || \ 81 ((CHANNEL) == TIM_CHANNEL_3) || \ 82 ((CHANNEL) == TIM_CHANNEL_4)) ) \ 83 || \ 84 (((INSTANCE) == TIM14) && \ 85 (((CHANNEL) == TIM_CHANNEL_1)) ) \ 86 || \ 87 (((INSTANCE) == TIM15) && \ 88 (((CHANNEL) == TIM_CHANNEL_1) || \ 89 ((CHANNEL) == TIM_CHANNEL_2)) ) \ 90 || \ 91 (((INSTANCE) == TIM16) && \ 92 (((CHANNEL) == TIM_CHANNEL_1)) ) \ 93 || \ 94 (((INSTANCE) == TIM17) && \ 95 ((CHANNEL) == TIM_CHANNEL_1) ) ) 96 97 /****************** TIM Instances : supporting complementary output(s) ********/ 98 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \ 99 ((( (INSTANCE) == TIM1) && \ 100 (((CHANNEL) == TIM_CHANNEL_1) || \ 101 ((CHANNEL) == TIM_CHANNEL_2) || \ 102 ((CHANNEL) == TIM_CHANNEL_3)) ) \ 103 || \ 104 (((INSTANCE) == TIM15) && \ 105 ((CHANNEL) == TIM_CHANNEL_1)) \ 106 || \ 107 (((INSTANCE) == TIM16) && \ 108 ((CHANNEL) == TIM_CHANNEL_1)) \ 109 || \ 110 (((INSTANCE) == TIM17) && \ 111 ((CHANNEL) == TIM_CHANNEL_1) ) ) 112 113 /****************** TIM Instances : supporting clock division *****************/ 114 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 115 ((INSTANCE) == TIM3) || \ 116 ((INSTANCE) == TIM14) || \ 117 ((INSTANCE) == TIM15) || \ 118 ((INSTANCE) == TIM16) || \ 119 ((INSTANCE) == TIM17)) 120 121 /****** TIM Instances : supporting external clock mode 1 for ETRF input *******/ 122 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 123 ((INSTANCE) == TIM2) \ 124 ((INSTANCE) == TIM3) \ 125 ((INSTANCE) == TIM4) ) 126 127 /****** TIM Instances : supporting external clock mode 2 for ETRF input *******/ 128 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 129 ((INSTANCE) == TIM2) \ 130 ((INSTANCE) == TIM3) \ 131 ((INSTANCE) == TIM4) ) 132 133 /****************** TIM Instances : supporting combined 3-phase PWM mode ******/ 134 #define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) ((INSTANCE) == TIM1) 135 136 /****************** TIM Instances : supporting commutation event generation ***/ 137 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 138 ((INSTANCE) == TIM15) || \ 139 ((INSTANCE) == TIM16) || \ 140 ((INSTANCE) == TIM17)) 141 142 /****************** TIM Instances : supporting encoder interface **************/ 143 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 144 ((INSTANCE) == TIM2) \ 145 ((INSTANCE) == TIM3) \ 146 ((INSTANCE) == TIM4) ) 147 148 /****************** TIM Instances : supporting Hall sensor interface **********/ 149 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 150 ((INSTANCE) == TIM2) \ 151 ((INSTANCE) == TIM3) \ 152 ((INSTANCE) == TIM4) ) 153 154 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/ 155 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 156 ((INSTANCE) == TIM3) || \ 157 ((INSTANCE) == TIM15)) 158 159 /****************** TIM Instances : supporting repetition counter *************/ 160 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 161 ((INSTANCE) == TIM15) || \ 162 ((INSTANCE) == TIM16) || \ 163 ((INSTANCE) == TIM17)) 164 165 #define HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__)) 166 #define HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__)) 167 168 #define HAL_TIM_ENABLE_IT_EX(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->DIER |= (__INTERRUPT__)) 169 #define HAL_TIM_DISABLE_IT_EX(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->DIER &= ~(__INTERRUPT__)) 170 171 #define HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA_REQ__) ((__HANDLE__)->Instance->DIER |= (__DMA_REQ__)) 172 #define HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA_REQ__) ((__HANDLE__)->Instance->DIER &= ~(__DMA_REQ__)) 173 174 175 176 #define TIM_CR2_CCPC_Pos (0U) 177 #define TIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos) 178 #define TIM_CR2_CCPC TIM_CR2_CCPC_Msk 179 #define TIM_CR2_CCUS_Pos (2U) 180 #define TIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos) 181 #define TIM_CR2_CCUS TIM_CR2_CCUS_Msk 182 #define TIM_CR2_CCDS_Pos (3U) 183 #define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos) 184 #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk 185 186 #define TIM_COMMUTATION_TRGI TIM_CR2_CCUS 187 #define TIM_COMMUTATION_SOFTWARE 0x00000000U 188 189 #define TIM_IT_UPDATE BIT0 190 #define TIM_IT_CC1 BIT1 191 #define TIM_IT_CC2 BIT2 192 #define TIM_IT_CC3 BIT3 193 #define TIM_IT_CC4 BIT4 194 #define TIM_IT_COM BIT5 195 #define TIM_IT_TRIGGER BIT6 196 #define TIM_IT_BREAK BIT7 197 198 #define TIM_DMA_UPDATE BIT8 199 #define TIM_DMA_CC1 BIT9 200 #define TIM_DMA_CC2 BIT10 201 #define TIM_DMA_CC3 BIT11 202 #define TIM_DMA_CC4 BIT12 203 #define TIM_DMA_COM BIT13 204 #define TIM_DMA_TRIGGER BIT14 205 #define TIM_DMA_BREAK BIT15 206 207 208 209 #define TIM_EVENTSOURCE_UPDATE BIT0 /*!< Reinitialize the counter and generates an update of the registers */ 210 #define TIM_EVENTSOURCE_CC1 BIT1 /*!< A capture/compare event is generated on channel 1 */ 211 #define TIM_EVENTSOURCE_CC2 BIT2 /*!< A capture/compare event is generated on channel 2 */ 212 #define TIM_EVENTSOURCE_CC3 BIT3 /*!< A capture/compare event is generated on channel 3 */ 213 #define TIM_EVENTSOURCE_CC4 BIT4 /*!< A capture/compare event is generated on channel 4 */ 214 #define TIM_EVENTSOURCE_COM BIT5 /*!< A commutation event is generated */ 215 #define TIM_EVENTSOURCE_TRIGGER BIT6 /*!< A trigger event is generated */ 216 #define TIM_EVENTSOURCE_BREAK BIT7 /*!< A break event is generated */ 217 218 #define TIM_ARR_PRELOAD_DISABLE 0 219 #define TIM_ARR_PRELOAD_ENABLE 1 220 221 #define TIM_COUNTERMODE_DIR_INDEX 4 222 #define TIM_COUNTERMODE_UP (0 << TIM_COUNTERMODE_DIR_INDEX) 223 #define TIM_COUNTERMODE_DOWN (1 << TIM_COUNTERMODE_DIR_INDEX) 224 225 #define TIM_COUNTERMODE_CMS_INDEX 5 226 #define TIM_COUNTERMODE_CENTERALIGNED1 (1 << TIM_COUNTERMODE_CMS_INDEX) 227 #define TIM_COUNTERMODE_CENTERALIGNED2 (2 << TIM_COUNTERMODE_CMS_INDEX) 228 #define TIM_COUNTERMODE_CENTERALIGNED3 (3 << TIM_COUNTERMODE_CMS_INDEX) 229 230 #define TIM_CLKCK_DIV_INDEX 8 231 #define TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< Clock division: tDTS=tCK_INT */ 232 #define TIM_CLOCKDIVISION_DIV2 (1U << TIM_CLKCK_DIV_INDEX) /*!< Clock division: tDTS=2*tCK_INT */ 233 #define TIM_CLOCKDIVISION_DIV4 (2U << TIM_CLKCK_DIV_INDEX) /*!< Clock division: tDTS=4*tCK_INT */ 234 235 #define TIM_TRGO_RESET (0 << 4) 236 #define TIM_TRGO_ENABLE (1 << 4) 237 #define TIM_TRGO_UPDATE (2 << 4) 238 #define TIM_TRGO_CMP_PULSE (3 << 4) 239 #define TIM_TRGO_OC1REF (4 << 4) 240 #define TIM_TRGO_OC2REF (5 << 4) 241 #define TIM_TRGO_OC3REF (6 << 4) 242 #define TIM_TRGO_OC4REF (7 << 4) 243 244 #define TIM_MASTERSLAVEMODE_DISABLE 0 245 #define TIM_MASTERSLAVEMODE_ENABLE BIT7 246 247 248 #define TIM_SLAVE_MODE_INDEX 0 249 #define TIM_SLAVE_MODE_DIS (0U << TIM_SLAVE_MODE_INDEX) 250 #define TIM_SLAVE_MODE_ENC1 (1U << TIM_SLAVE_MODE_INDEX) 251 #define TIM_SLAVE_MODE_ENC2 (2U << TIM_SLAVE_MODE_INDEX) 252 #define TIM_SLAVE_MODE_ENC3 (3U << TIM_SLAVE_MODE_INDEX) 253 #define TIM_SLAVE_MODE_RST (4U << TIM_SLAVE_MODE_INDEX) 254 #define TIM_SLAVE_MODE_GATE (5U << TIM_SLAVE_MODE_INDEX) 255 #define TIM_SLAVE_MODE_TRIG (6U << TIM_SLAVE_MODE_INDEX) 256 #define TIM_SLAVE_MODE_EXT1 (7U << TIM_SLAVE_MODE_INDEX) 257 258 #define TIM_TRIGGER_SOURCE_INDEX 4 259 #define TIM_TRIGGER_SOURCE_ITR0 (0U << TIM_TRIGGER_SOURCE_INDEX) 260 #define TIM_TRIGGER_SOURCE_ITR1 (1U << TIM_TRIGGER_SOURCE_INDEX) 261 #define TIM_TRIGGER_SOURCE_ITR2 (2U << TIM_TRIGGER_SOURCE_INDEX) 262 #define TIM_TRIGGER_SOURCE_ITR3 (3U << TIM_TRIGGER_SOURCE_INDEX) 263 #define TIM_TRIGGER_SOURCE_TI1F_ED (4U << TIM_TRIGGER_SOURCE_INDEX) 264 #define TIM_TRIGGER_SOURCE_TI1FP1 (5U << TIM_TRIGGER_SOURCE_INDEX) 265 #define TIM_TRIGGER_SOURCE_TI2FP2 (6U << TIM_TRIGGER_SOURCE_INDEX) 266 #define TIM_TRIGGER_SOURCE_ETRF (7U << TIM_TRIGGER_SOURCE_INDEX) 267 268 #define TIMER_SR_UIF BIT0 269 #define TIMER_SR_CC1IF BIT1 270 #define TIMER_SR_CC2IF BIT2 271 #define TIMER_SR_CC3IF BIT3 272 #define TIMER_SR_CC4IF BIT4 273 #define TIMER_SR_COMIF BIT5 274 #define TIMER_SR_TIF BIT6 275 #define TIMER_SR_BIF BIT7 276 #define TIMER_SR_CC1OF BIT9 277 #define TIMER_SR_CC2OF BIT10 278 #define TIMER_SR_CC3OF BIT11 279 #define TIMER_SR_CC4OF BIT12 280 281 #define TIMER_INT_EN_UPD BIT0 282 #define TIMER_INT_EN_CC1 BIT1 283 #define TIMER_INT_EN_CC2 BIT2 284 #define TIMER_INT_EN_CC3 BIT3 285 #define TIMER_INT_EN_CC4 BIT4 286 #define TIMER_INT_EN_COM BIT5 287 #define TIMER_INT_EN_TRI BIT6 288 #define TIMER_INT_EN_BRK BIT7 289 290 #define TIMER_DMA_EN_UPD BIT8 291 #define TIMER_DMA_EN_CC1 BIT9 292 #define TIMER_DMA_EN_CC2 BIT10 293 #define TIMER_DMA_EN_CC3 BIT11 294 #define TIMER_DMA_EN_CC4 BIT12 295 #define TIMER_DMA_EN_COM BIT13 296 #define TIMER_DMA_EN_TRI BIT14 297 298 #define TIM_CHANNEL_1 0 299 #define TIM_CHANNEL_2 1 300 #define TIM_CHANNEL_3 2 301 #define TIM_CHANNEL_4 3 302 303 #define OUTPUT_FAST_MODE_DISABLE 0 304 #define OUTPUT_FAST_MODE_ENABLE 1 305 306 #define OUTPUT_POL_ACTIVE_HIGH 0 307 #define OUTPUT_POL_ACTIVE_LOW 1 308 309 #define OUTPUT_DISABLE_IDLE_STATE 0 310 #define OUTPUT_ENABLE_IDLE_STATE 1 311 312 #define OUTPUT_IDLE_STATE_0 0 313 #define OUTPUT_IDLE_STATE_1 1 314 315 #define OUTPUT_MODE_FROZEN 0 316 #define OUTPUT_MODE_MATCH_HIGH 1 317 #define OUTPUT_MODE_MATCH_LOW 2 318 #define OUTPUT_MODE_MATCH_TOGGLE 3 319 #define OUTPUT_MODE_FORCE_LOW 4 320 #define OUTPUT_MODE_FORCE_HIGH 5 321 #define OUTPUT_MODE_PWM1 6 322 #define OUTPUT_MODE_PWM2 7 323 324 #define TIM_CLOCKSOURCE_INT 0 325 #define TIM_CLOCKSOURCE_ITR0 1 326 #define TIM_CLOCKSOURCE_ITR1 2 327 #define TIM_CLOCKSOURCE_ITR2 3 328 #define TIM_CLOCKSOURCE_ITR3 4 329 #define TIM_CLOCKSOURCE_TI1FP1 5 330 #define TIM_CLOCKSOURCE_TI2FP2 6 331 #define TIM_CLOCKSOURCE_ETR 7 332 333 #define TIM_ETR_POLAIRTY_HIGH 0 334 #define TIM_ETR_POLAIRTY_LOW (BIT15) 335 #define TIM_ETR_FILTER_LVL(x) (x << 8) //BIT8-BIT11 336 337 #define TIM_ETR_PRESCALER_1 0 338 #define TIM_ETR_PRESCALER_2 (BIT12) 339 #define TIM_ETR_PRESCALER_4 (BIT13) 340 #define TIM_ETR_PRESCALER_8 (BIT12|BIT13) 341 342 #define ETR_SELECT_GPIO 0 343 #define ETR_SELECT_COMP1_OUT BIT14 344 #define ETR_SELECT_COMP2_OUT BIT15 345 #define ETR_SELECT_ADC_AWD BIT14|BIT15 346 #define ETR_SELECT_MASK (BIT14|BIT15) 347 348 #define TIM_TI1_FILTER_LVL(x) (x << 4) 349 #define TIM_TI2_FILTER_LVL(x) (x << 12) 350 #define TIM_TI3_FILTER_LVL(x) (x << 4) 351 #define TIM_TI4_FILTER_LVL(x) (x << 12) 352 353 #define TIM_IC1_PRESCALER_1 0 354 #define TIM_IC1_PRESCALER_2 (BIT2) 355 #define TIM_IC1_PRESCALER_4 (BIT3) 356 #define TIM_IC1_PRESCALER_8 (BIT2|BIT3) 357 358 #define TIM_IC2_PRESCALER_1 0 359 #define TIM_IC2_PRESCALER_2 (BIT10) 360 #define TIM_IC2_PRESCALER_4 (BIT11) 361 #define TIM_IC2_PRESCALER_8 (BIT10|BIT11) 362 363 #define TIM_IC3_PRESCALER_1 0 364 #define TIM_IC3_PRESCALER_2 (BIT2) 365 #define TIM_IC3_PRESCALER_4 (BIT3) 366 #define TIM_IC3_PRESCALER_8 (BIT2|BIT3) 367 368 #define TIM_IC4_PRESCALER_1 0 369 #define TIM_IC4_PRESCALER_2 (BIT10) 370 #define TIM_IC4_PRESCALER_4 (BIT11) 371 #define TIM_IC4_PRESCALER_8 (BIT10|BIT11) 372 373 typedef struct 374 { 375 uint32_t ClockSource; //TIMER clock sources 376 uint32_t ClockPolarity; //TIMER clock polarity 377 uint32_t ClockPrescaler; //TIMER clock prescaler 378 uint32_t ClockFilter; //TIMER clock filter 379 } TIM_ClockConfigTypeDef; 380 381 typedef struct 382 { 383 uint32_t OCMode; // Specifies the TIM mode. 384 uint32_t Pulse; // Specifies the pulse value to be loaded into the Capture Compare Register. 385 uint32_t OCPolarity; // Specifies the output polarity. 386 uint32_t OCNPolarity; // Specifies the complementary output polarity. 387 uint32_t OCFastMode; // Specifies the Fast mode state. 388 uint32_t OCIdleState; // Specifies the TIM Output Compare pin state during Idle state. 389 uint32_t OCNIdleState; // Specifies the TIM Output Compare complementary pin state during Idle state. 390 } TIM_OC_InitTypeDef; 391 392 393 #define TIM_SLAVE_CAPTURE_ACTIVE_RISING 0 394 #define TIM_SLAVE_CAPTURE_ACTIVE_FALLING 1 395 #define TIM_SLAVE_CAPTURE_ACTIVE_RISING_FALLING 2 396 397 #define TIM_ICSELECTION_DIRECTTI 0 398 #define TIM_ICSELECTION_INDIRECTTI 1 399 400 #define TIM_CC1_SLAVE_CAPTURE_POL_RISING (0) 401 #define TIM_CC1_SLAVE_CAPTURE_POL_FALLING (BIT1) 402 #define TIM_CC1_SLAVE_CAPTURE_POL_BOTH (BIT1 | BIT3) 403 404 #define TIM_CC2_SLAVE_CAPTURE_POL_RISING (0) 405 #define TIM_CC2_SLAVE_CAPTURE_POL_FALLING (BIT5) 406 #define TIM_CC2_SLAVE_CAPTURE_POL_BOTH (BIT5 | BIT7) 407 408 #define TIM_CC3_SLAVE_CAPTURE_POL_RISING (0) 409 #define TIM_CC3_SLAVE_CAPTURE_POL_FALLING (BIT9) 410 #define TIM_CC3_SLAVE_CAPTURE_POL_BOTH (BIT9 | BIT11) 411 412 #define TIM_CC4_SLAVE_CAPTURE_POL_RISING (0) 413 #define TIM_CC4_SLAVE_CAPTURE_POL_FALLING (BIT13) 414 #define TIM_CC4_SLAVE_CAPTURE_POL_BOTH (BIT13 | BIT15) 415 416 typedef struct 417 { 418 uint32_t SlaveMode; // Slave mode selection 419 uint32_t InputTrigger; // Input Trigger source 420 uint32_t TriggerPolarity; // Input Trigger polarity 421 uint32_t TriggerPrescaler; // input prescaler, only for ETR input 422 uint32_t TriggerFilter; // Input trigger filter 423 } TIM_SlaveConfigTypeDef; 424 425 typedef struct 426 { 427 uint32_t ICPolarity; // Specifies the active edge of the input signal. 428 uint32_t ICSelection; // Specifies the input 429 uint32_t ICPrescaler; // Specifies the Input Capture Prescaler. 430 uint32_t TIFilter; // Specifies the input capture filter. 431 } TIM_IC_InitTypeDef; 432 433 typedef struct 434 { 435 uint32_t MasterOutputTrigger; // Trigger output (TRGO) selection 436 uint32_t MasterSlaveMode; // Master/slave mode selection 437 } TIM_MasterConfigTypeDef; 438 439 #define TIM_DMA_UPDATE_INDEX 0 440 #define TIM_DMA_CC1_INDEX 1 441 #define TIM_DMA_CC2_INDEX 2 442 #define TIM_DMA_CC3_INDEX 3 443 #define TIM_DMA_CC4_INDEX 4 444 #define TIM_DMA_COM_INDEX 5 445 #define TIM_DMA_TRIG_INDEX 6 446 447 #define MAX_DMA_REQ_ONE_TIMER 7 448 449 typedef struct 450 { 451 uint32_t Prescaler; // Specifies the prescaler value used to divide the TIM clock. 452 uint32_t Period; // Specifies the ARR value 453 uint32_t ARRPreLoadEn; // Specifies the preload enable or disable 454 uint32_t RepetitionCounter; // Specifies the repetition counter value 455 uint32_t CounterMode; // Specifies the counter mode.Up/Down/Center 456 uint32_t ClockDivision; // Specifies the clock division, used for deadtime or sampling 457 } TIM_Base_InitTypeDef; 458 459 typedef struct 460 { 461 TIM_TypeDef *Instance; 462 TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ 463 DMA_HandleTypeDef *hdma[MAX_DMA_REQ_ONE_TIMER]; 464 }TIM_HandleTypeDef; 465 466 /* HAL_TIMER_MSP_Init */ 467 extern uint32_t HAL_TIMER_MSP_Init(TIM_HandleTypeDef * htim); 468 /* HAL_TIMER_Slave_Mode_Config */ 469 extern uint32_t HAL_TIMER_Slave_Mode_Config(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig); 470 /* HAL_TIMER_Base_Init */ 471 extern uint32_t HAL_TIMER_Base_Init(TIM_HandleTypeDef * htim); 472 /* HAL_TIMER_Output_Config */ 473 extern uint32_t HAL_TIMER_Output_Config(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef * Output_Config, uint32_t Channel); 474 /* HAL_TIMER_Base_Start */ 475 extern void HAL_TIMER_Base_Start(TIM_TypeDef *TIMx); 476 extern HAL_StatusTypeDef HAL_TIMER_Base_Stop(TIM_TypeDef *TIMx); 477 /* HAL_TIM_PWM_Output_Start */ 478 extern uint32_t HAL_TIM_PWM_Output_Start(TIM_TypeDef *TIMx, uint32_t Channel); 479 /* HAL_TIM_PWM_Output_Stop */ 480 extern HAL_StatusTypeDef HAL_TIM_PWM_Output_Stop(TIM_TypeDef *TIMx, uint32_t Channel); 481 /* HAL_TIMER_OC_Start */ 482 extern uint32_t HAL_TIMER_OC_Start(TIM_TypeDef *TIMx, uint32_t Channel); 483 /* HAL_TIMER_OCxN_Start */ 484 extern uint32_t HAL_TIMER_OCxN_Start(TIM_TypeDef *TIMx, uint32_t Channel); 485 /* HAL_TIMER_OC_Stop */ 486 extern HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_TypeDef *TIMx, uint32_t Channel); 487 /* HAL_TIM_Capture_Start */ 488 extern uint32_t HAL_TIM_Capture_Start(TIM_TypeDef *TIMx, uint32_t Channel); 489 /* HAL_TIM_Capture_Stop */ 490 extern uint32_t HAL_TIM_Capture_Stop(TIM_TypeDef *TIMx, uint32_t Channel); 491 /* HAL_TIMER_Capture_Config */ 492 extern uint32_t HAL_TIMER_Capture_Config(TIM_TypeDef *TIMx, TIM_IC_InitTypeDef * Capture_Config, uint32_t Channel); 493 /* HAL_TIMER_Master_Mode_Config */ 494 extern uint32_t HAL_TIMER_Master_Mode_Config(TIM_TypeDef *TIMx, TIM_MasterConfigTypeDef * sMasterConfig); 495 /* HAL_TIMER_SelectClockSource */ 496 extern HAL_StatusTypeDef HAL_TIMER_SelectClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig); 497 /* HAL_TIMER_ReadCapturedValue */ 498 extern uint32_t HAL_TIMER_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel); 499 /* HAL_TIMER_Clear_Capture_Flag */ 500 extern void HAL_TIMER_Clear_Capture_Flag(TIM_HandleTypeDef *htim, uint32_t Channel); 501 #endif 502 503 504 505 506