1 /*********************************************************************** 2 * Filename : hal_timer_ex.h 3 * Description : timer driver header file 4 * Author(s) : xwl 5 * version : V1.0 6 * Modify date : 2021-03-24 7 ***********************************************************************/ 8 #ifndef __HAL_TIMER_EX_H__ 9 #define __HAL_TIMER_EX_H__ 10 11 #include "ACM32Fxx_HAL.h" 12 13 14 #define TIM_BDTR_DTG_Pos (0U) 15 #define TIM_BDTR_DTG_Msk (0xFFUL << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */ 16 #define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */ 17 #define TIM_BDTR_DTG_0 (0x01UL << TIM_BDTR_DTG_Pos) /*!< 0x00000001 */ 18 #define TIM_BDTR_DTG_1 (0x02UL << TIM_BDTR_DTG_Pos) /*!< 0x00000002 */ 19 #define TIM_BDTR_DTG_2 (0x04UL << TIM_BDTR_DTG_Pos) /*!< 0x00000004 */ 20 #define TIM_BDTR_DTG_3 (0x08UL << TIM_BDTR_DTG_Pos) /*!< 0x00000008 */ 21 #define TIM_BDTR_DTG_4 (0x10UL << TIM_BDTR_DTG_Pos) /*!< 0x00000010 */ 22 #define TIM_BDTR_DTG_5 (0x20UL << TIM_BDTR_DTG_Pos) /*!< 0x00000020 */ 23 #define TIM_BDTR_DTG_6 (0x40UL << TIM_BDTR_DTG_Pos) /*!< 0x00000040 */ 24 #define TIM_BDTR_DTG_7 (0x80UL << TIM_BDTR_DTG_Pos) 25 26 #define TIM_BDTR_LOCK_Pos (8U) 27 #define TIM_BDTR_LOCK_Msk (0x3UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */ 28 #define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */ 29 #define TIM_BDTR_LOCK_0 (0x1UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000100 */ 30 #define TIM_BDTR_LOCK_1 (0x2UL << TIM_BDTR_LOCK_Pos) 31 32 #define TIM_BDTR_OSSI_Pos (10U) 33 #define TIM_BDTR_OSSI_Msk (0x1UL << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */ 34 #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */ 35 #define TIM_BDTR_OSSR_Pos (11U) 36 #define TIM_BDTR_OSSR_Msk (0x1UL << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */ 37 #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */ 38 #define TIM_BDTR_BKE_Pos (12U) 39 #define TIM_BDTR_BKE_Msk (0x1UL << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */ 40 #define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable for Break 1 */ 41 #define TIM_BDTR_BKP_Pos (13U) 42 #define TIM_BDTR_BKP_Msk (0x1UL << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */ 43 #define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity for Break 1 */ 44 #define TIM_BDTR_AOE_Pos (14U) 45 #define TIM_BDTR_AOE_Msk (0x1UL << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */ 46 #define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */ 47 #define TIM_BDTR_MOE_Pos (15U) 48 #define TIM_BDTR_MOE_Msk (0x1UL << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */ 49 #define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */ 50 51 #define TIM_BDTR_BKF_Pos (16U) 52 #define TIM_BDTR_BKF_Msk (0xFUL << TIM_BDTR_BKF_Pos) /*!< 0x000F0000 */ 53 #define TIM_BDTR_BKF TIM_BDTR_BKF_Msk 54 55 #define TIM_BREAKINPUTSOURCE_BKIN 0x00000001U /* !< An external source (GPIO) is connected to the BKIN pin */ 56 #ifdef HAL_COMP_MODULE_ENABLED 57 #define TIM_BREAKINPUTSOURCE_COMP1 0x00000002U /* !< The COMP1 output is connected to the break input */ 58 #define TIM_BREAKINPUTSOURCE_COMP2 0x00000004U /* !< The COMP2 output is connected to the break input */ 59 #endif /* COMP1 && COMP2 */ 60 61 #define TIM_BREAKINPUT_BRK 0x00000001U 62 63 #define TIM1_AF1_BKINE_Pos (0U) 64 #define TIM1_AF1_BKINE_Msk (0x1UL << TIM1_AF1_BKINE_Pos) /*!< 0x00000001 */ 65 #define TIM1_AF1_BKINE TIM1_AF1_BKINE_Msk /*!<BRK BKIN input enable */ 66 #define TIM1_AF1_BKCMP1E_Pos (1U) 67 #define TIM1_AF1_BKCMP1E_Msk (0x1UL << TIM1_AF1_BKCMP1E_Pos) /*!< 0x00000002 */ 68 #define TIM1_AF1_BKCMP1E TIM1_AF1_BKCMP1E_Msk /*!<BRK COMP1 enable */ 69 #define TIM1_AF1_BKCMP2E_Pos (2U) 70 #define TIM1_AF1_BKCMP2E_Msk (0x1UL << TIM1_AF1_BKCMP2E_Pos) /*!< 0x00000004 */ 71 #define TIM1_AF1_BKCMP2E TIM1_AF1_BKCMP2E_Msk /*!<BRK COMP2 enable */ 72 #define TIM1_AF1_BKINP_Pos (9U) 73 #define TIM1_AF1_BKINP_Msk (0x1UL << TIM1_AF1_BKINP_Pos) /*!< 0x00000200 */ 74 #define TIM1_AF1_BKINP TIM1_AF1_BKINP_Msk /*!<BRK BKIN input polarity */ 75 #define TIM1_AF1_BKCMP1P_Pos (10U) 76 #define TIM1_AF1_BKCMP1P_Msk (0x1UL << TIM1_AF1_BKCMP1P_Pos) /*!< 0x00000400 */ 77 #define TIM1_AF1_BKCMP1P TIM1_AF1_BKCMP1P_Msk /*!<BRK COMP1 input polarity */ 78 #define TIM1_AF1_BKCMP2P_Pos (11U) 79 #define TIM1_AF1_BKCMP2P_Msk (0x1UL << TIM1_AF1_BKCMP2P_Pos) /*!< 0x00000800 */ 80 #define TIM1_AF1_BKCMP2P TIM1_AF1_BKCMP2P_Msk 81 82 83 typedef struct 84 { 85 uint32_t OffStateRunMode; // TIM off state in run mode 86 uint32_t OffStateIDLEMode; // TIM off state in IDLE mode 87 uint32_t LockLevel; // TIM Lock level 88 uint32_t DeadTime; // TIM dead Time 89 uint32_t BreakState; // TIM Break State 90 uint32_t BreakPolarity; // TIM Break input polarity 91 uint32_t BreakFilter; // Specifies the break input filter. 92 uint32_t AutomaticOutput; // TIM Automatic Output Enable state 93 } TIM_BreakDeadTimeConfigTypeDef; 94 95 typedef struct 96 { 97 uint32_t Source; /*!< Specifies the source of the timer break input. 98 This parameter can be a value of @ref TIMEx_Break_Input_Source */ 99 uint32_t Enable; /*!< Specifies whether or not the break input source is enabled. 100 This parameter can be a value of @ref TIMEx_Break_Input_Source_Enable */ 101 uint32_t Polarity; /*!< Specifies the break input source polarity. 102 This parameter can be a value of @ref TIMEx_Break_Input_Source_Polarity */ 103 } 104 TIMEx_BreakInputConfigTypeDef; 105 106 /******************* Bit definition for TIM_TISEL register *********************/ 107 #define TIM_TISEL_TI1SEL_Pos (0U) 108 #define TIM_TISEL_TI1SEL_Msk (0xFUL << TIM_TISEL_TI1SEL_Pos) /*!< 0x0000000F */ 109 #define TIM_TISEL_TI1SEL TIM_TISEL_TI1SEL_Msk /*!<TI1SEL[3:0] bits (TIM1 TI1 SEL)*/ 110 #define TIM_TISEL_TI1SEL_0 (0x1UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000001 */ 111 #define TIM_TISEL_TI1SEL_1 (0x2UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000002 */ 112 #define TIM_TISEL_TI1SEL_2 (0x4UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000004 */ 113 #define TIM_TISEL_TI1SEL_3 (0x8UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000008 */ 114 115 #define TIM_TISEL_TI2SEL_Pos (8U) 116 #define TIM_TISEL_TI2SEL_Msk (0xFUL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000F00 */ 117 #define TIM_TISEL_TI2SEL TIM_TISEL_TI2SEL_Msk /*!<TI2SEL[3:0] bits (TIM1 TI2 SEL)*/ 118 #define TIM_TISEL_TI2SEL_0 (0x1UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000100 */ 119 #define TIM_TISEL_TI2SEL_1 (0x2UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000200 */ 120 #define TIM_TISEL_TI2SEL_2 (0x4UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000400 */ 121 #define TIM_TISEL_TI2SEL_3 (0x8UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000800 */ 122 123 124 #endif 125 126 127 128 129