1 /* 2 ****************************************************************************** 3 * @file HAL_Can.h 4 * @version V1.0.0 5 * @date 2020 6 * @brief Header file of CAN HAL module. 7 ****************************************************************************** 8 */ 9 #ifndef __HAL_DAC_H__ 10 #define __HAL_DAC_H__ 11 12 #include "ACM32Fxx_HAL.h" 13 14 /** 15 * @} 16 */ 17 18 /******************************************************************************/ 19 /* Peripheral Registers Bits Definition */ 20 /******************************************************************************/ 21 /******************************************************************************/ 22 /* (DAC) */ 23 /******************************************************************************/ 24 25 /**************** Bit definition for DAC CR register ***********************/ 26 #define DAC_CR_EN1_Pos (0U) 27 #define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */ 28 #define DAC_CR_EN1 DAC_CR_EN1_Msk /*!<DAC channel1 enable */ 29 30 #define DAC_CR_TEN1_Pos (2U) 31 #define DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos) /*!< 0x00000002 */ 32 #define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!<DAC channel1 Trigger enable */ 33 34 #define DAC_CR_TSEL1_Pos (3U) 35 #define DAC_CR_TSEL1_Msk (0x7UL << DAC_CR_TSEL1_Pos) /*!< 0x0000003C */ 36 #define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!<TSEL1[3:0] (DAC channel1 Trigger selection) */ 37 #define DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos) /*!< 0x00000004 */ 38 #define DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */ 39 #define DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */ 40 41 #define DAC_CR_WAVE1_Pos (6U) 42 #define DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */ 43 #define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */ 44 #define DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */ 45 #define DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */ 46 47 #define DAC_CR_MAMP1_Pos (8U) 48 #define DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */ 49 #define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */ 50 #define DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */ 51 #define DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */ 52 #define DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */ 53 #define DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */ 54 55 #define DAC_CR_DMAEN1_Pos (12U) 56 #define DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */ 57 #define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!<DAC channel1 DMA enable */ 58 59 #define DAC_CR_DMAUDRIE1_Pos (13U) 60 #define DAC_CR_DMAUDRIE1_Msk (0x1UL << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */ 61 #define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!<DAC channel 1 DMA underrun interrupt enable >*/ 62 63 #define DAC_CR_CEN1_Pos (14U) 64 #define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ 65 #define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!<DAC channel 1 calibration enable >*/ 66 67 #define DAC_CR_EN2_Pos (16U) 68 #define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ 69 #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!<DAC channel2 enable */ 70 71 #define DAC_CR_TEN2_Pos (18U) 72 #define DAC_CR_TEN2_Msk (0x1UL << DAC_CR_TEN2_Pos) /*!< 0x00020000 */ 73 #define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!<DAC channel2 Trigger enable */ 74 75 #define DAC_CR_TSEL2_Pos (19U) 76 #define DAC_CR_TSEL2_Msk (0x7UL << DAC_CR_TSEL2_Pos) /*!< 0x003C0000 */ 77 #define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */ 78 #define DAC_CR_TSEL2_0 (0x1UL << DAC_CR_TSEL2_Pos) /*!< 0x00040000 */ 79 #define DAC_CR_TSEL2_1 (0x2UL << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */ 80 #define DAC_CR_TSEL2_2 (0x4UL << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */ 81 82 #define DAC_CR_WAVE2_Pos (22U) 83 #define DAC_CR_WAVE2_Msk (0x3UL << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */ 84 #define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */ 85 #define DAC_CR_WAVE2_0 (0x1UL << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */ 86 #define DAC_CR_WAVE2_1 (0x2UL << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */ 87 88 #define DAC_CR_MAMP2_Pos (24U) 89 #define DAC_CR_MAMP2_Msk (0xFUL << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */ 90 #define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */ 91 #define DAC_CR_MAMP2_0 (0x1UL << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */ 92 #define DAC_CR_MAMP2_1 (0x2UL << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */ 93 #define DAC_CR_MAMP2_2 (0x4UL << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */ 94 #define DAC_CR_MAMP2_3 (0x8UL << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */ 95 96 #define DAC_CR_DMAEN2_Pos (28U) 97 #define DAC_CR_DMAEN2_Msk (0x1UL << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */ 98 #define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!<DAC channel2 DMA enabled */ 99 100 #define DAC_CR_DMAUDRIE2_Pos (29U) 101 #define DAC_CR_DMAUDRIE2_Msk (0x1UL << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */ 102 #define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!<DAC channel2 DMA underrun interrupt enable >*/ 103 104 #define DAC_CR_CEN2_Pos (30U) 105 #define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ 106 #define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!<DAC channel2 calibration enable >*/ 107 108 /**************** Bit definition for DAC SWTRIGR register ***********************/ 109 #define DAC_SWTRIGR_SWTRIG1_Pos (0U) 110 #define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ 111 #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!<DAC channel1 software trigger */ 112 #define DAC_SWTRIGR_SWTRIG2_Pos (1U) 113 #define DAC_SWTRIGR_SWTRIG2_Msk (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */ 114 #define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!<DAC channel2 software trigger */ 115 116 /***************** Bit definition for DAC_DHR12R1 register ******************/ 117 #define DAC_DHR12R1_DACC1DHR_Pos (0U) 118 #define DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */ 119 #define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */ 120 121 /***************** Bit definition for DAC_DHR12L1 register ******************/ 122 #define DAC_DHR12L1_DACC1DHR_Pos (4U) 123 #define DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */ 124 #define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */ 125 126 /****************** Bit definition for DAC_DHR8R1 register ******************/ 127 #define DAC_DHR8R1_DACC1DHR_Pos (0U) 128 #define DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */ 129 #define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */ 130 131 /***************** Bit definition for DAC_DHR12R2 register ******************/ 132 #define DAC_DHR12R2_DACC2DHR_Pos (0U) 133 #define DAC_DHR12R2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */ 134 #define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */ 135 136 /***************** Bit definition for DAC_DHR12L2 register ******************/ 137 #define DAC_DHR12L2_DACC2DHR_Pos (4U) 138 #define DAC_DHR12L2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */ 139 #define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */ 140 141 /****************** Bit definition for DAC_DHR8R2 register ******************/ 142 #define DAC_DHR8R2_DACC2DHR_Pos (0U) 143 #define DAC_DHR8R2_DACC2DHR_Msk (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */ 144 #define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */ 145 146 /***************** Bit definition for DAC_DHR12RD register ******************/ 147 #define DAC_DHR12RD_DACC1DHR_Pos (0U) 148 #define DAC_DHR12RD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */ 149 #define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */ 150 #define DAC_DHR12RD_DACC2DHR_Pos (16U) 151 #define DAC_DHR12RD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */ 152 #define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */ 153 154 /***************** Bit definition for DAC_DHR12LD register ******************/ 155 #define DAC_DHR12LD_DACC1DHR_Pos (4U) 156 #define DAC_DHR12LD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */ 157 #define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */ 158 #define DAC_DHR12LD_DACC2DHR_Pos (20U) 159 #define DAC_DHR12LD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */ 160 #define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */ 161 162 /****************** Bit definition for DAC_DHR8RD register ******************/ 163 #define DAC_DHR8RD_DACC1DHR_Pos (0U) 164 #define DAC_DHR8RD_DACC1DHR_Msk (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */ 165 #define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */ 166 #define DAC_DHR8RD_DACC2DHR_Pos (8U) 167 #define DAC_DHR8RD_DACC2DHR_Msk (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */ 168 #define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */ 169 170 /******************* Bit definition for DAC_DOR1 register *******************/ 171 #define DAC_DOR1_DACC1DOR_Pos (0U) 172 #define DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */ 173 #define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!<DAC channel1 data output */ 174 175 /******************* Bit definition for DAC_DOR2 register *******************/ 176 #define DAC_DOR2_DACC2DOR_Pos (0U) 177 #define DAC_DOR2_DACC2DOR_Msk (0xFFFUL << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */ 178 #define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!<DAC channel2 data output */ 179 180 /******************** Bit definition for DAC_SR register ********************/ 181 #define DAC_SR_SAMOV1_Pos (8U) 182 #define DAC_SR_SAMOV1_Msk (0x1UL << DAC_SR_SAMOV1_Pos) /*!< 0x00002000 */ 183 #define DAC_SR_SAMOV1 DAC_SR_SAMOV1_Msk /*!<DAC channel1 DMA SAMOV1 flag */ 184 185 #define DAC_SR_DMAUDR1_Pos (13U) 186 #define DAC_SR_DMAUDR1_Msk (0x1UL << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */ 187 #define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!<DAC channel1 DMA underrun flag */ 188 189 #define DAC_SR_CAL_FLAG1_Pos (14U) 190 #define DAC_SR_CAL_FLAG1_Msk (0x1UL << DAC_SR_CAL_FLAG1_Pos) /*!< 0x00004000 */ 191 #define DAC_SR_CAL_FLAG1 DAC_SR_CAL_FLAG1_Msk /*!<DAC channel1 calibration offset status */ 192 193 #define DAC_SR_SAMOV2_Pos (24U) 194 #define DAC_SR_SAMOV2_Msk (0x1UL << DAC_SR_SAMOV2_Pos) /*!< 0x00002000 */ 195 #define DAC_SR_SAMOV2 DAC_SR_SAMOV2_Msk /*!<DAC channel1 DMA SAMOV1 flag */ 196 197 #define DAC_SR_DMAUDR2_Pos (29U) 198 #define DAC_SR_DMAUDR2_Msk (0x1UL << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */ 199 #define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!<DAC channel2 DMA underrun flag */ 200 #define DAC_SR_CAL_FLAG2_Pos (30U) 201 #define DAC_SR_CAL_FLAG2_Msk (0x1UL << DAC_SR_CAL_FLAG2_Pos) /*!< 0x40000000 */ 202 #define DAC_SR_CAL_FLAG2 DAC_SR_CAL_FLAG2_Msk /*!<DAC channel2 calibration offset status */ 203 204 /**************** Bit definition for DAC CCR register ***********************/ 205 #define DAC_CCR_OTRIM1_Pos (0U) 206 #define DAC_CCR_OTRIM1_Msk (0x1FUL << DAC_CCR_OTRIM1_Pos) /*!< 0x0000001F */ 207 #define DAC_CCR_OTRIM1 DAC_CCR_OTRIM1_Msk /*!<DAC channel1 offset trimming value */ 208 #define DAC_CCR_OTRIM2_Pos (16U) 209 #define DAC_CCR_OTRIM2_Msk (0x1FUL << DAC_CCR_OTRIM2_Pos) /*!< 0x001F0000 */ 210 #define DAC_CCR_OTRIM2 DAC_CCR_OTRIM2_Msk /*!<DAC channel2 offset trimming value */ 211 212 /******************* Bit definition for DAC_MCR register *******************/ 213 #define DAC_MCR_MODE1_Pos (0U) 214 #define DAC_MCR_MODE1_Msk (0x7UL << DAC_MCR_MODE1_Pos) /*!< 0x00000007 */ 215 #define DAC_MCR_MODE1 DAC_MCR_MODE1_Msk /*!<MODE1[2:0] (DAC channel1 mode) */ 216 #define DAC_MCR_MODE1_0 (0x1UL << DAC_MCR_MODE1_Pos) /*!< 0x00000001 */ 217 #define DAC_MCR_MODE1_1 (0x2UL << DAC_MCR_MODE1_Pos) /*!< 0x00000002 */ 218 #define DAC_MCR_MODE1_2 (0x4UL << DAC_MCR_MODE1_Pos) /*!< 0x00000004 */ 219 220 #define DAC_MCR_MODE2_Pos (16U) 221 #define DAC_MCR_MODE2_Msk (0x7UL << DAC_MCR_MODE2_Pos) /*!< 0x00070000 */ 222 #define DAC_MCR_MODE2 DAC_MCR_MODE2_Msk /*!<MODE2[2:0] (DAC channel2 mode) */ 223 #define DAC_MCR_MODE2_0 (0x1UL << DAC_MCR_MODE2_Pos) /*!< 0x00010000 */ 224 #define DAC_MCR_MODE2_1 (0x2UL << DAC_MCR_MODE2_Pos) /*!< 0x00020000 */ 225 #define DAC_MCR_MODE2_2 (0x4UL << DAC_MCR_MODE2_Pos) /*!< 0x00040000 */ 226 227 228 /****************** Bit definition for DAC_SHSR1 register ******************/ 229 #define DAC_SHSR1_TSAMPLE1_Pos (0U) 230 #define DAC_SHSR1_TSAMPLE1_Msk (0x3FFUL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x000003FF */ 231 #define DAC_SHSR1_TSAMPLE1 DAC_SHSR1_TSAMPLE1_Msk /*!<DAC channel1 sample time */ 232 233 /****************** Bit definition for DAC_SHSR2 register ******************/ 234 #define DAC_SHSR2_TSAMPLE2_Pos (0U) 235 #define DAC_SHSR2_TSAMPLE2_Msk (0x3FFUL << DAC_SHSR2_TSAMPLE2_Pos) /*!< 0x000003FF */ 236 #define DAC_SHSR2_TSAMPLE2 DAC_SHSR2_TSAMPLE2_Msk /*!<DAC channel2 sample time */ 237 238 /****************** Bit definition for DAC_SHHR register ******************/ 239 #define DAC_SHHR_THOLD1_Pos (0U) 240 #define DAC_SHHR_THOLD1_Msk (0x3FFUL << DAC_SHHR_THOLD1_Pos) /*!< 0x000003FF */ 241 #define DAC_SHHR_THOLD1 DAC_SHHR_THOLD1_Msk /*!<DAC channel1 hold time */ 242 #define DAC_SHHR_THOLD2_Pos (16U) 243 #define DAC_SHHR_THOLD2_Msk (0x3FFUL << DAC_SHHR_THOLD2_Pos) /*!< 0x03FF0000 */ 244 #define DAC_SHHR_THOLD2 DAC_SHHR_THOLD2_Msk /*!<DAC channel2 hold time */ 245 246 /****************** Bit definition for DAC_SHRR register ******************/ 247 #define DAC_SHRR_TREFRESH1_Pos (0U) 248 #define DAC_SHRR_TREFRESH1_Msk (0xFFUL << DAC_SHRR_TREFRESH1_Pos) /*!< 0x000000FF */ 249 #define DAC_SHRR_TREFRESH1 DAC_SHRR_TREFRESH1_Msk /*!<DAC channel1 refresh time */ 250 #define DAC_SHRR_TREFRESH2_Pos (16U) 251 #define DAC_SHRR_TREFRESH2_Msk (0xFFUL << DAC_SHRR_TREFRESH2_Pos) /*!< 0x00FF0000 */ 252 #define DAC_SHRR_TREFRESH2 DAC_SHRR_TREFRESH2_Msk /*!<DAC channel2 refresh time */ 253 /** 254 * @brief DAC Configuration sample and hold Channel structure definition 255 */ 256 typedef struct 257 { 258 uint32_t DAC_SampleTime ; /*!< Specifies the Sample time for the selected channel. 259 This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE. 260 This parameter must be a number between Min_Data = 0 and Max_Data = 1023 */ 261 262 uint32_t DAC_HoldTime ; /*!< Specifies the hold time for the selected channel 263 This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE. 264 This parameter must be a number between Min_Data = 0 and Max_Data = 1023 */ 265 266 uint32_t DAC_RefreshTime ; /*!< Specifies the refresh time for the selected channel 267 This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE. 268 This parameter must be a number between Min_Data = 0 and Max_Data = 255 */ 269 } 270 DAC_SampleAndHoldConfTypeDef; 271 272 typedef struct 273 { 274 uint32_t DAC_Calibration ; /*!< Specifies the Sample time for the selected channel. 275 This parameter can be a value of @ref DAC_Calibration */ 276 277 uint32_t DAC_Calibration_TRIM ; /*!< Specifies the hold time for the selected channel 278 This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE. 279 This parameter must be a number between Min_Data = 0 and Max_Data = 1023 */ 280 } 281 DAC_CalibrationConfTypeDef; 282 283 /** 284 * @brief DAC Configuration regular Channel structure definition 285 */ 286 typedef struct 287 { 288 uint32_t DAC_SampleAndHold; /*!< Specifies whether the DAC mode. 289 This parameter can be a value of @ref DAC_SampleAndHold */ 290 291 uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel. 292 This parameter can be a value of @ref DAC_trigger_selection */ 293 294 uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled. 295 This parameter can be a value of @ref DAC_output_buffer */ 296 297 298 uint32_t DAC_ConnectOnChipPeripheral ; /*!< Specifies whether the DAC output is connected or not to on chip peripheral . 299 This parameter can be a value of @ref DAC_ConnectOnChipPeripheral */ 300 301 uint32_t DAC_UserTrimming; /*!< Specifies the trimming mode 302 This parameter must be a value of @ref DAC_UserTrimming 303 DAC_UserTrimming is either factory or user trimming */ 304 305 uint32_t DAC_TrimmingValue; /*!< Specifies the offset trimming value 306 i.e. when DAC_SampleAndHold is DAC_TRIMMING_USER. 307 This parameter must be a number between Min_Data = 1 and Max_Data = 31 */ 308 309 DAC_SampleAndHoldConfTypeDef DAC_SampleAndHoldConfig; /*!< Sample and Hold settings */ 310 311 } DAC_ChannelConfTypeDef; 312 313 /** 314 * @brief CAN handle Structure definition 315 */ 316 typedef struct 317 { 318 DAC_TypeDef *Instance; /*!< Register base address */ 319 320 DMA_HandleTypeDef *DMA_Handle1; /*!< Pointer DMA handler for channel 1 */ 321 322 DMA_HandleTypeDef *DMA_Handle2; /*!< Pointer DMA handler for channel 2 */ 323 324 325 } DAC_HandleTypeDef; 326 327 328 #define IS_DAC_ALL_PERIPH(PERIPH) (((PERIPH) == DAC)) 329 330 331 332 /** @defgroup DAC_SampleAndHold DAC power mode 333 * @{ 334 */ 335 #define IS_DAC_SAMPLETIME(TIME) ((TIME) <= 0x000003FFU) 336 #define IS_DAC_HOLDTIME(TIME) ((TIME) <= 0x000003FFU) 337 #define IS_DAC_REFRESHTIME(TIME) ((TIME) <= 0x000000FFU) 338 339 340 /** @defgroup DAC_CHANNEL 341 * @{ 342 */ 343 344 #define DAC_CHANNEL_1 0x00000000U 345 #define DAC_CHANNEL_2 0x00000010U 346 #define DAC_CHANNEL_Dual 0x00000020U 347 #define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \ 348 ((CHANNEL) == DAC_CHANNEL_2) || \ 349 ((CHANNEL) == DAC_CHANNEL_Dual)) 350 /** 351 * @} 352 */ 353 354 /** @defgroup DAC_trigger 355 * @{ 356 */ 357 #define DAC_TRIGGER_T6_TRGO (0x00000000U| DAC_CR_TEN1) 358 #define DAC_TRIGGER_T3_TRGO ( DAC_CR_TSEL1_0| DAC_CR_TEN1) 359 #define DAC_TRIGGER_T7_TRGO ( DAC_CR_TSEL1_1| DAC_CR_TEN1 ) 360 #define DAC_TRIGGER_T15_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0| DAC_CR_TEN1) 361 #define DAC_TRIGGER_T2_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TEN1) 362 #define DAC_TRIGGER_T1_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0| DAC_CR_TEN1) 363 #define DAC_TRIGGER_EXT_IT9 ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1| DAC_CR_TEN1 ) 364 #define DAC_TRIGGER_SOFTWARE ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0| DAC_CR_TEN1) 365 #define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \ 366 ((TRIGGER) == DAC_TRIGGER_T3_TRGO) || \ 367 ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \ 368 ((TRIGGER) == DAC_TRIGGER_T15_TRGO) || \ 369 ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \ 370 ((TRIGGER) == DAC_TRIGGER_T1_TRGO) || \ 371 ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \ 372 ((TRIGGER) == DAC_TRIGGER_SOFTWARE)) 373 /** 374 * @} 375 */ 376 377 /** @defgroup DAC_wave_generation 378 * @{ 379 */ 380 381 #define DAC_WaveGeneration_None 0x00000000U 382 #define DAC_WaveGeneration_Noise 0x00000001U 383 #define DAC_WaveGeneration_Triangle 0x00000002U 384 #define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || \ 385 ((WAVE) == DAC_WaveGeneration_Noise) || \ 386 ((WAVE) == DAC_WaveGeneration_Triangle)) 387 /** 388 * @} 389 */ 390 /** @defgroup DAC_lfsrunmask_triangleamplitude 391 * @{ 392 */ 393 #define DAC_LFSRUNMASK_BIT0 0x00000000U /*!< Unmask DAC channel LFSR bit0 for noise wave generation */ 394 #define DAC_LFSRUNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */ 395 #define DAC_LFSRUNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */ 396 #define DAC_LFSRUNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */ 397 #define DAC_LFSRUNMASK_BITS4_0 ( DAC_CR_MAMP1_2 ) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */ 398 #define DAC_LFSRUNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */ 399 #define DAC_LFSRUNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */ 400 #define DAC_LFSRUNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */ 401 #define DAC_LFSRUNMASK_BITS8_0 (DAC_CR_MAMP1_3 ) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */ 402 #define DAC_LFSRUNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */ 403 #define DAC_LFSRUNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */ 404 #define DAC_LFSRUNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */ 405 #define DAC_TRIANGLEAMPLITUDE_1 0x00000000U /*!< Select max triangle amplitude of 1 */ 406 #define DAC_TRIANGLEAMPLITUDE_3 ( DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 3 */ 407 #define DAC_TRIANGLEAMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /*!< Select max triangle amplitude of 7 */ 408 #define DAC_TRIANGLEAMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 15 */ 409 #define DAC_TRIANGLEAMPLITUDE_31 ( DAC_CR_MAMP1_2 ) /*!< Select max triangle amplitude of 31 */ 410 #define DAC_TRIANGLEAMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 63 */ 411 #define DAC_TRIANGLEAMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Select max triangle amplitude of 127 */ 412 #define DAC_TRIANGLEAMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 255 */ 413 #define DAC_TRIANGLEAMPLITUDE_511 (DAC_CR_MAMP1_3 ) /*!< Select max triangle amplitude of 511 */ 414 #define DAC_TRIANGLEAMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 1023 */ 415 #define DAC_TRIANGLEAMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Select max triangle amplitude of 2047 */ 416 #define DAC_TRIANGLEAMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 4095 */ 417 418 #define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUNMASK_BIT0) || \ 419 ((VALUE) == DAC_LFSRUNMASK_BITS1_0) || \ 420 ((VALUE) == DAC_LFSRUNMASK_BITS2_0) || \ 421 ((VALUE) == DAC_LFSRUNMASK_BITS3_0) || \ 422 ((VALUE) == DAC_LFSRUNMASK_BITS4_0) || \ 423 ((VALUE) == DAC_LFSRUNMASK_BITS5_0) || \ 424 ((VALUE) == DAC_LFSRUNMASK_BITS6_0) || \ 425 ((VALUE) == DAC_LFSRUNMASK_BITS7_0) || \ 426 ((VALUE) == DAC_LFSRUNMASK_BITS8_0) || \ 427 ((VALUE) == DAC_LFSRUNMASK_BITS9_0) || \ 428 ((VALUE) == DAC_LFSRUNMASK_BITS10_0) || \ 429 ((VALUE) == DAC_LFSRUNMASK_BITS11_0) || \ 430 ((VALUE) == DAC_TRIANGLEAMPLITUDE_1) || \ 431 ((VALUE) == DAC_TRIANGLEAMPLITUDE_3) || \ 432 ((VALUE) == DAC_TRIANGLEAMPLITUDE_7) || \ 433 ((VALUE) == DAC_TRIANGLEAMPLITUDE_15) || \ 434 ((VALUE) == DAC_TRIANGLEAMPLITUDE_31) || \ 435 ((VALUE) == DAC_TRIANGLEAMPLITUDE_63) || \ 436 ((VALUE) == DAC_TRIANGLEAMPLITUDE_127) || \ 437 ((VALUE) == DAC_TRIANGLEAMPLITUDE_255) || \ 438 ((VALUE) == DAC_TRIANGLEAMPLITUDE_511) || \ 439 ((VALUE) == DAC_TRIANGLEAMPLITUDE_1023) || \ 440 ((VALUE) == DAC_TRIANGLEAMPLITUDE_2047) || \ 441 ((VALUE) == DAC_TRIANGLEAMPLITUDE_4095)) 442 /** 443 * @} 444 */ 445 446 /** @defgroup DAC_MODE 447 * @{ 448 */ 449 450 #define DAC_Mode_Normal_BufferEnable_OutPAD 0x00000000U 451 #define DAC_Mode_Normal_BufferEnable_OutPAD_OutInternal 0x00000001U 452 #define DAC_Mode_Normal_BufferDisable_OutPAD 0x00000002U 453 #define DAC_Mode_Normal_BufferDisable_OutPAD_OutInternal 0x00000003U 454 455 #define DAC_Mode_SampleAndHold_BufferEnable_OutPAD 0x00000004U 456 #define DAC_Mode_SampleAndHold_BufferEnable_OutPAD_OutInternal 0x00000005U 457 #define DAC_Mode_SampleAndHold_BufferDisable_OutPAD_OutInternal 0x00000006U 458 #define DAC_Mode_SampleAndHold_BufferDisable_OutInternal 0x00000007U 459 #define IS_DAC_MODE(MODE) (((MODE) == DAC_Mode_Normal_BufferEnable_OutPAD) || \ 460 ((MODE) == DAC_Mode_Normal_BufferEnable_OutPAD_OutInternal) || \ 461 ((MODE) == DAC_Mode_Normal_BufferDisable_OutPAD)|| \ 462 ((MODE) == DAC_Mode_Normal_BufferDisable_OutPAD_OutInternal)|| \ 463 ((MODE) == DAC_Mode_SampleAndHold_BufferEnable_OutPAD)|| \ 464 ((MODE) == DAC_Mode_SampleAndHold_BufferEnable_OutPAD_OutInternal)|| \ 465 ((MODE) == DAC_Mode_SampleAndHold_BufferDisable_OutPAD_OutInternal)|| \ 466 ((MODE) == DAC_Mode_SampleAndHold_BufferDisable_OutInternal)) 467 /** 468 * @} 469 */ 470 471 /** @defgroup DAC_SampleAndHold DAC power mode 472 * @{ 473 */ 474 #define DAC_SAMPLEANDHOLD_DISABLE 0x00000000U 475 #define DAC_SAMPLEANDHOLD_ENABLE (DAC_MCR_MODE1_2) 476 #define IS_DAC_SAMPLEANDHOLD(MODE) (((MODE) == DAC_SAMPLEANDHOLD_DISABLE) || \ 477 ((MODE) == DAC_SAMPLEANDHOLD_ENABLE)) 478 /** 479 * @} 480 */ 481 482 483 /** @defgroup DAC_UserTrimming DAC User Trimming 484 * @{ 485 */ 486 487 #define DAC_TRIMMING_FACTORY 0x00000000U /*!< Factory trimming */ 488 #define DAC_TRIMMING_USER 0x00000001U /*!< User trimming */ 489 #define IS_DAC_TRIMMING(TRIMMING) (((TRIMMING) == DAC_TRIMMING_FACTORY) || \ 490 ((TRIMMING) == DAC_TRIMMING_USER)) 491 #define IS_DAC_TRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1FU) 492 /** 493 * @} 494 */ 495 496 /** @defgroup DAC_Calibration 497 * @{ 498 */ 499 500 #define DAC_Calibration_Disable 0x00000000U 501 #define DAC_Calibration_Enable 0x00000001U 502 #define IS_DAC_Calibration(Calibration) (((Calibration) == DAC_Calibration_Disable) || \ 503 ((Calibration) == DAC_Calibration_Enable)) 504 505 #define IS_DAC_Calibration_TRIM(TRIM) ((TRIM) <= 0x1FU) 506 /** 507 * @} 508 */ 509 /** @defgroup DAC_output_buffer DAC output buffer 510 * @{ 511 */ 512 #define DAC_OUTPUTBUFFER_ENABLE 0x00000000U 513 #define DAC_OUTPUTBUFFER_DISABLE (DAC_MCR_MODE1_1) 514 #define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \ 515 ((STATE) == DAC_OUTPUTBUFFER_DISABLE)) 516 /** 517 * @} 518 */ 519 /** @defgroup DAC_ConnectOnChipPeripheral DAC ConnectOnChipPeripheral 520 * @{ 521 */ 522 #define DAC_CHIPCONNECT_DISABLE 0x00000000U 523 #define DAC_CHIPCONNECT_ENABLE (DAC_MCR_MODE1_0) 524 #define IS_DAC_CHIP_CONNECTION(CONNECT) (((CONNECT) == DAC_CHIPCONNECT_DISABLE) || \ 525 ((CONNECT) == DAC_CHIPCONNECT_ENABLE)) 526 /** 527 * @} 528 */ 529 530 531 /** @defgroup DAC_data_alignment DAC data alignment 532 * @{ 533 */ 534 535 #define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (0x00000008U + (__ALIGNMENT__)) 536 #define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (0x00000014U + (__ALIGNMENT__)) 537 538 539 540 #define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (0x00000020U + (__ALIGNMENT__)) 541 542 #define DAC_ALIGN_12B_R 0x00000000U 543 #define DAC_ALIGN_12B_L 0x00000004U 544 #define DAC_ALIGN_8B_R 0x00000008U 545 #define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \ 546 ((ALIGN) == DAC_ALIGN_12B_L) || \ 547 ((ALIGN) == DAC_ALIGN_8B_R)) 548 /** 549 * @} 550 */ 551 552 553 554 555 /* Initialization/de-initialization functions *********************************/ 556 void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac); 557 558 void HAL_DAC_MspInit(DAC_HandleTypeDef *hdac); 559 void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac); 560 561 HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef *hdac); 562 HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac); 563 564 HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel); 565 566 /* I/O operation functions ****************************************************/ 567 HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel); 568 HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel); 569 570 HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length, uint32_t Alignment); 571 HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel); 572 573 /* Peripheral Control functions ***********************************************/ 574 HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data); 575 HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef *hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2); 576 577 uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel); 578 uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef *hdac); 579 580 HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude); 581 HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude) ; 582 583 584 HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel); 585 HAL_StatusTypeDef HAL_DACEx_SetUserTrimming(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel, uint32_t NewTrimmingValue); 586 uint32_t HAL_DACEx_GetTrimOffset(DAC_HandleTypeDef *hdac, uint32_t Channel); 587 588 589 #endif