1 /* 2 ****************************************************************************** 3 * @file HAL_DMA.h 4 * @version V1.0.0 5 * @date 2020 6 * @brief Header file of DMA HAL module. 7 ****************************************************************************** 8 */ 9 #ifndef __HAL_DMA_H__ 10 #define __HAL_DMA_H__ 11 12 #include "ACM32Fxx_HAL.h" 13 14 #define DMA_CHANNEL_NUM (8) 15 16 /******************************************************************************/ 17 /* Peripheral Registers Bits Definition */ 18 /******************************************************************************/ 19 20 /**************** Bit definition for DMA CONFIG register ***********************/ 21 #define DMA_CONFIG_M2ENDIAN BIT2 22 #define DMA_CONFIG_M1ENDIAN BIT1 23 #define DMA_CONFIG_EN BIT0 24 25 /**************** Bit definition for DMA Channel CTRL register ***********************/ 26 #define DMA_CHANNEL_CTRL_ITC BIT31 27 #define DMA_CHANNEL_CTRL_DI BIT27 28 #define DMA_CHANNEL_CTRL_SI BIT26 29 30 31 /**************** Bit definition for DMA Channel CONFIG register ***********************/ 32 #define DMA_CHANNEL_CONFIG_DEST_PERIPH (BIT19|BIT20|BIT21|BIT22|BIT23|BIT24) 33 #define DMA_CHANNEL_CONFIG_DEST_PERIPH_POS (19) 34 #define DMA_CHANNEL_CONFIG_HALT BIT18 35 #define DMA_CHANNEL_CONFIG_ACTIVE BIT17 36 #define DMA_CHANNEL_CONFIG_LOCK BIT16 37 #define DMA_CHANNEL_CONFIG_ITC BIT15 38 #define DMA_CHANNEL_CONFIG_IE BIT14 39 #define DMA_CHANNEL_CONFIG_FLOW_CTRL (BIT11|BIT12|BIT13) 40 #define DMA_CHANNEL_CONFIG_SRC_PERIPH (BIT1|BIT2|BIT3|BIT4|BIT5|BIT6) 41 #define DMA_CHANNEL_CONFIG_SRC_PERIPH_POS (1) 42 #define DMA_CHANNEL_CONFIG_EN BIT0 43 44 /** @defgroup DMA_DATA_FLOW 45 * @{ 46 */ 47 #define DMA_DATA_FLOW_M2M (0x00000000) 48 #define DMA_DATA_FLOW_M2P (0x00000800) 49 #define DMA_DATA_FLOW_P2M (0x00001000) 50 /** 51 * @} 52 */ 53 54 55 /** @defgroup REQUEST_ID 56 * @{ 57 */ 58 #define REG_M2M (0) 59 60 #define REQ0_ADC (0) 61 #define REQ1_SPI1_SEND (1) 62 #define REQ2_SPI1_RECV (2) 63 #define REQ3_SPI2_SEND (3) 64 #define REQ4_SPI2_RECV (4) 65 #define REQ5_UART1_SEND (5) 66 #define REQ6_UART1_RECV (6) 67 #define REQ7_UART2_SEND (7) 68 #define REQ8_UART2_RECV (8) 69 #define REQ9_I2C1_SEND (9) 70 #define REQ10_I2C1_RECV (10) 71 #define REQ11_I2C2_SEND (11) 72 #define REQ12_I2C2_RECV (12) 73 #define REQ13_TIM1_CH1 (13) 74 #define REQ14_TIM1_CH2 (14) 75 #define REQ15_TIM1_CH3 (15) 76 #define REQ16_TIM1_CH4 (16) 77 #define REQ17_TIM1_UP (17) 78 #define REQ18_TIM1_TRIG_COM (18) 79 #define REQ19_TIM3_CH3 (19) 80 #define REQ20_TIM3_CH4_OR_UP (20) 81 #define REQ21_TIM3_CH1_OR_TRIG (21) 82 #define REQ22_TIM3_CH2 (22) 83 #define REQ23_TIM6_UP (23) 84 #define REQ24_TIM15_CH1_UP_TRIG_COM (24) 85 #define REQ25_TIM15_CH2 (25) 86 #define REQ26_TIM16_CH1_UP (26) 87 #define REQ27_TIM16_TRIG_COM (27) 88 #define REQ27_UART3_SEND (27) 89 #define REQ28_TIM17_CH1_UP (28) 90 #define REQ29_TIM17_TRIG_COM (29) 91 #define REQ29_UART3_RECV (29) 92 #define REQ30_LPUART_SEND (30) 93 #define REQ31_LPUART_RECV (31) 94 #define REQ32_TIM2_CH3 (32) 95 #define REQ33_TIM2_CH4 (33) 96 #define REQ34_TIM2_CH1 (34) 97 #define REQ35_TIM2_CH2 (35) 98 #define REQ36_TIM7_UP (36) 99 #define REQ37_I2S1_TX (37) 100 #define REQ38_I2S1_RX (38) 101 #define REQ39_DAC1_CH1 (39) 102 #define REQ40_DAC1_CH2 (40) 103 #define REQ41_TIM4_CH3 (41) 104 #define REQ42_TIM4_CH4 (42) 105 #define REQ43_TIM4_CH1 (43) 106 #define REQ44_TIM4_CH2 (44) 107 #define REQ45_UART4_SEND (45) 108 #define REQ46_UART4_RECV (46) 109 #define REQ47_SPI3_SEND (47) 110 #define REQ48_SPI3_RECV (48) 111 #define REQ49_SPI4_SEND (49) 112 #define REQ50_SPI4_RECV (50) 113 114 #define REQ_MAX_LIMIT (51) 115 /** 116 * @} 117 */ 118 119 120 /** @defgroup DMA_SOURCE_ADDR_INCREASE 121 * @{ 122 */ 123 #define DMA_SOURCE_ADDR_INCREASE_DISABLE (0x00000000) 124 #define DMA_SOURCE_ADDR_INCREASE_ENABLE (0x04000000) 125 /** 126 * @} 127 */ 128 129 130 /** @defgroup DMA_DST_ADDR_INCREASE 131 * @{ 132 */ 133 #define DMA_DST_ADDR_INCREASE_DISABLE (0x00000000) 134 #define DMA_DST_ADDR_INCREASE_ENABLE (0x08000000) 135 /** 136 * @} 137 */ 138 139 140 /** @defgroup DMA_SRC_WIDTH 141 * @{ 142 */ 143 #define DMA_SRC_WIDTH_BYTE (0x00000000) /* 8bit */ 144 #define DMA_SRC_WIDTH_HALF_WORD (0x00040000) /* 16bit */ 145 #define DMA_SRC_WIDTH_WORD (0x00080000) /* 36bit */ 146 /** 147 * @} 148 */ 149 150 /** @defgroup DMA_DST_WIDTH 151 * @{ 152 */ 153 #define DMA_DST_WIDTH_BYTE (0x00000000) /* 8bit */ 154 #define DMA_DST_WIDTH_HALF_WORD (0x00200000) /* 16bit */ 155 #define DMA_DST_WIDTH_WORD (0x00400000) /* 36bit */ 156 /** 157 * @} 158 */ 159 160 /** @defgroup DMA_MODE DMA MODE 161 * @{ 162 */ 163 #define DMA_NORMAL 0x00000000U /*!< Normal mode */ 164 #define DMA_CIRCULAR 0x00000001U /*!< Circular mode */ 165 /** 166 * @} 167 */ 168 169 /** 170 * @brief DMA burst length Structure definition 171 */ 172 typedef enum 173 { 174 DMA_BURST_LENGTH_1 = 0, 175 DMA_BURST_LENGTH_4 = 1, 176 DMA_BURST_LENGTH_8 = 2, 177 DMA_BURST_LENGTH_16 = 3, 178 DMA_BURST_LENGTH_32 = 4, 179 DMA_BURST_LENGTH_64 = 5, 180 DMA_BURST_LENGTH_128 = 6, 181 DMA_BURST_LENGTH_256 = 7, 182 }DMA_BURST_LENGTH; 183 184 185 /** 186 * @brief DMA Configuration Structure definition 187 */ 188 typedef struct 189 { 190 uint32_t Mode; /* This parameter can be a value of @ref DMA_MODE */ 191 192 uint32_t Data_Flow; /* This parameter can be a value of @ref DMA_DATA_FLOW */ 193 194 uint32_t Request_ID; /* This parameter can be a value of @ref REQUEST_ID */ 195 196 uint32_t Source_Inc; /* This parameter can be a value of @ref DMA_SOURCE_ADDR_INCREASE */ 197 198 uint32_t Desination_Inc; /* This parameter can be a value of @ref DMA_DST_ADDR_INCREASE */ 199 200 uint32_t Source_Width; /* This parameter can be a value of @ref DMA_SRC_WIDTH */ 201 202 uint32_t Desination_Width; /* This parameter can be a value of @ref DMA_DST_WIDTH */ 203 204 }DMA_InitParaTypeDef; 205 206 207 /** 208 * @brief DMA handle Structure definition 209 */ 210 typedef struct 211 { 212 DMA_Channel_TypeDef *Instance; /* DMA registers base address */ 213 214 DMA_InitParaTypeDef Init; /* DMA initialization parameters */ 215 216 void (*DMA_ITC_Callback)(void); /* DMA transfer complete callback */ 217 218 void (*DMA_IE_Callback)(void); /* DMA error complete callback */ 219 220 }DMA_HandleTypeDef; 221 222 /** 223 * @brief DMA Link List Item Structure 224 */ 225 typedef struct DMA_NextLink 226 { 227 uint32_t SrcAddr; /* source address */ 228 229 uint32_t DstAddr; /* desination address */ 230 231 struct DMA_NextLink *Next; /* Next Link */ 232 233 uint32_t Control; /* Control */ 234 235 }DMA_LLI_InitTypeDef; 236 237 238 /** @defgroup GPIO Private Macros 239 * @{ 240 */ 241 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ 242 ((MODE) == DMA_CIRCULAR)) 243 244 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA_Channel0) || \ 245 ((INSTANCE) == DMA_Channel1) || \ 246 ((INSTANCE) == DMA_Channel2) || \ 247 ((INSTANCE) == DMA_Channel3) || \ 248 ((INSTANCE) == DMA_Channel4) || \ 249 ((INSTANCE) == DMA_Channel5) || \ 250 ((INSTANCE) == DMA_Channel6) || \ 251 ((INSTANCE) == DMA_Channel7)) 252 253 #define IS_DMA_DATA_FLOW(DATA_FLOW) (((DATA_FLOW) == DMA_DATA_FLOW_M2M) || \ 254 ((DATA_FLOW) == DMA_DATA_FLOW_M2P) || \ 255 ((DATA_FLOW) == DMA_DATA_FLOW_P2M)) 256 257 #define IS_DMA_REQUEST_ID(REQUEST_ID) ((REQUEST_ID < REQ_MAX_LIMIT) ? true : false) 258 259 #define IS_DMA_SRC_WIDTH(WIDTH) (((WIDTH) == DMA_SRC_WIDTH_BYTE) || \ 260 ((WIDTH) == DMA_SRC_WIDTH_HALF_WORD) || \ 261 ((WIDTH) == DMA_SRC_WIDTH_WORD)) 262 263 #define IS_DMA_DST_WIDTH(WIDTH) (((WIDTH) == DMA_DST_WIDTH_BYTE) || \ 264 ((WIDTH) == DMA_DST_WIDTH_HALF_WORD) || \ 265 ((WIDTH) == DMA_DST_WIDTH_WORD)) 266 267 /** 268 * @} 269 */ 270 271 272 /* Exported functions --------------------------------------------------------*/ 273 274 #define __HAL_LINK_DMA(_HANDLE_, _DMA_LINK_, _DMA_HANDLE_) (_HANDLE_._DMA_LINK_ = &_DMA_HANDLE_) 275 276 /* HAL_DMA_IRQHandler */ 277 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); 278 279 /* HAL_DMA_Init */ 280 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); 281 282 /* HAL_DMA_DeInit */ 283 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma); 284 285 /* HAL_DMA_Start */ 286 HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t fu32_SrcAddr, uint32_t fu32_DstAddr, uint32_t fu32_Size); 287 288 /* HAL_DMA_Start */ 289 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t fu32_SrcAddr, uint32_t fu32_DstAddr, uint32_t fu32_Size); 290 291 /* HAL_DMA_Abort */ 292 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); 293 294 /* HAL_DMA_GetState */ 295 HAL_StatusTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); 296 297 #endif 298