1 /* 2 ****************************************************************************** 3 * @file HAL_I2S.h 4 * @version V1.0.0 5 * @date 2020 6 * @brief Header file of I2S HAL module. 7 ****************************************************************************** 8 */ 9 10 #ifndef __HAL_I2S_H__ 11 #define __HAL_I2S_H__ 12 13 #include "ACM32Fxx_HAL.h" 14 15 /************************************************************************************/ 16 /* Registers Bits Definition */ 17 /************************************************************************************/ 18 19 /**************** Bit definition for I2S CTL Register ***********************/ 20 #define I2S_CTL_I2SEN (BIT10) 21 #define I2S_CTL_I2SOPMOD (BIT9|BIT8) 22 #define I2S_CTL_PCMSMOD (BIT7) 23 #define I2S_CTL_I2SSTD (BIT5|BIT4) 24 #define I2S_CTL_CKPL (BIT3) 25 #define I2S_CTL_DTLEN (BIT2|BIT1) 26 #define I2S_CTL_CHLEN (BIT0) 27 28 /**************** Bit definition for I2S PSC Register ***********************/ 29 #define I2S_PSC_MCKOEN (BIT10) 30 #define I2S_PSC_OF (BIT9) 31 #define I2S_PSC_DIV (0x1FF) 32 33 /**************** Bit definition for I2S DIE Register ***********************/ 34 #define I2S_DIE_TBEIE (BIT7) 35 #define I2S_DIE_RBNEIE (BIT6) 36 #define I2S_DIE_ERRIE (BIT5) 37 #define I2S_DIE_DMATEN (BIT1) 38 #define I2S_DIE_DMAREN (BIT0) 39 40 /**************** Bit definition for I2S STATUS Register ***********************/ 41 #define I2S_STATUS_FERR (BIT8) 42 #define I2S_STATUS_TRANS (BIT7) 43 #define I2S_STATUS_RXORERR (BIT6) 44 #define I2S_STATUS_TXURERR (BIT3) 45 #define I2S_STATUS_I2SCH (BIT2) 46 #define I2S_STATUS_TXBE (BIT1) 47 #define I2S_STATUS_RXBNE (BIT0) 48 49 50 51 /** @defgroup I2S_Mode I2S Mode 52 * @{ 53 */ 54 #define I2S_MODE_SLAVE_TX (0x00000000) 55 #define I2S_MODE_SLAVE_RX (0x00000100) 56 #define I2S_MODE_MASTER_TX (0x00000200) 57 #define I2S_MODE_MASTER_RX (I2S_CTL_I2SOPMOD) 58 /** 59 * @} 60 */ 61 62 63 /** @defgroup I2S_Standard I2S Standard 64 * @{ 65 */ 66 #define I2S_STANDARD_PHILIPS (0x00000000U) 67 #define I2S_STANDARD_MSB (0x00000010U) 68 #define I2S_STANDARD_LSB (0x00000020U) 69 #define I2S_STANDARD_PCM_SHORT (I2S_CTL_I2SSTD) 70 #define I2S_STANDARD_PCM_LONG (I2S_CTL_I2SSTD | I2S_CTL_PCMSMOD) 71 /** 72 * @} 73 */ 74 75 76 /** @defgroup I2S_Data_Format I2S Data Format 77 * @{ 78 */ 79 #define I2S_DATAFORMAT_16B (0x00000000U) 80 #define I2S_DATAFORMAT_16B_EXTENDED (I2S_CTL_CHLEN) 81 #define I2S_DATAFORMAT_24B (I2S_CTL_CHLEN | 0x02) 82 #define I2S_DATAFORMAT_32B (I2S_CTL_CHLEN | 0x04) 83 /** 84 * @} 85 */ 86 87 88 /** @defgroup I2S_MCLK_Output I2S MCLK Output 89 * @{ 90 */ 91 #define I2S_MCLKOUTPUT_ENABLE (I2S_PSC_MCKOEN) 92 #define I2S_MCLKOUTPUT_DISABLE (0x00000000U) 93 /** 94 * @} 95 */ 96 97 98 /** @defgroup I2S_Clock_Polarity I2S Clock Polarity 99 * @{ 100 */ 101 #define I2S_CPOL_LOW (0x00000000U) 102 #define I2S_CPOL_HIGH (I2S_CTL_CKPL) 103 /** 104 * @} 105 */ 106 107 108 /** @defgroup I2S_Audio_FrequencyOF I2S Clock Frequency OF 109 * @{ 110 */ 111 #define I2S_FREQ_OF_DISABLE (0x00000000U) 112 #define I2S_FREQ_OF_ENABLE (I2S_PSC_OF) 113 /** 114 * @} 115 */ 116 117 /** 118 * @brief HAL State structures definition 119 */ 120 typedef enum 121 { 122 HAL_I2S_STATE_RESET = 0x00U, /*!< I2S not yet initialized or disabled */ 123 HAL_I2S_STATE_READY = 0x01U, /*!< I2S initialized and ready for use */ 124 HAL_I2S_STATE_BUSY = 0x02U, /*!< I2S internal process is ongoing */ 125 HAL_I2S_STATE_BUSY_TX = 0x03U, /*!< Data Transmission process is ongoing */ 126 HAL_I2S_STATE_BUSY_RX = 0x04U, /*!< Data Reception process is ongoing */ 127 HAL_I2S_STATE_TIMEOUT = 0x06U, /*!< I2S timeout state */ 128 HAL_I2S_STATE_ERROR = 0x07U /*!< I2S error state */ 129 }enum_I2S_State; 130 131 132 /** 133 * @brief I2S Init structure definition 134 */ 135 typedef struct 136 { 137 uint32_t u32_Mode; /*!< Specifies the I2S operating mode. 138 This parameter can be a value of @ref I2S_Mode */ 139 140 uint32_t u32_Standard; /*!< Specifies the standard used for the I2S communication. 141 This parameter can be a value of @ref I2S_Standard */ 142 143 uint32_t u32_DataFormat; /*!< Specifies the data format for the I2S communication. 144 This parameter can be a value of @ref I2S_Data_Format */ 145 146 uint32_t u32_MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not. 147 This parameter can be a value of @ref I2S_MCLK_Output */ 148 149 uint32_t u32_CPOL; /*!< Specifies the idle state of the I2S clock. 150 This parameter can be a value of @ref I2S_Clock_Polarity */ 151 152 uint32_t u32_FreqOF; /*!< Specifies the frequency selected for the I2S communication. 153 This parameter can be a value of @ref I2S_Audio_FrequencyFO */ 154 155 uint32_t u32_FreqDIV; /*!< Specifies the frequency selected for the I2S communication. 156 This parameter must be a number between Min_Data = 0x001 and Max_Data = 0x1FF */ 157 }I2S_InitTypeDef; 158 159 160 161 /** 162 * @brief I2S handle Structure definition 163 */ 164 typedef struct 165 { 166 I2S_TypeDef *Instance; /*!< I2S registers base address */ 167 168 I2S_InitTypeDef Init; /*!< I2S communication parameters */ 169 170 enum_I2S_State I2S_Status; 171 172 uint32_t *u32_Rx_Buffer; /* I2S Rx Buffer */ 173 uint32_t *u32_Tx_Buffer; /* I2S Tx Buffer */ 174 175 uint32_t u32_Rx_Size; /* I2S Rx Size */ 176 uint32_t u32_Tx_Size; /* I2S Tx Size */ 177 178 uint32_t u32_Rx_Count; /* I2S RX Count */ 179 uint32_t u32_Tx_Count; /* I2S TX Count */ 180 181 DMA_HandleTypeDef *HDMA_Rx; /* SPI Rx DMA handle parameters */ 182 DMA_HandleTypeDef *HDMA_Tx; /* SPI Tx DMA handle parameters */ 183 184 }I2S_HandleTypeDef; 185 186 187 /** @defgroup RTC Private Macros 188 * @{ 189 */ 190 #define IS_I2S_MODE(__MODE__) (((__MODE__) == I2S_MODE_SLAVE_TX) || \ 191 ((__MODE__) == I2S_MODE_SLAVE_RX) || \ 192 ((__MODE__) == I2S_MODE_MASTER_TX) || \ 193 ((__MODE__) == I2S_MODE_MASTER_RX)) 194 195 #define IS_I2S_STANDARD(__STANDARD__) (((__STANDARD__) == I2S_STANDARD_PHILIPS) || \ 196 ((__STANDARD__) == I2S_STANDARD_MSB) || \ 197 ((__STANDARD__) == I2S_STANDARD_LSB) || \ 198 ((__STANDARD__) == I2S_STANDARD_PCM_SHORT) || \ 199 ((__STANDARD__) == I2S_STANDARD_PCM_LONG)) 200 201 #define IS_I2S_DATAFORMAT(__DATAFORMAT__) (((__DATAFORMAT__) == I2S_DATAFORMAT_16B) || \ 202 ((__DATAFORMAT__) == I2S_DATAFORMAT_16B_EXTENDED) || \ 203 ((__DATAFORMAT__) == I2S_DATAFORMAT_24B) || \ 204 ((__DATAFORMAT__) == I2S_DATAFORMAT_32B)) 205 206 #define IS_I2S_MCLK_OUTPUT(__MCLK_OUTPUT__) (((__MCLK_OUTPUT__) == I2S_MCLKOUTPUT_ENABLE) || \ 207 ((__MCLK_OUTPUT__) == I2S_MCLKOUTPUT_DISABLE)) 208 209 #define IS_I2S_MCLK_CPOL(__CPOL__) (((__CPOL__) == I2S_CPOL_LOW) || \ 210 ((__CPOL__) == I2S_CPOL_HIGH)) 211 212 #define IS_I2S_OF(__OF__) (((__OF__) == I2S_FREQ_OF_DISABLE) || \ 213 ((__OF__) == I2S_FREQ_OF_ENABLE)) 214 215 #define IS_I2S_DIV(__DIV__) ((__DIV__) >= 0x001 && (__DIV__) <= 0x1FF) 216 /** 217 * @} 218 */ 219 220 /* HAL_I2S_IRQHandler */ 221 void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s); 222 223 /* HAL_I2S_MspInit */ 224 void HAL_I2S_MspInit(I2S_HandleTypeDef *hspi); 225 226 /* HAL_I2S_Init */ 227 HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s); 228 229 /* HAL_I2S_Transmit */ 230 HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint32_t *fp32_Data, uint32_t fu32_Size, uint32_t fu32_Timeout); 231 232 /* HAL_I2S_Receive */ 233 HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint32_t *fp32_Data, uint32_t fu32_Size, uint32_t fu32_Timeout); 234 235 /* HAL_I2S_Transmit_IT */ 236 HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint32_t *fp32_Data, uint32_t fu32_Size); 237 238 /* HAL_I2S_Receive_IT */ 239 HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint32_t *fp32_Data, uint32_t fu32_Size); 240 241 /* HAL_I2S_Transmit_DMA */ 242 HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint32_t *fp32_Data, uint32_t fu32_Size); 243 244 /* HAL_I2S_Receive_DMA */ 245 HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint32_t *fp32_Data, uint32_t fu32_Size); 246 247 #endif 248 249