1 /* 2 ****************************************************************************** 3 * @file HAL_SPI.h 4 * @version V1.0.0 5 * @date 2020 6 * @brief Header file of SPI HAL module. 7 ****************************************************************************** 8 */ 9 #ifndef __HAL_SPI_H__ 10 #define __HAL_SPI_H__ 11 12 #include "ACM32Fxx_HAL.h" 13 14 /**************** Bit definition for SPI_CTL register **************************/ 15 #define SPI_CTL_CS_TIME (BIT11|BIT12|BIT13|BIT14|BIT15|BIT16|BIT17|BIT18) 16 #define SPI_CTL_CS_FILTER BIT10 17 #define SPI_CTL_CS_RST BIT9 18 #define SPI_CTL_SLAVE_EN BIT8 19 #define SPI_CTL_IO_MODE BIT7 20 #define SPI_CTL_X_MODE (BIT6|BIT5) 21 #define SPI_CTL_LSB_FIRST BIT4 22 #define SPI_CTL_CPOL BIT3 23 #define SPI_CTL_CPHA BIT2 24 #define SPI_CTL_SFILTER BIT1 25 #define SPI_CTL_MST_MODE BIT0 26 27 /**************** Bit definition for SPI_TX_CTL register ***********************/ 28 #define SPI_TX_CTL_DMA_LEVEL (BIT4|BIT5|BIT6|BIT7) 29 #define SPI_TX_CTL_DMA_LEVEL_3 BIT7 30 #define SPI_TX_CTL_DMA_LEVEL_2 BIT6 31 #define SPI_TX_CTL_DMA_LEVEL_1 BIT5 32 #define SPI_TX_CTL_DMA_LEVEL_0 BIT4 33 #define SPI_TX_CTL_DMA_REQ_EN BIT3 34 #define SPI_TX_CTL_MODE BIT2 35 #define SPI_TX_CTL_FIFO_RESET BIT1 36 #define SPI_TX_CTL_EN BIT0 37 38 /**************** Bit definition for SPI_RX_CTL register ***********************/ 39 #define SPI_RX_CTL_DMA_LEVEL (BIT4|BIT5|BIT6|BIT7) 40 #define SPI_RX_CTL_DMA_LEVEL_3 BIT7 41 #define SPI_RX_CTL_DMA_LEVEL_2 BIT6 42 #define SPI_RX_CTL_DMA_LEVEL_1 BIT5 43 #define SPI_RX_CTL_DMA_LEVEL_0 BIT4 44 #define SPI_RX_CTL_DMA_REQ_EN BIT3 45 #define SPI_RX_CTL_FIFO_RESET BIT1 46 #define SPI_RX_CTL_EN BIT0 47 48 /**************** Bit definition for SPI_IE register ***************************/ 49 #define SPI_IE_RX_BATCH_DONE_EN BIT15 50 #define SPI_IE_TX_BATCH_DONE_EN BIT14 51 #define SPI_IE_RX_FIFO_FULL_OV_EN BIT13 52 #define SPI_IE_RX_FIFO_EMPTY_OV_EN BIT12 53 #define SPI_IE_RX_NOT_EMPTY_EN BIT11 54 #define SPI_IE_CS_POS_EN BIT10 55 #define SPI_IE_RX_FIFO_HALF_FULL_EN BIT9 56 #define SPI_IE_RX_FIFO_HALF_EMPTY_EN BIT8 57 #define SPI_IE_TX_FIFO_HALF_FULL_EN BIT7 58 #define SPI_IE_TX_FIFO_HALF_EMPTY_EN BIT6 59 #define SPI_IE_RX_FIFO_FULL_EN BIT5 60 #define SPI_IE_RX_FIFO_EMPTY_EN BIT4 61 #define SPI_IE_TX_FIFO_FULL_EN BIT3 62 #define SPI_IE_TX_FIFO_EMPTY_EN BIT2 63 #define SPI_IE_BATCH_DONE_EN BIT1 64 65 /**************** Bit definition for SPI_STATUS register ***********************/ 66 #define SPI_STATUS_RX_BATCH_DONE BIT15 67 #define SPI_STATUS_TX_BATCH_DONE BIT14 68 #define SPI_STATUS_RX_FIFO_FULL_OV BIT13 69 #define SPI_STATUS_RX_FIFO_EMPTY_OV BIT12 70 #define SPI_STATUS_RX_NOT_EMPTY BIT11 71 #define SPI_STATUS_CS_POS BIT10 72 #define SPI_STATUS_RX_FIFO_HALF_FULL BIT9 73 #define SPI_STATUS_RX_FIFO_HALF_EMPTY BIT8 74 #define SPI_STATUS_TX_FIFO_HALF_FULL BIT7 75 #define SPI_STATUS_TX_FIFO_HALF_EMPTY BIT6 76 #define SPI_STATUS_RX_FIFO_FULL BIT5 77 #define SPI_STATUS_RX_FIFO_EMPTY BIT4 78 #define SPI_STATUS_TX_FIFO_FULL BIT3 79 #define SPI_STATUS_TX_FIFO_EMPTY BIT2 80 #define SPI_STATUS_BATCH_DONE BIT1 81 #define SPI_STATUS_TX_BUSY BIT0 82 83 /**************** Bit definition for SPI_CS register ***************************/ 84 #define SPI_CS_CSX BIT1 85 #define SPI_CS_CS0 BIT0 86 87 /**************** Bit definition for SPI_OUT_EN register ***********************/ 88 #define SPI_HOLD_EN BIT3 89 #define SPI_HOLD_WP_EN BIT2 90 #define SPI_HOLD_MISO_EN BIT1 91 #define SPI_HOLD_MOSI_EN BIT0 92 93 /**************** Bit definition for SPI_MEMO_ACC register ***********************/ 94 #define SPI_ADDR_WIDTH (BIT14|BIT15|BIT16|BIT17|BIT18) 95 #define SPI_PARA_NO2 (BIT9|BIT10|BIT11|BIT12|BIT13) 96 #define SPI_PARA_NO1 (BIT5|BIT6|BIT7|BIT8) 97 #define SPI_CON_RD_EN BIT3 98 #define SPI_PARA_ORD2 BIT2 99 #define SPI_PARA_ORD1 BIT1 100 #define SPI_ACC_EN BIT0 101 102 /** @defgroup SLAVE State machine 103 * @{ 104 */ 105 #define SPI_RX_STATE_IDLE (0U) 106 #define SPI_RX_STATE_RECEIVING (1U) 107 #define SPI_TX_STATE_IDLE (0U) 108 #define SPI_TX_STATE_SENDING (1U) 109 /** 110 * @} 111 */ 112 113 114 /** @defgroup SPI_MODE 115 * @{ 116 */ 117 #define SPI_MODE_SLAVE (0U) 118 #define SPI_MODE_MASTER (1U) 119 /** 120 * @} 121 */ 122 123 124 /** @defgroup SPI_WORK_MODE 125 * @{ 126 */ 127 #define SPI_WORK_MODE_0 (0x00000000) 128 #define SPI_WORK_MODE_1 (0x00000004) 129 #define SPI_WORK_MODE_2 (0x00000008) 130 #define SPI_WORK_MODE_3 (0x0000000C) 131 /** 132 * @} 133 */ 134 135 136 /** @defgroup SPI_CLOCK_PHASE SPI Clock Phase 137 * @{ 138 */ 139 #define SPI_PHASE_1EDGE (0U) 140 #define SPI_PHASE_2EDGE (1U) 141 /** 142 * @} 143 */ 144 145 146 /** @defgroup X_MODE SPI Clock Phase 147 * @{ 148 */ 149 #define SPI_1X_MODE (0x00000000) 150 #define SPI_2X_MODE (0x00000020) 151 #define SPI_4X_MODE (0x00000040) 152 /** 153 * @} 154 */ 155 156 157 /** @defgroup SPI_MSB_LSB_FIRST 158 * @{ 159 */ 160 #define SPI_FIRSTBIT_MSB (0U) 161 #define SPI_FIRSTBIT_LSB (1U) 162 /** 163 * @} 164 */ 165 166 167 /** @defgroup BAUDRATE_PRESCALER 168 * @{ 169 */ 170 #define SPI_BAUDRATE_PRESCALER_4 (4U) 171 #define SPI_BAUDRATE_PRESCALER_8 (8U) 172 #define SPI_BAUDRATE_PRESCALER_16 (16U) 173 #define SPI_BAUDRATE_PRESCALER_32 (32U) 174 #define SPI_BAUDRATE_PRESCALER_64 (64U) 175 #define SPI_BAUDRATE_PRESCALER_128 (128U) 176 #define SPI_BAUDRATE_PRESCALER_254 (254U) 177 /** 178 * @} 179 */ 180 181 182 /** 183 * @brief SPI Configuration Structure definition 184 */ 185 typedef struct 186 { 187 uint32_t SPI_Mode; /* This parameter can be a value of @ref SPI_MODE */ 188 189 uint32_t SPI_Work_Mode; /* This parameter can be a value of @ref SPI_WORK_MODE */ 190 191 uint32_t X_Mode; /* This parameter can be a value of @ref X_MODE */ 192 193 uint32_t First_Bit; /* This parameter can be a value of @ref SPI_MSB_LSB_FIRST */ 194 195 uint32_t BaudRate_Prescaler; /* This parameter can be a value of @ref BAUDRATE_PRESCALER */ 196 }SPI_InitTypeDef; 197 198 /******************************** Check SPI Parameter *******************************/ 199 #define IS_SPI_ALL_MODE(SPI_Mode) (((SPI_Mode) == SPI_MODE_SLAVE) || \ 200 ((SPI_Mode) == SPI_MODE_MASTER)) 201 202 #define IS_SPI_WORK_MODE(WORK_MODE) (((WORK_MODE) == SPI_WORK_MODE_0) || \ 203 ((WORK_MODE) == SPI_WORK_MODE_1) || \ 204 ((WORK_MODE) == SPI_WORK_MODE_2) || \ 205 ((WORK_MODE) == SPI_WORK_MODE_3)) 206 207 #define IS_SPI_X_MODE(X_MODE) (((X_MODE) == SPI_1X_MODE) || \ 208 ((X_MODE) == SPI_2X_MODE) || \ 209 ((X_MODE) == SPI_4X_MODE)) 210 211 #define IS_SPI_FIRST_BIT(FIRST_BIT) (((FIRST_BIT) == SPI_FIRSTBIT_MSB) || \ 212 ((FIRST_BIT) == SPI_FIRSTBIT_LSB)) 213 214 #define IS_SPI_BAUDRATE_PRESCALER(BAUDRATE) (((BAUDRATE) == SPI_BAUDRATE_PRESCALER_4) || \ 215 ((BAUDRATE) == SPI_BAUDRATE_PRESCALER_8) || \ 216 ((BAUDRATE) == SPI_BAUDRATE_PRESCALER_16) || \ 217 ((BAUDRATE) == SPI_BAUDRATE_PRESCALER_32) || \ 218 ((BAUDRATE) == SPI_BAUDRATE_PRESCALER_64) || \ 219 ((BAUDRATE) == SPI_BAUDRATE_PRESCALER_128) || \ 220 ((BAUDRATE) == SPI_BAUDRATE_PRESCALER_254)) 221 222 /** 223 * @brief SPI handle Structure definition 224 */ 225 typedef struct 226 { 227 SPI_TypeDef *Instance; /* SPI registers base address */ 228 229 SPI_InitTypeDef Init; /* SPI communication parameters */ 230 231 uint32_t RxState; /* SPI state machine */ 232 uint32_t TxState; /* SPI state machine */ 233 234 uint8_t *Rx_Buffer; /* SPI Rx Buffer */ 235 uint8_t *Tx_Buffer; /* SPI Tx Buffer */ 236 237 uint32_t Rx_Size; /* SPI Rx Size */ 238 uint32_t Tx_Size; /* SPI Tx Size */ 239 240 uint32_t Rx_Count; /* SPI RX Count */ 241 uint32_t Tx_Count; /* SPI TX Count */ 242 243 DMA_HandleTypeDef *HDMA_Rx; /* SPI Rx DMA handle parameters */ 244 DMA_HandleTypeDef *HDMA_Tx; /* SPI Tx DMA handle parameters */ 245 246 }SPI_HandleTypeDef; 247 248 /******************************** SPI Instances *******************************/ 249 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || ((INSTANCE) == SPI2) || ((INSTANCE) == SPI3) || ((INSTANCE) == SPI4)) 250 251 /* Function : HAL_SPI_IRQHandler */ 252 void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi); 253 254 /* Function : HAL_SPI_MspInit */ 255 void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi); 256 257 /* Function : HAL_SPI_MspDeInit */ 258 void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi); 259 260 /* Function : HAL_SPI_Init */ 261 HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi); 262 263 /* Function : HAL_SPI_DeInit */ 264 HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi); 265 266 /* Function : HAL_SPI_Transmit */ 267 HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint32_t Size, uint32_t Timeout); 268 269 /* Function : HAL_SPI_Transmit_DMA */ 270 HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint32_t Size); 271 272 /* Function : HAL_SPI_Receive */ 273 HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint32_t Size, uint32_t Timeout); 274 275 /* Function : HAL_SPI_Receive_DMA */ 276 HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint32_t Size); 277 278 /* Function : HAL_SPI_Wire_Config */ 279 HAL_StatusTypeDef HAL_SPI_Wire_Config(SPI_HandleTypeDef *hspi, uint32_t X_Mode); 280 281 /* Function : HAL_SPI_Transmit_IT */ 282 HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint32_t Size); 283 284 /* Function : HAL_SPI_Receive_IT */ 285 HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint32_t Size); 286 287 /* Function : HAL_SPI_TransmitReceive */ 288 HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint32_t Size, uint32_t Timeout); 289 290 /* Function : HAL_SPI_GetTxState */ 291 uint8_t HAL_SPI_GetTxState(SPI_HandleTypeDef *hspi); 292 293 /* Function : HAL_SPI_GetRxState */ 294 uint8_t HAL_SPI_GetRxState(SPI_HandleTypeDef *hspi); 295 296 #endif 297 298 299 300 301 302