1 /*********************************************************************** 2 * Filename : hal_timer.h 3 * Description : timer driver header file 4 * Author(s) : Eric 5 * version : V1.0 6 * Modify date : 2016-03-24 7 ***********************************************************************/ 8 #ifndef __HAL_TIMER_H__ 9 #define __HAL_TIMER_H__ 10 11 #include "ACM32Fxx_HAL.h" 12 13 #define IS_TIMER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) \ 14 || ((INSTANCE) == TIM4) || ((INSTANCE) == TIM6) || ((INSTANCE) == TIM7)\ 15 || ((INSTANCE) == TIM14) || ((INSTANCE) == TIM15) || ((INSTANCE) == TIM16)\ 16 | ((INSTANCE) == TIM17) ) 17 18 /****************** TIM Instances : supporting the break function *************/ 19 #define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 20 ((INSTANCE) == TIM15) || \ 21 ((INSTANCE) == TIM16) || \ 22 ((INSTANCE) == TIM17)) 23 24 /************** TIM Instances : supporting Break source selection *************/ 25 #define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 26 ((INSTANCE) == TIM15) || \ 27 ((INSTANCE) == TIM16) || \ 28 ((INSTANCE) == TIM17)) 29 30 31 /************* TIM Instances : at least 1 capture/compare channel *************/ 32 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 33 ((INSTANCE) == TIM2) || \ 34 ((INSTANCE) == TIM3) || \ 35 ((INSTANCE) == TIM4) || \ 36 ((INSTANCE) == TIM14) || \ 37 ((INSTANCE) == TIM15) || \ 38 ((INSTANCE) == TIM16) || \ 39 ((INSTANCE) == TIM17)) 40 41 /************ TIM Instances : at least 2 capture/compare channels *************/ 42 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 43 ((INSTANCE) == TIM2) || \ 44 ((INSTANCE) == TIM3) || \ 45 ((INSTANCE) == TIM4) || \ 46 ((INSTANCE) == TIM15)) 47 48 /************ TIM Instances : at least 3 capture/compare channels *************/ 49 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 50 ((INSTANCE) == TIM2) || \ 51 ((INSTANCE) == TIM3) || \ 52 ((INSTANCE) == TIM4)) 53 54 /************ TIM Instances : at least 4 capture/compare channels *************/ 55 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 56 ((INSTANCE) == TIM2) || \ 57 ((INSTANCE) == TIM3) || \ 58 ((INSTANCE) == TIM4)) 59 60 61 /****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/ 62 #define IS_TIM_UDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 63 ((INSTANCE) == TIM3) || \ 64 ((INSTANCE) == TIM6) || \ 65 ((INSTANCE) == TIM7) || \ 66 ((INSTANCE) == TIM15) || \ 67 ((INSTANCE) == TIM16) || \ 68 ((INSTANCE) == TIM17)) 69 70 /******************* TIM Instances : output(s) available **********************/ 71 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \ 72 ( (((INSTANCE) == TIM1) && \ 73 (((CHANNEL) == TIM_CHANNEL_1) || \ 74 ((CHANNEL) == TIM_CHANNEL_2) || \ 75 ((CHANNEL) == TIM_CHANNEL_3) || \ 76 ((CHANNEL) == TIM_CHANNEL_4) ) ) \ 77 || \ 78 (((INSTANCE) == TIM2) && \ 79 (((CHANNEL) == TIM_CHANNEL_1) || \ 80 ((CHANNEL) == TIM_CHANNEL_2) || \ 81 ((CHANNEL) == TIM_CHANNEL_3) || \ 82 ((CHANNEL) == TIM_CHANNEL_4)) ) \ 83 || \ 84 (((INSTANCE) == TIM3) && \ 85 (((CHANNEL) == TIM_CHANNEL_1) || \ 86 ((CHANNEL) == TIM_CHANNEL_2) || \ 87 ((CHANNEL) == TIM_CHANNEL_3) || \ 88 ((CHANNEL) == TIM_CHANNEL_4)) ) \ 89 || \ 90 (((INSTANCE) == TIM4) && \ 91 (((CHANNEL) == TIM_CHANNEL_1) || \ 92 ((CHANNEL) == TIM_CHANNEL_2) || \ 93 ((CHANNEL) == TIM_CHANNEL_3) || \ 94 ((CHANNEL) == TIM_CHANNEL_4)) ) \ 95 || \ 96 (((INSTANCE) == TIM14) && \ 97 (((CHANNEL) == TIM_CHANNEL_1)) ) \ 98 || \ 99 (((INSTANCE) == TIM15) && \ 100 (((CHANNEL) == TIM_CHANNEL_1) || \ 101 ((CHANNEL) == TIM_CHANNEL_2)) ) \ 102 || \ 103 (((INSTANCE) == TIM16) && \ 104 (((CHANNEL) == TIM_CHANNEL_1)) ) \ 105 || \ 106 (((INSTANCE) == TIM17) && \ 107 ((CHANNEL) == TIM_CHANNEL_1) ) ) 108 109 /****************** TIM Instances : supporting complementary output(s) ********/ 110 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \ 111 ((( (INSTANCE) == TIM1) && \ 112 (((CHANNEL) == TIM_CHANNEL_1) || \ 113 ((CHANNEL) == TIM_CHANNEL_2) || \ 114 ((CHANNEL) == TIM_CHANNEL_3)) ) \ 115 || \ 116 (((INSTANCE) == TIM15) && \ 117 ((CHANNEL) == TIM_CHANNEL_1)) \ 118 || \ 119 (((INSTANCE) == TIM16) && \ 120 ((CHANNEL) == TIM_CHANNEL_1)) \ 121 || \ 122 (((INSTANCE) == TIM17) && \ 123 ((CHANNEL) == TIM_CHANNEL_1) ) ) 124 125 /****************** TIM Instances : supporting clock division *****************/ 126 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 127 ((INSTANCE) == TIM2) || \ 128 ((INSTANCE) == TIM3) || \ 129 ((INSTANCE) == TIM4) || \ 130 ((INSTANCE) == TIM14) || \ 131 ((INSTANCE) == TIM15) || \ 132 ((INSTANCE) == TIM16) || \ 133 ((INSTANCE) == TIM17)) 134 135 /****** TIM Instances : supporting external clock mode 1 for ETRF input *******/ 136 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 137 ((INSTANCE) == TIM2) \ 138 ((INSTANCE) == TIM3) \ 139 ((INSTANCE) == TIM4) ) 140 141 /****** TIM Instances : supporting external clock mode 2 for ETRF input *******/ 142 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 143 ((INSTANCE) == TIM2) \ 144 ((INSTANCE) == TIM3) \ 145 ((INSTANCE) == TIM4) ) 146 147 /****************** TIM Instances : supporting combined 3-phase PWM mode ******/ 148 #define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) ((INSTANCE) == TIM1) 149 150 /****************** TIM Instances : supporting commutation event generation ***/ 151 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 152 ((INSTANCE) == TIM15) || \ 153 ((INSTANCE) == TIM16) || \ 154 ((INSTANCE) == TIM17)) 155 156 /****************** TIM Instances : supporting encoder interface **************/ 157 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 158 ((INSTANCE) == TIM2) \ 159 ((INSTANCE) == TIM3) \ 160 ((INSTANCE) == TIM4) ) 161 162 /****************** TIM Instances : supporting Hall sensor interface **********/ 163 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 164 ((INSTANCE) == TIM2) \ 165 ((INSTANCE) == TIM3) \ 166 ((INSTANCE) == TIM4) ) 167 168 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/ 169 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 170 ((INSTANCE) == TIM2) || \ 171 ((INSTANCE) == TIM3) || \ 172 ((INSTANCE) == TIM4) || \ 173 ((INSTANCE) == TIM15)) 174 175 /****************** TIM Instances : supporting repetition counter *************/ 176 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 177 ((INSTANCE) == TIM15) || \ 178 ((INSTANCE) == TIM16) || \ 179 ((INSTANCE) == TIM17)) 180 181 #define HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__)) 182 #define HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__)) 183 184 #define HAL_TIM_ENABLE_IT_EX(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->DIER |= (__INTERRUPT__)) 185 #define HAL_TIM_DISABLE_IT_EX(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->DIER &= ~(__INTERRUPT__)) 186 187 #define HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA_REQ__) ((__HANDLE__)->Instance->DIER |= (__DMA_REQ__)) 188 #define HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA_REQ__) ((__HANDLE__)->Instance->DIER &= ~(__DMA_REQ__)) 189 190 191 192 #define TIM_CR2_CCPC_Pos (0U) 193 #define TIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos) 194 #define TIM_CR2_CCPC TIM_CR2_CCPC_Msk 195 #define TIM_CR2_CCUS_Pos (2U) 196 #define TIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos) 197 #define TIM_CR2_CCUS TIM_CR2_CCUS_Msk 198 #define TIM_CR2_CCDS_Pos (3U) 199 #define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos) 200 #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk 201 202 #define TIM_COMMUTATION_TRGI TIM_CR2_CCUS 203 #define TIM_COMMUTATION_SOFTWARE 0x00000000U 204 205 #define TIM_IT_UPDATE BIT0 206 #define TIM_IT_CC1 BIT1 207 #define TIM_IT_CC2 BIT2 208 #define TIM_IT_CC3 BIT3 209 #define TIM_IT_CC4 BIT4 210 #define TIM_IT_COM BIT5 211 #define TIM_IT_TRIGGER BIT6 212 #define TIM_IT_BREAK BIT7 213 214 #define TIM_DMA_UPDATE BIT8 215 #define TIM_DMA_CC1 BIT9 216 #define TIM_DMA_CC2 BIT10 217 #define TIM_DMA_CC3 BIT11 218 #define TIM_DMA_CC4 BIT12 219 #define TIM_DMA_COM BIT13 220 #define TIM_DMA_TRIGGER BIT14 221 #define TIM_DMA_BREAK BIT15 222 223 224 225 #define TIM_EVENTSOURCE_UPDATE BIT0 /*!< Reinitialize the counter and generates an update of the registers */ 226 #define TIM_EVENTSOURCE_CC1 BIT1 /*!< A capture/compare event is generated on channel 1 */ 227 #define TIM_EVENTSOURCE_CC2 BIT2 /*!< A capture/compare event is generated on channel 2 */ 228 #define TIM_EVENTSOURCE_CC3 BIT3 /*!< A capture/compare event is generated on channel 3 */ 229 #define TIM_EVENTSOURCE_CC4 BIT4 /*!< A capture/compare event is generated on channel 4 */ 230 #define TIM_EVENTSOURCE_COM BIT5 /*!< A commutation event is generated */ 231 #define TIM_EVENTSOURCE_TRIGGER BIT6 /*!< A trigger event is generated */ 232 #define TIM_EVENTSOURCE_BREAK BIT7 /*!< A break event is generated */ 233 234 #define TIM_ARR_PRELOAD_DISABLE 0 235 #define TIM_ARR_PRELOAD_ENABLE 1 236 237 #define TIM_COUNTERMODE_DIR_INDEX 4 238 #define TIM_COUNTERMODE_UP (0 << TIM_COUNTERMODE_DIR_INDEX) 239 #define TIM_COUNTERMODE_DOWN (1 << TIM_COUNTERMODE_DIR_INDEX) 240 241 #define TIM_COUNTERMODE_CMS_INDEX 5 242 #define TIM_COUNTERMODE_CENTERALIGNED1 (1 << TIM_COUNTERMODE_CMS_INDEX) 243 #define TIM_COUNTERMODE_CENTERALIGNED2 (2 << TIM_COUNTERMODE_CMS_INDEX) 244 #define TIM_COUNTERMODE_CENTERALIGNED3 (3 << TIM_COUNTERMODE_CMS_INDEX) 245 246 #define TIM_CLKCK_DIV_INDEX 8 247 #define TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< Clock division: tDTS=tCK_INT */ 248 #define TIM_CLOCKDIVISION_DIV2 (1U << TIM_CLKCK_DIV_INDEX) /*!< Clock division: tDTS=2*tCK_INT */ 249 #define TIM_CLOCKDIVISION_DIV4 (2U << TIM_CLKCK_DIV_INDEX) /*!< Clock division: tDTS=4*tCK_INT */ 250 251 #define TIM_TRGO_RESET (0 << 4) 252 #define TIM_TRGO_ENABLE (1 << 4) 253 #define TIM_TRGO_UPDATE (2 << 4) 254 #define TIM_TRGO_CMP_PULSE (3 << 4) 255 #define TIM_TRGO_OC1REF (4 << 4) 256 #define TIM_TRGO_OC2REF (5 << 4) 257 #define TIM_TRGO_OC3REF (6 << 4) 258 #define TIM_TRGO_OC4REF (7 << 4) 259 260 #define TIM_MASTERSLAVEMODE_DISABLE 0 261 #define TIM_MASTERSLAVEMODE_ENABLE BIT7 262 263 264 #define TIM_SLAVE_MODE_INDEX 0 265 #define TIM_SLAVE_MODE_DIS (0U << TIM_SLAVE_MODE_INDEX) 266 #define TIM_SLAVE_MODE_ENC1 (1U << TIM_SLAVE_MODE_INDEX) 267 #define TIM_SLAVE_MODE_ENC2 (2U << TIM_SLAVE_MODE_INDEX) 268 #define TIM_SLAVE_MODE_ENC3 (3U << TIM_SLAVE_MODE_INDEX) 269 #define TIM_SLAVE_MODE_RST (4U << TIM_SLAVE_MODE_INDEX) 270 #define TIM_SLAVE_MODE_GATE (5U << TIM_SLAVE_MODE_INDEX) 271 #define TIM_SLAVE_MODE_TRIG (6U << TIM_SLAVE_MODE_INDEX) 272 #define TIM_SLAVE_MODE_EXT1 (7U << TIM_SLAVE_MODE_INDEX) 273 274 #define TIM_TRIGGER_SOURCE_INDEX 4 275 #define TIM_TRIGGER_SOURCE_ITR0 (0U << TIM_TRIGGER_SOURCE_INDEX) 276 #define TIM_TRIGGER_SOURCE_ITR1 (1U << TIM_TRIGGER_SOURCE_INDEX) 277 #define TIM_TRIGGER_SOURCE_ITR2 (2U << TIM_TRIGGER_SOURCE_INDEX) 278 #define TIM_TRIGGER_SOURCE_ITR3 (3U << TIM_TRIGGER_SOURCE_INDEX) 279 #define TIM_TRIGGER_SOURCE_TI1F_ED (4U << TIM_TRIGGER_SOURCE_INDEX) 280 #define TIM_TRIGGER_SOURCE_TI1FP1 (5U << TIM_TRIGGER_SOURCE_INDEX) 281 #define TIM_TRIGGER_SOURCE_TI2FP2 (6U << TIM_TRIGGER_SOURCE_INDEX) 282 #define TIM_TRIGGER_SOURCE_ETRF (7U << TIM_TRIGGER_SOURCE_INDEX) 283 284 #define TIMER_SR_UIF BIT0 285 #define TIMER_SR_CC1IF BIT1 286 #define TIMER_SR_CC2IF BIT2 287 #define TIMER_SR_CC3IF BIT3 288 #define TIMER_SR_CC4IF BIT4 289 #define TIMER_SR_COMIF BIT5 290 #define TIMER_SR_TIF BIT6 291 #define TIMER_SR_BIF BIT7 292 #define TIMER_SR_CC1OF BIT9 293 #define TIMER_SR_CC2OF BIT10 294 #define TIMER_SR_CC3OF BIT11 295 #define TIMER_SR_CC4OF BIT12 296 297 #define TIMER_INT_EN_UPD BIT0 298 #define TIMER_INT_EN_CC1 BIT1 299 #define TIMER_INT_EN_CC2 BIT2 300 #define TIMER_INT_EN_CC3 BIT3 301 #define TIMER_INT_EN_CC4 BIT4 302 #define TIMER_INT_EN_COM BIT5 303 #define TIMER_INT_EN_TRI BIT6 304 #define TIMER_INT_EN_BRK BIT7 305 306 #define TIMER_DMA_EN_UPD BIT8 307 #define TIMER_DMA_EN_CC1 BIT9 308 #define TIMER_DMA_EN_CC2 BIT10 309 #define TIMER_DMA_EN_CC3 BIT11 310 #define TIMER_DMA_EN_CC4 BIT12 311 #define TIMER_DMA_EN_COM BIT13 312 #define TIMER_DMA_EN_TRI BIT14 313 314 #define TIM_CHANNEL_1 0 315 #define TIM_CHANNEL_2 1 316 #define TIM_CHANNEL_3 2 317 #define TIM_CHANNEL_4 3 318 319 #define OUTPUT_FAST_MODE_DISABLE 0 320 #define OUTPUT_FAST_MODE_ENABLE 1 321 322 #define OUTPUT_POL_ACTIVE_HIGH 0 323 #define OUTPUT_POL_ACTIVE_LOW 1 324 325 #define OUTPUT_DISABLE_IDLE_STATE 0 326 #define OUTPUT_ENABLE_IDLE_STATE 1 327 328 #define OUTPUT_IDLE_STATE_0 0 329 #define OUTPUT_IDLE_STATE_1 1 330 331 #define OUTPUT_MODE_FROZEN 0 332 #define OUTPUT_MODE_MATCH_HIGH 1 333 #define OUTPUT_MODE_MATCH_LOW 2 334 #define OUTPUT_MODE_MATCH_TOGGLE 3 335 #define OUTPUT_MODE_FORCE_LOW 4 336 #define OUTPUT_MODE_FORCE_HIGH 5 337 #define OUTPUT_MODE_PWM1 6 338 #define OUTPUT_MODE_PWM2 7 339 340 #define TIM_CLOCKSOURCE_INT 0 341 #define TIM_CLOCKSOURCE_ITR0 1 342 #define TIM_CLOCKSOURCE_ITR1 2 343 #define TIM_CLOCKSOURCE_ITR2 3 344 #define TIM_CLOCKSOURCE_ITR3 4 345 #define TIM_CLOCKSOURCE_TI1FP1 5 346 #define TIM_CLOCKSOURCE_TI2FP2 6 347 #define TIM_CLOCKSOURCE_ETR 7 348 349 #define TIM_ETR_POLAIRTY_HIGH 0 350 #define TIM_ETR_POLAIRTY_LOW (BIT15) 351 #define TIM_ETR_FILTER_LVL(x) (x << 8) //BIT8-BIT11 352 353 #define TIM_ETR_PRESCALER_1 0 354 #define TIM_ETR_PRESCALER_2 (BIT12) 355 #define TIM_ETR_PRESCALER_4 (BIT13) 356 #define TIM_ETR_PRESCALER_8 (BIT12|BIT13) 357 358 #define ETR_SELECT_GPIO 0 359 #define ETR_SELECT_COMP1_OUT BIT14 360 #define ETR_SELECT_COMP2_OUT BIT15 361 #define ETR_SELECT_ADC_AWD BIT14|BIT15 362 #define ETR_SELECT_MASK (BIT14|BIT15) 363 364 #define TIM_TI1_FILTER_LVL(x) (x << 4) 365 #define TIM_TI2_FILTER_LVL(x) (x << 12) 366 #define TIM_TI3_FILTER_LVL(x) (x << 4) 367 #define TIM_TI4_FILTER_LVL(x) (x << 12) 368 369 #define TIM_IC1_PRESCALER_1 0 370 #define TIM_IC1_PRESCALER_2 (BIT2) 371 #define TIM_IC1_PRESCALER_4 (BIT3) 372 #define TIM_IC1_PRESCALER_8 (BIT2|BIT3) 373 374 #define TIM_IC2_PRESCALER_1 0 375 #define TIM_IC2_PRESCALER_2 (BIT10) 376 #define TIM_IC2_PRESCALER_4 (BIT11) 377 #define TIM_IC2_PRESCALER_8 (BIT10|BIT11) 378 379 #define TIM_IC3_PRESCALER_1 0 380 #define TIM_IC3_PRESCALER_2 (BIT2) 381 #define TIM_IC3_PRESCALER_4 (BIT3) 382 #define TIM_IC3_PRESCALER_8 (BIT2|BIT3) 383 384 #define TIM_IC4_PRESCALER_1 0 385 #define TIM_IC4_PRESCALER_2 (BIT10) 386 #define TIM_IC4_PRESCALER_4 (BIT11) 387 #define TIM_IC4_PRESCALER_8 (BIT10|BIT11) 388 389 typedef struct 390 { 391 uint32_t ClockSource; //TIMER clock sources 392 uint32_t ClockPolarity; //TIMER clock polarity 393 uint32_t ClockPrescaler; //TIMER clock prescaler 394 uint32_t ClockFilter; //TIMER clock filter 395 } TIM_ClockConfigTypeDef; 396 397 typedef struct 398 { 399 uint32_t OCMode; // Specifies the TIM mode. 400 uint32_t Pulse; // Specifies the pulse value to be loaded into the Capture Compare Register. 401 uint32_t OCPolarity; // Specifies the output polarity. 402 uint32_t OCNPolarity; // Specifies the complementary output polarity. 403 uint32_t OCFastMode; // Specifies the Fast mode state. 404 uint32_t OCIdleState; // Specifies the TIM Output Compare pin state during Idle state. 405 uint32_t OCNIdleState; // Specifies the TIM Output Compare complementary pin state during Idle state. 406 } TIM_OC_InitTypeDef; 407 408 409 #define TIM_SLAVE_CAPTURE_ACTIVE_RISING 0 410 #define TIM_SLAVE_CAPTURE_ACTIVE_FALLING 1 411 #define TIM_SLAVE_CAPTURE_ACTIVE_RISING_FALLING 2 412 413 #define TIM_ICSELECTION_DIRECTTI 0 414 #define TIM_ICSELECTION_INDIRECTTI 1 415 416 #define TIM_CC1_SLAVE_CAPTURE_POL_RISING (0) 417 #define TIM_CC1_SLAVE_CAPTURE_POL_FALLING (BIT1) 418 #define TIM_CC1_SLAVE_CAPTURE_POL_BOTH (BIT1 | BIT3) 419 420 #define TIM_CC2_SLAVE_CAPTURE_POL_RISING (0) 421 #define TIM_CC2_SLAVE_CAPTURE_POL_FALLING (BIT5) 422 #define TIM_CC2_SLAVE_CAPTURE_POL_BOTH (BIT5 | BIT7) 423 424 #define TIM_CC3_SLAVE_CAPTURE_POL_RISING (0) 425 #define TIM_CC3_SLAVE_CAPTURE_POL_FALLING (BIT9) 426 #define TIM_CC3_SLAVE_CAPTURE_POL_BOTH (BIT9 | BIT11) 427 428 #define TIM_CC4_SLAVE_CAPTURE_POL_RISING (0) 429 #define TIM_CC4_SLAVE_CAPTURE_POL_FALLING (BIT13) 430 #define TIM_CC4_SLAVE_CAPTURE_POL_BOTH (BIT13 | BIT15) 431 432 typedef struct 433 { 434 uint32_t SlaveMode; // Slave mode selection 435 uint32_t InputTrigger; // Input Trigger source 436 uint32_t TriggerPolarity; // Input Trigger polarity 437 uint32_t TriggerPrescaler; // input prescaler, only for ETR input 438 uint32_t TriggerFilter; // Input trigger filter 439 } TIM_SlaveConfigTypeDef; 440 441 typedef struct 442 { 443 uint32_t ICPolarity; // Specifies the active edge of the input signal. 444 uint32_t ICSelection; // Specifies the input 445 uint32_t ICPrescaler; // Specifies the Input Capture Prescaler. 446 uint32_t TIFilter; // Specifies the input capture filter. 447 } TIM_IC_InitTypeDef; 448 449 typedef struct 450 { 451 uint32_t MasterOutputTrigger; // Trigger output (TRGO) selection 452 uint32_t MasterSlaveMode; // Master/slave mode selection 453 } TIM_MasterConfigTypeDef; 454 455 #define TIM_DMA_UPDATE_INDEX 0 456 #define TIM_DMA_CC1_INDEX 1 457 #define TIM_DMA_CC2_INDEX 2 458 #define TIM_DMA_CC3_INDEX 3 459 #define TIM_DMA_CC4_INDEX 4 460 #define TIM_DMA_COM_INDEX 5 461 #define TIM_DMA_TRIG_INDEX 6 462 463 #define MAX_DMA_REQ_ONE_TIMER 7 464 465 typedef struct 466 { 467 uint32_t Prescaler; // Specifies the prescaler value used to divide the TIM clock. 468 uint32_t Period; // Specifies the ARR value 469 uint32_t ARRPreLoadEn; // Specifies the preload enable or disable 470 uint32_t RepetitionCounter; // Specifies the repetition counter value 471 uint32_t CounterMode; // Specifies the counter mode.Up/Down/Center 472 uint32_t ClockDivision; // Specifies the clock division, used for deadtime or sampling 473 } TIM_Base_InitTypeDef; 474 475 typedef struct 476 { 477 TIM_TypeDef *Instance; 478 TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ 479 DMA_HandleTypeDef *hdma[MAX_DMA_REQ_ONE_TIMER]; 480 }TIM_HandleTypeDef; 481 482 /* HAL_TIMER_MSP_Init */ 483 extern uint32_t HAL_TIMER_MSP_Init(TIM_HandleTypeDef * htim); 484 /* HAL_TIMER_Slave_Mode_Config */ 485 extern uint32_t HAL_TIMER_Slave_Mode_Config(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig); 486 /* HAL_TIMER_Base_Init */ 487 extern uint32_t HAL_TIMER_Base_Init(TIM_HandleTypeDef * htim); 488 /* HAL_TIMER_Output_Config */ 489 extern uint32_t HAL_TIMER_Output_Config(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef * Output_Config, uint32_t Channel); 490 /* HAL_TIMER_Base_Start */ 491 extern void HAL_TIMER_Base_Start(TIM_TypeDef *TIMx); 492 /* HAL_TIM_PWM_Output_Start */ 493 extern uint32_t HAL_TIM_PWM_Output_Start(TIM_TypeDef *TIMx, uint32_t Channel); 494 /* HAL_TIM_PWM_Output_Stop */ 495 extern HAL_StatusTypeDef HAL_TIM_PWM_Output_Stop(TIM_TypeDef *TIMx, uint32_t Channel); 496 /* HAL_TIMER_OC_Start */ 497 extern uint32_t HAL_TIMER_OC_Start(TIM_TypeDef *TIMx, uint32_t Channel); 498 /* HAL_TIMER_OCxN_Start */ 499 extern uint32_t HAL_TIMER_OCxN_Start(TIM_TypeDef *TIMx, uint32_t Channel); 500 /* HAL_TIMER_OC_Stop */ 501 extern HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_TypeDef *TIMx, uint32_t Channel); 502 /* HAL_TIM_Capture_Start */ 503 extern uint32_t HAL_TIM_Capture_Start(TIM_TypeDef *TIMx, uint32_t Channel); 504 /* HAL_TIM_Capture_Stop */ 505 extern uint32_t HAL_TIM_Capture_Stop(TIM_TypeDef *TIMx, uint32_t Channel); 506 /* HAL_TIMER_Capture_Config */ 507 extern uint32_t HAL_TIMER_Capture_Config(TIM_TypeDef *TIMx, TIM_IC_InitTypeDef * Capture_Config, uint32_t Channel); 508 /* HAL_TIMER_Master_Mode_Config */ 509 extern uint32_t HAL_TIMER_Master_Mode_Config(TIM_TypeDef *TIMx, TIM_MasterConfigTypeDef * sMasterConfig); 510 /* HAL_TIMER_SelectClockSource */ 511 extern HAL_StatusTypeDef HAL_TIMER_SelectClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig); 512 /* HAL_TIMER_ReadCapturedValue */ 513 extern uint32_t HAL_TIMER_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel); 514 /* HAL_TIMER_Clear_Capture_Flag */ 515 extern void HAL_TIMER_Clear_Capture_Flag(TIM_HandleTypeDef *htim, uint32_t Channel); 516 #endif 517 518 519 520 521