1 /* 2 * Copyright (c) 2006-2022, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2022-02-22 airm2m first version 9 */ 10 11 #ifndef __BOARD_H__ 12 #define __BOARD_H__ 13 14 #include <air32f10x_conf.h> 15 #include "drv_common.h" 16 #include "drv_gpio.h" 17 18 #ifdef __cplusplus 19 extern "C" { 20 #endif 21 22 #define AIR32_FLASH_START_ADRESS ((uint32_t)0x08000000) 23 #define FLASH_PAGE_SIZE (64) 24 #define AIR32_FLASH_SIZE (128 * 1024) 25 #define AIR32_FLASH_END_ADDRESS ((uint32_t)(AIR32_FLASH_START_ADRESS + AIR32_FLASH_SIZE)) 26 27 /* Internal SRAM memory size[Kbytes] , Default: 96*/ 28 #define AIR32_SRAM_SIZE 96 29 #define AIR32_SRAM_END (0x20000000 + AIR32_SRAM_SIZE * 1024) 30 31 #if defined(__ARMCC_VERSION) 32 extern int Image$$RW_IRAM1$$ZI$$Limit; 33 #define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit) 34 #elif __ICCARM__ 35 #pragma section="CSTACK" 36 #define HEAP_BEGIN (__segment_end("CSTACK")) 37 #else 38 extern int __bss_end; 39 #define HEAP_BEGIN ((void *)&__bss_end) 40 #endif 41 42 #define HEAP_END AIR32_SRAM_END 43 44 void SystemClock_Config(void); 45 46 #ifdef BSP_USING_UART 47 void air32_usart_clock_and_io_init(USART_TypeDef *usartx); 48 #endif 49 50 #ifdef BSP_USING_SPI 51 void air32_spi_clock_and_io_init(SPI_TypeDef* spix); 52 rt_uint32_t air32_spi_clock_get(SPI_TypeDef* spix); 53 #endif 54 55 #ifdef BSP_USING_TIM 56 void air32_tim_clock_init(TIM_TypeDef *timx); 57 rt_uint32_t air32_tim_clock_get(TIM_TypeDef *timx); 58 #endif 59 60 #ifdef BSP_USING_TIM 61 struct rt_hwtimer_info* air32_hwtimer_info_config_get(TIM_TypeDef *timx); 62 #endif 63 64 #ifdef BSP_USING_PWM 65 void air32_pwm_io_init(TIM_TypeDef *timx, rt_uint8_t channel); 66 #endif 67 68 #ifdef __cplusplus 69 } 70 #endif 71 72 #endif /* __BOARD_H__ */ 73