1 /* Define to prevent recursive inclusion -------------------------------------*/ 2 #ifndef __AIR32F10x_FSMC_H 3 #define __AIR32F10x_FSMC_H 4 5 #ifdef __cplusplus 6 extern "C" { 7 #endif 8 9 /* Includes ------------------------------------------------------------------*/ 10 #include "air32f10x.h" 11 12 /** @addtogroup air32f10x_StdPeriph_Driver 13 * @{ 14 */ 15 16 /** @addtogroup FSMC 17 * @{ 18 */ 19 20 /** @defgroup FSMC_Exported_Types 21 * @{ 22 */ 23 24 /** 25 * @brief Timing parameters For NOR/SRAM Banks 26 */ 27 28 typedef struct 29 { 30 uint32_t FSMC_AddressSetupTime; /*!< Defines the number of HCLK cycles to configure 31 the duration of the address setup time. 32 This parameter can be a value between 0 and 0xF. 33 @note: It is not used with synchronous NOR Flash memories. */ 34 35 uint32_t FSMC_AddressHoldTime; /*!< Defines the number of HCLK cycles to configure 36 the duration of the address hold time. 37 This parameter can be a value between 0 and 0xF. 38 @note: It is not used with synchronous NOR Flash memories.*/ 39 40 uint32_t FSMC_DataSetupTime; /*!< Defines the number of HCLK cycles to configure 41 the duration of the data setup time. 42 This parameter can be a value between 0 and 0xFF. 43 @note: It is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */ 44 45 uint32_t FSMC_BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure 46 the duration of the bus turnaround. 47 This parameter can be a value between 0 and 0xF. 48 @note: It is only used for multiplexed NOR Flash memories. */ 49 50 uint32_t FSMC_CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of HCLK cycles. 51 This parameter can be a value between 1 and 0xF. 52 @note: This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */ 53 54 uint32_t FSMC_DataLatency; /*!< Defines the number of memory clock cycles to issue 55 to the memory before getting the first data. 56 The value of this parameter depends on the memory type as shown below: 57 - It must be set to 0 in case of a CRAM 58 - It is don't care in asynchronous NOR, SRAM or ROM accesses 59 - It may assume a value between 0 and 0xF in NOR Flash memories 60 with synchronous burst mode enable */ 61 62 uint32_t FSMC_AccessMode; /*!< Specifies the asynchronous access mode. 63 This parameter can be a value of @ref FSMC_Access_Mode */ 64 }FSMC_NORSRAMTimingInitTypeDef; 65 66 /** 67 * @brief FSMC NOR/SRAM Init structure definition 68 */ 69 70 typedef struct 71 { 72 uint32_t FSMC_Bank; /*!< Specifies the NOR/SRAM memory bank that will be used. 73 This parameter can be a value of @ref FSMC_NORSRAM_Bank */ 74 75 uint32_t FSMC_DataAddressMux; /*!< Specifies whether the address and data values are 76 multiplexed on the databus or not. 77 This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */ 78 79 uint32_t FSMC_MemoryType; /*!< Specifies the type of external memory attached to 80 the corresponding memory bank. 81 This parameter can be a value of @ref FSMC_Memory_Type */ 82 83 uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width. 84 This parameter can be a value of @ref FSMC_Data_Width */ 85 86 uint32_t FSMC_BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory, 87 valid only with synchronous burst Flash memories. 88 This parameter can be a value of @ref FSMC_Burst_Access_Mode */ 89 90 uint32_t FSMC_AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers, 91 valid only with asynchronous Flash memories. 92 This parameter can be a value of @ref FSMC_AsynchronousWait */ 93 94 uint32_t FSMC_WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing 95 the Flash memory in burst mode. 96 This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */ 97 98 uint32_t FSMC_WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash 99 memory, valid only when accessing Flash memories in burst mode. 100 This parameter can be a value of @ref FSMC_Wrap_Mode */ 101 102 uint32_t FSMC_WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one 103 clock cycle before the wait state or during the wait state, 104 valid only when accessing memories in burst mode. 105 This parameter can be a value of @ref FSMC_Wait_Timing */ 106 107 uint32_t FSMC_WriteOperation; /*!< Enables or disables the write operation in the selected bank by the FSMC. 108 This parameter can be a value of @ref FSMC_Write_Operation */ 109 110 uint32_t FSMC_WaitSignal; /*!< Enables or disables the wait-state insertion via wait 111 signal, valid for Flash memory access in burst mode. 112 This parameter can be a value of @ref FSMC_Wait_Signal */ 113 114 uint32_t FSMC_ExtendedMode; /*!< Enables or disables the extended mode. 115 This parameter can be a value of @ref FSMC_Extended_Mode */ 116 117 uint32_t FSMC_WriteBurst; /*!< Enables or disables the write burst operation. 118 This parameter can be a value of @ref FSMC_Write_Burst */ 119 120 FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct; /*!< Timing Parameters for write and read access if the ExtendedMode is not used*/ 121 122 FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct; /*!< Timing Parameters for write access if the ExtendedMode is used*/ 123 }FSMC_NORSRAMInitTypeDef; 124 125 /** 126 * @brief Timing parameters For FSMC NAND and PCCARD Banks 127 */ 128 129 typedef struct 130 { 131 uint32_t FSMC_SetupTime; /*!< Defines the number of HCLK cycles to setup address before 132 the command assertion for NAND-Flash read or write access 133 to common/Attribute or I/O memory space (depending on 134 the memory space timing to be configured). 135 This parameter can be a value between 0 and 0xFF.*/ 136 137 uint32_t FSMC_WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the 138 command for NAND-Flash read or write access to 139 common/Attribute or I/O memory space (depending on the 140 memory space timing to be configured). 141 This parameter can be a number between 0x00 and 0xFF */ 142 143 uint32_t FSMC_HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address 144 (and data for write access) after the command deassertion 145 for NAND-Flash read or write access to common/Attribute 146 or I/O memory space (depending on the memory space timing 147 to be configured). 148 This parameter can be a number between 0x00 and 0xFF */ 149 150 uint32_t FSMC_HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the 151 databus is kept in HiZ after the start of a NAND-Flash 152 write access to common/Attribute or I/O memory space (depending 153 on the memory space timing to be configured). 154 This parameter can be a number between 0x00 and 0xFF */ 155 }FSMC_NAND_PCCARDTimingInitTypeDef; 156 157 /** 158 * @brief FSMC NAND Init structure definition 159 */ 160 161 typedef struct 162 { 163 uint32_t FSMC_Bank; /*!< Specifies the NAND memory bank that will be used. 164 This parameter can be a value of @ref FSMC_NAND_Bank */ 165 166 uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory Bank. 167 This parameter can be any value of @ref FSMC_Wait_feature */ 168 169 uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width. 170 This parameter can be any value of @ref FSMC_Data_Width */ 171 172 uint32_t FSMC_ECC; /*!< Enables or disables the ECC computation. 173 This parameter can be any value of @ref FSMC_ECC */ 174 175 uint32_t FSMC_ECCPageSize; /*!< Defines the page size for the extended ECC. 176 This parameter can be any value of @ref FSMC_ECC_Page_Size */ 177 178 uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the 179 delay between CLE low and RE low. 180 This parameter can be a value between 0 and 0xFF. */ 181 182 uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the 183 delay between ALE low and RE low. 184 This parameter can be a number between 0x0 and 0xFF */ 185 186 FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */ 187 188 FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */ 189 }FSMC_NANDInitTypeDef; 190 191 /** 192 * @brief FSMC PCCARD Init structure definition 193 */ 194 195 typedef struct 196 { 197 uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the Memory Bank. 198 This parameter can be any value of @ref FSMC_Wait_feature */ 199 200 uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the 201 delay between CLE low and RE low. 202 This parameter can be a value between 0 and 0xFF. */ 203 204 uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the 205 delay between ALE low and RE low. 206 This parameter can be a number between 0x0 and 0xFF */ 207 208 209 FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */ 210 211 FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */ 212 213 FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_IOSpaceTimingStruct; /*!< FSMC IO Space Timing */ 214 }FSMC_PCCARDInitTypeDef; 215 216 /** 217 * @} 218 */ 219 220 /** @defgroup FSMC_Exported_Constants 221 * @{ 222 */ 223 224 /** @defgroup FSMC_NORSRAM_Bank 225 * @{ 226 */ 227 #define FSMC_Bank1_NORSRAM1 ((uint32_t)0x00000000) 228 #define FSMC_Bank1_NORSRAM2 ((uint32_t)0x00000002) 229 #define FSMC_Bank1_NORSRAM3 ((uint32_t)0x00000004) 230 #define FSMC_Bank1_NORSRAM4 ((uint32_t)0x00000006) 231 /** 232 * @} 233 */ 234 235 /** @defgroup FSMC_NAND_Bank 236 * @{ 237 */ 238 #define FSMC_Bank2_NAND ((uint32_t)0x00000010) 239 #define FSMC_Bank3_NAND ((uint32_t)0x00000100) 240 /** 241 * @} 242 */ 243 244 /** @defgroup FSMC_PCCARD_Bank 245 * @{ 246 */ 247 #define FSMC_Bank4_PCCARD ((uint32_t)0x00001000) 248 /** 249 * @} 250 */ 251 252 #define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_Bank1_NORSRAM1) || \ 253 ((BANK) == FSMC_Bank1_NORSRAM2) || \ 254 ((BANK) == FSMC_Bank1_NORSRAM3) || \ 255 ((BANK) == FSMC_Bank1_NORSRAM4)) 256 257 #define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \ 258 ((BANK) == FSMC_Bank3_NAND)) 259 260 #define IS_FSMC_GETFLAG_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \ 261 ((BANK) == FSMC_Bank3_NAND) || \ 262 ((BANK) == FSMC_Bank4_PCCARD)) 263 264 #define IS_FSMC_IT_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \ 265 ((BANK) == FSMC_Bank3_NAND) || \ 266 ((BANK) == FSMC_Bank4_PCCARD)) 267 268 /** @defgroup NOR_SRAM_Controller 269 * @{ 270 */ 271 272 /** @defgroup FSMC_Data_Address_Bus_Multiplexing 273 * @{ 274 */ 275 276 #define FSMC_DataAddressMux_Disable ((uint32_t)0x00000000) 277 #define FSMC_DataAddressMux_Enable ((uint32_t)0x00000002) 278 #define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) || \ 279 ((MUX) == FSMC_DataAddressMux_Enable)) 280 281 /** 282 * @} 283 */ 284 285 /** @defgroup FSMC_Memory_Type 286 * @{ 287 */ 288 289 #define FSMC_MemoryType_SRAM ((uint32_t)0x00000000) 290 #define FSMC_MemoryType_PSRAM ((uint32_t)0x00000004) 291 #define FSMC_MemoryType_NOR ((uint32_t)0x00000008) 292 #define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) || \ 293 ((MEMORY) == FSMC_MemoryType_PSRAM)|| \ 294 ((MEMORY) == FSMC_MemoryType_NOR)) 295 296 /** 297 * @} 298 */ 299 300 /** @defgroup FSMC_Data_Width 301 * @{ 302 */ 303 304 #define FSMC_MemoryDataWidth_8b ((uint32_t)0x00000000) 305 #define FSMC_MemoryDataWidth_16b ((uint32_t)0x00000010) 306 #define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \ 307 ((WIDTH) == FSMC_MemoryDataWidth_16b)) 308 309 /** 310 * @} 311 */ 312 313 /** @defgroup FSMC_Burst_Access_Mode 314 * @{ 315 */ 316 317 #define FSMC_BurstAccessMode_Disable ((uint32_t)0x00000000) 318 #define FSMC_BurstAccessMode_Enable ((uint32_t)0x00000100) 319 #define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) || \ 320 ((STATE) == FSMC_BurstAccessMode_Enable)) 321 /** 322 * @} 323 */ 324 325 /** @defgroup FSMC_AsynchronousWait 326 * @{ 327 */ 328 #define FSMC_AsynchronousWait_Disable ((uint32_t)0x00000000) 329 #define FSMC_AsynchronousWait_Enable ((uint32_t)0x00008000) 330 #define IS_FSMC_ASYNWAIT(STATE) (((STATE) == FSMC_AsynchronousWait_Disable) || \ 331 ((STATE) == FSMC_AsynchronousWait_Enable)) 332 333 /** 334 * @} 335 */ 336 337 /** @defgroup FSMC_Wait_Signal_Polarity 338 * @{ 339 */ 340 341 #define FSMC_WaitSignalPolarity_Low ((uint32_t)0x00000000) 342 #define FSMC_WaitSignalPolarity_High ((uint32_t)0x00000200) 343 #define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) || \ 344 ((POLARITY) == FSMC_WaitSignalPolarity_High)) 345 346 /** 347 * @} 348 */ 349 350 /** @defgroup FSMC_Wrap_Mode 351 * @{ 352 */ 353 354 #define FSMC_WrapMode_Disable ((uint32_t)0x00000000) 355 #define FSMC_WrapMode_Enable ((uint32_t)0x00000400) 356 #define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) || \ 357 ((MODE) == FSMC_WrapMode_Enable)) 358 359 /** 360 * @} 361 */ 362 363 /** @defgroup FSMC_Wait_Timing 364 * @{ 365 */ 366 367 #define FSMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000) 368 #define FSMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800) 369 #define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) || \ 370 ((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState)) 371 372 /** 373 * @} 374 */ 375 376 /** @defgroup FSMC_Write_Operation 377 * @{ 378 */ 379 380 #define FSMC_WriteOperation_Disable ((uint32_t)0x00000000) 381 #define FSMC_WriteOperation_Enable ((uint32_t)0x00001000) 382 #define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) || \ 383 ((OPERATION) == FSMC_WriteOperation_Enable)) 384 385 /** 386 * @} 387 */ 388 389 /** @defgroup FSMC_Wait_Signal 390 * @{ 391 */ 392 393 #define FSMC_WaitSignal_Disable ((uint32_t)0x00000000) 394 #define FSMC_WaitSignal_Enable ((uint32_t)0x00002000) 395 #define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) || \ 396 ((SIGNAL) == FSMC_WaitSignal_Enable)) 397 /** 398 * @} 399 */ 400 401 /** @defgroup FSMC_Extended_Mode 402 * @{ 403 */ 404 405 #define FSMC_ExtendedMode_Disable ((uint32_t)0x00000000) 406 #define FSMC_ExtendedMode_Enable ((uint32_t)0x00004000) 407 408 #define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) || \ 409 ((MODE) == FSMC_ExtendedMode_Enable)) 410 411 /** 412 * @} 413 */ 414 415 /** @defgroup FSMC_Write_Burst 416 * @{ 417 */ 418 419 #define FSMC_WriteBurst_Disable ((uint32_t)0x00000000) 420 #define FSMC_WriteBurst_Enable ((uint32_t)0x00080000) 421 #define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) || \ 422 ((BURST) == FSMC_WriteBurst_Enable)) 423 /** 424 * @} 425 */ 426 427 /** @defgroup FSMC_Address_Setup_Time 428 * @{ 429 */ 430 431 #define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF) 432 433 /** 434 * @} 435 */ 436 437 /** @defgroup FSMC_Address_Hold_Time 438 * @{ 439 */ 440 441 #define IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF) 442 443 /** 444 * @} 445 */ 446 447 /** @defgroup FSMC_Data_Setup_Time 448 * @{ 449 */ 450 451 #define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF)) 452 453 /** 454 * @} 455 */ 456 457 /** @defgroup FSMC_Bus_Turn_around_Duration 458 * @{ 459 */ 460 461 #define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF) 462 463 /** 464 * @} 465 */ 466 467 /** @defgroup FSMC_CLK_Division 468 * @{ 469 */ 470 471 #define IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF) 472 473 /** 474 * @} 475 */ 476 477 /** @defgroup FSMC_Data_Latency 478 * @{ 479 */ 480 481 #define IS_FSMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF) 482 483 /** 484 * @} 485 */ 486 487 /** @defgroup FSMC_Access_Mode 488 * @{ 489 */ 490 491 #define FSMC_AccessMode_A ((uint32_t)0x00000000) 492 #define FSMC_AccessMode_B ((uint32_t)0x10000000) 493 #define FSMC_AccessMode_C ((uint32_t)0x20000000) 494 #define FSMC_AccessMode_D ((uint32_t)0x30000000) 495 #define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) || \ 496 ((MODE) == FSMC_AccessMode_B) || \ 497 ((MODE) == FSMC_AccessMode_C) || \ 498 ((MODE) == FSMC_AccessMode_D)) 499 500 /** 501 * @} 502 */ 503 504 /** 505 * @} 506 */ 507 508 /** @defgroup NAND_PCCARD_Controller 509 * @{ 510 */ 511 512 /** @defgroup FSMC_Wait_feature 513 * @{ 514 */ 515 516 #define FSMC_Waitfeature_Disable ((uint32_t)0x00000000) 517 #define FSMC_Waitfeature_Enable ((uint32_t)0x00000002) 518 #define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_Waitfeature_Disable) || \ 519 ((FEATURE) == FSMC_Waitfeature_Enable)) 520 521 /** 522 * @} 523 */ 524 525 526 /** @defgroup FSMC_ECC 527 * @{ 528 */ 529 530 #define FSMC_ECC_Disable ((uint32_t)0x00000000) 531 #define FSMC_ECC_Enable ((uint32_t)0x00000040) 532 #define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_ECC_Disable) || \ 533 ((STATE) == FSMC_ECC_Enable)) 534 535 /** 536 * @} 537 */ 538 539 /** @defgroup FSMC_ECC_Page_Size 540 * @{ 541 */ 542 543 #define FSMC_ECCPageSize_256Bytes ((uint32_t)0x00000000) 544 #define FSMC_ECCPageSize_512Bytes ((uint32_t)0x00020000) 545 #define FSMC_ECCPageSize_1024Bytes ((uint32_t)0x00040000) 546 #define FSMC_ECCPageSize_2048Bytes ((uint32_t)0x00060000) 547 #define FSMC_ECCPageSize_4096Bytes ((uint32_t)0x00080000) 548 #define FSMC_ECCPageSize_8192Bytes ((uint32_t)0x000A0000) 549 #define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_ECCPageSize_256Bytes) || \ 550 ((SIZE) == FSMC_ECCPageSize_512Bytes) || \ 551 ((SIZE) == FSMC_ECCPageSize_1024Bytes) || \ 552 ((SIZE) == FSMC_ECCPageSize_2048Bytes) || \ 553 ((SIZE) == FSMC_ECCPageSize_4096Bytes) || \ 554 ((SIZE) == FSMC_ECCPageSize_8192Bytes)) 555 556 /** 557 * @} 558 */ 559 560 /** @defgroup FSMC_TCLR_Setup_Time 561 * @{ 562 */ 563 564 #define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 0xFF) 565 566 /** 567 * @} 568 */ 569 570 /** @defgroup FSMC_TAR_Setup_Time 571 * @{ 572 */ 573 574 #define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 0xFF) 575 576 /** 577 * @} 578 */ 579 580 /** @defgroup FSMC_Setup_Time 581 * @{ 582 */ 583 584 #define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 0xFF) 585 586 /** 587 * @} 588 */ 589 590 /** @defgroup FSMC_Wait_Setup_Time 591 * @{ 592 */ 593 594 #define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 0xFF) 595 596 /** 597 * @} 598 */ 599 600 /** @defgroup FSMC_Hold_Setup_Time 601 * @{ 602 */ 603 604 #define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 0xFF) 605 606 /** 607 * @} 608 */ 609 610 /** @defgroup FSMC_HiZ_Setup_Time 611 * @{ 612 */ 613 614 #define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 0xFF) 615 616 /** 617 * @} 618 */ 619 620 /** @defgroup FSMC_Interrupt_sources 621 * @{ 622 */ 623 624 #define FSMC_IT_RisingEdge ((uint32_t)0x00000008) 625 #define FSMC_IT_Level ((uint32_t)0x00000010) 626 #define FSMC_IT_FallingEdge ((uint32_t)0x00000020) 627 #define IS_FSMC_IT(IT) ((((IT) & (uint32_t)0xFFFFFFC7) == 0x00000000) && ((IT) != 0x00000000)) 628 #define IS_FSMC_GET_IT(IT) (((IT) == FSMC_IT_RisingEdge) || \ 629 ((IT) == FSMC_IT_Level) || \ 630 ((IT) == FSMC_IT_FallingEdge)) 631 /** 632 * @} 633 */ 634 635 /** @defgroup FSMC_Flags 636 * @{ 637 */ 638 639 #define FSMC_FLAG_RisingEdge ((uint32_t)0x00000001) 640 #define FSMC_FLAG_Level ((uint32_t)0x00000002) 641 #define FSMC_FLAG_FallingEdge ((uint32_t)0x00000004) 642 #define FSMC_FLAG_FEMPT ((uint32_t)0x00000040) 643 #define IS_FSMC_GET_FLAG(FLAG) (((FLAG) == FSMC_FLAG_RisingEdge) || \ 644 ((FLAG) == FSMC_FLAG_Level) || \ 645 ((FLAG) == FSMC_FLAG_FallingEdge) || \ 646 ((FLAG) == FSMC_FLAG_FEMPT)) 647 648 #define IS_FSMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000)) 649 650 /** 651 * @} 652 */ 653 654 /** 655 * @} 656 */ 657 658 /** 659 * @} 660 */ 661 662 /** @defgroup FSMC_Exported_Macros 663 * @{ 664 */ 665 666 /** 667 * @} 668 */ 669 670 /** @defgroup FSMC_Exported_Functions 671 * @{ 672 */ 673 674 void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank); 675 void FSMC_NANDDeInit(uint32_t FSMC_Bank); 676 void FSMC_PCCARDDeInit(void); 677 void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct); 678 void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct); 679 void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct); 680 void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct); 681 void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct); 682 void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct); 683 void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState); 684 void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState); 685 void FSMC_PCCARDCmd(FunctionalState NewState); 686 void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState); 687 uint32_t FSMC_GetECC(uint32_t FSMC_Bank); 688 void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState); 689 FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG); 690 void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG); 691 ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT); 692 void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT); 693 694 #ifdef __cplusplus 695 } 696 #endif 697 698 #endif /*__AIR32F10x_FSMC_H */ 699 /** 700 * @} 701 */ 702 703 /** 704 * @} 705 */ 706 707 /** 708 * @} 709 */ 710 711