1 /* Define to prevent recursive inclusion -------------------------------------*/ 2 #ifndef __AIR32F10x_SPI_H 3 #define __AIR32F10x_SPI_H 4 5 #ifdef __cplusplus 6 extern "C" { 7 #endif 8 9 /* Includes ------------------------------------------------------------------*/ 10 #include "air32f10x.h" 11 12 /** @addtogroup air32f10x_StdPeriph_Driver 13 * @{ 14 */ 15 16 /** @addtogroup SPI 17 * @{ 18 */ 19 20 /** @defgroup SPI_Exported_Types 21 * @{ 22 */ 23 24 /** 25 * @brief SPI Init structure definition 26 */ 27 28 typedef struct 29 { 30 uint16_t SPI_Direction; /*!< Specifies the SPI unidirectional or bidirectional data mode. 31 This parameter can be a value of @ref SPI_data_direction */ 32 33 uint16_t SPI_Mode; /*!< Specifies the SPI operating mode. 34 This parameter can be a value of @ref SPI_mode */ 35 36 uint16_t SPI_DataSize; /*!< Specifies the SPI data size. 37 This parameter can be a value of @ref SPI_data_size */ 38 39 uint16_t SPI_CPOL; /*!< Specifies the serial clock steady state. 40 This parameter can be a value of @ref SPI_Clock_Polarity */ 41 42 uint16_t SPI_CPHA; /*!< Specifies the clock active edge for the bit capture. 43 This parameter can be a value of @ref SPI_Clock_Phase */ 44 45 uint16_t SPI_NSS; /*!< Specifies whether the NSS signal is managed by 46 hardware (NSS pin) or by software using the SSI bit. 47 This parameter can be a value of @ref SPI_Slave_Select_management */ 48 49 uint16_t SPI_BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be 50 used to configure the transmit and receive SCK clock. 51 This parameter can be a value of @ref SPI_BaudRate_Prescaler. 52 @note The communication clock is derived from the master 53 clock. The slave clock does not need to be set. */ 54 55 uint16_t SPI_FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit. 56 This parameter can be a value of @ref SPI_MSB_LSB_transmission */ 57 58 uint16_t SPI_CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. */ 59 }SPI_InitTypeDef; 60 61 /** 62 * @brief I2S Init structure definition 63 */ 64 65 typedef struct 66 { 67 68 uint16_t I2S_Mode; /*!< Specifies the I2S operating mode. 69 This parameter can be a value of @ref I2S_Mode */ 70 71 uint16_t I2S_Standard; /*!< Specifies the standard used for the I2S communication. 72 This parameter can be a value of @ref I2S_Standard */ 73 74 uint16_t I2S_DataFormat; /*!< Specifies the data format for the I2S communication. 75 This parameter can be a value of @ref I2S_Data_Format */ 76 77 uint16_t I2S_MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not. 78 This parameter can be a value of @ref I2S_MCLK_Output */ 79 80 uint32_t I2S_AudioFreq; /*!< Specifies the frequency selected for the I2S communication. 81 This parameter can be a value of @ref I2S_Audio_Frequency */ 82 83 uint16_t I2S_CPOL; /*!< Specifies the idle state of the I2S clock. 84 This parameter can be a value of @ref I2S_Clock_Polarity */ 85 }I2S_InitTypeDef; 86 87 /** 88 * @} 89 */ 90 91 /** @defgroup SPI_Exported_Constants 92 * @{ 93 */ 94 95 #define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \ 96 ((PERIPH) == SPI2) || \ 97 ((PERIPH) == SPI3)) 98 99 #define IS_SPI_23_PERIPH(PERIPH) (((PERIPH) == SPI2) || \ 100 ((PERIPH) == SPI3)) 101 102 /** @defgroup SPI_data_direction 103 * @{ 104 */ 105 106 #define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000) 107 #define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400) 108 #define SPI_Direction_1Line_Rx ((uint16_t)0x8000) 109 #define SPI_Direction_1Line_Tx ((uint16_t)0xC000) 110 #define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \ 111 ((MODE) == SPI_Direction_2Lines_RxOnly) || \ 112 ((MODE) == SPI_Direction_1Line_Rx) || \ 113 ((MODE) == SPI_Direction_1Line_Tx)) 114 /** 115 * @} 116 */ 117 118 /** @defgroup SPI_mode 119 * @{ 120 */ 121 122 #define SPI_Mode_Master ((uint16_t)0x0104) 123 #define SPI_Mode_Slave ((uint16_t)0x0000) 124 #define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \ 125 ((MODE) == SPI_Mode_Slave)) 126 /** 127 * @} 128 */ 129 130 /** @defgroup SPI_data_size 131 * @{ 132 */ 133 134 #define SPI_DataSize_16b ((uint16_t)0x0800) 135 #define SPI_DataSize_8b ((uint16_t)0x0000) 136 #define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DataSize_16b) || \ 137 ((DATASIZE) == SPI_DataSize_8b)) 138 /** 139 * @} 140 */ 141 142 /** @defgroup SPI_Clock_Polarity 143 * @{ 144 */ 145 146 #define SPI_CPOL_Low ((uint16_t)0x0000) 147 #define SPI_CPOL_High ((uint16_t)0x0002) 148 #define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \ 149 ((CPOL) == SPI_CPOL_High)) 150 /** 151 * @} 152 */ 153 154 /** @defgroup SPI_Clock_Phase 155 * @{ 156 */ 157 158 #define SPI_CPHA_1Edge ((uint16_t)0x0000) 159 #define SPI_CPHA_2Edge ((uint16_t)0x0001) 160 #define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \ 161 ((CPHA) == SPI_CPHA_2Edge)) 162 /** 163 * @} 164 */ 165 166 /** @defgroup SPI_Slave_Select_management 167 * @{ 168 */ 169 170 #define SPI_NSS_Soft ((uint16_t)0x0200) 171 #define SPI_NSS_Hard ((uint16_t)0x0000) 172 #define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \ 173 ((NSS) == SPI_NSS_Hard)) 174 /** 175 * @} 176 */ 177 178 /** @defgroup SPI_BaudRate_Prescaler 179 * @{ 180 */ 181 182 #define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000) 183 #define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008) 184 #define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010) 185 #define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018) 186 #define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020) 187 #define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028) 188 #define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030) 189 #define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038) 190 #define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \ 191 ((PRESCALER) == SPI_BaudRatePrescaler_4) || \ 192 ((PRESCALER) == SPI_BaudRatePrescaler_8) || \ 193 ((PRESCALER) == SPI_BaudRatePrescaler_16) || \ 194 ((PRESCALER) == SPI_BaudRatePrescaler_32) || \ 195 ((PRESCALER) == SPI_BaudRatePrescaler_64) || \ 196 ((PRESCALER) == SPI_BaudRatePrescaler_128) || \ 197 ((PRESCALER) == SPI_BaudRatePrescaler_256)) 198 /** 199 * @} 200 */ 201 202 /** @defgroup SPI_MSB_LSB_transmission 203 * @{ 204 */ 205 206 #define SPI_FirstBit_MSB ((uint16_t)0x0000) 207 #define SPI_FirstBit_LSB ((uint16_t)0x0080) 208 #define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \ 209 ((BIT) == SPI_FirstBit_LSB)) 210 /** 211 * @} 212 */ 213 214 /** @defgroup I2S_Mode 215 * @{ 216 */ 217 218 #define I2S_Mode_SlaveTx ((uint16_t)0x0000) 219 #define I2S_Mode_SlaveRx ((uint16_t)0x0100) 220 #define I2S_Mode_MasterTx ((uint16_t)0x0200) 221 #define I2S_Mode_MasterRx ((uint16_t)0x0300) 222 #define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \ 223 ((MODE) == I2S_Mode_SlaveRx) || \ 224 ((MODE) == I2S_Mode_MasterTx) || \ 225 ((MODE) == I2S_Mode_MasterRx) ) 226 /** 227 * @} 228 */ 229 230 /** @defgroup I2S_Standard 231 * @{ 232 */ 233 234 #define I2S_Standard_Phillips ((uint16_t)0x0000) 235 #define I2S_Standard_MSB ((uint16_t)0x0010) 236 #define I2S_Standard_LSB ((uint16_t)0x0020) 237 #define I2S_Standard_PCMShort ((uint16_t)0x0030) 238 #define I2S_Standard_PCMLong ((uint16_t)0x00B0) 239 #define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || \ 240 ((STANDARD) == I2S_Standard_MSB) || \ 241 ((STANDARD) == I2S_Standard_LSB) || \ 242 ((STANDARD) == I2S_Standard_PCMShort) || \ 243 ((STANDARD) == I2S_Standard_PCMLong)) 244 /** 245 * @} 246 */ 247 248 /** @defgroup I2S_Data_Format 249 * @{ 250 */ 251 252 #define I2S_DataFormat_16b ((uint16_t)0x0000) 253 #define I2S_DataFormat_16bextended ((uint16_t)0x0001) 254 #define I2S_DataFormat_24b ((uint16_t)0x0003) 255 #define I2S_DataFormat_32b ((uint16_t)0x0005) 256 #define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || \ 257 ((FORMAT) == I2S_DataFormat_16bextended) || \ 258 ((FORMAT) == I2S_DataFormat_24b) || \ 259 ((FORMAT) == I2S_DataFormat_32b)) 260 /** 261 * @} 262 */ 263 264 /** @defgroup I2S_MCLK_Output 265 * @{ 266 */ 267 268 #define I2S_MCLKOutput_Enable ((uint16_t)0x0200) 269 #define I2S_MCLKOutput_Disable ((uint16_t)0x0000) 270 #define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || \ 271 ((OUTPUT) == I2S_MCLKOutput_Disable)) 272 /** 273 * @} 274 */ 275 276 /** @defgroup I2S_Audio_Frequency 277 * @{ 278 */ 279 280 #define I2S_AudioFreq_192k ((uint32_t)192000) 281 #define I2S_AudioFreq_96k ((uint32_t)96000) 282 #define I2S_AudioFreq_48k ((uint32_t)48000) 283 #define I2S_AudioFreq_44k ((uint32_t)44100) 284 #define I2S_AudioFreq_32k ((uint32_t)32000) 285 #define I2S_AudioFreq_22k ((uint32_t)22050) 286 #define I2S_AudioFreq_16k ((uint32_t)16000) 287 #define I2S_AudioFreq_11k ((uint32_t)11025) 288 #define I2S_AudioFreq_8k ((uint32_t)8000) 289 #define I2S_AudioFreq_Default ((uint32_t)2) 290 291 #define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AudioFreq_8k) && \ 292 ((FREQ) <= I2S_AudioFreq_192k)) || \ 293 ((FREQ) == I2S_AudioFreq_Default)) 294 /** 295 * @} 296 */ 297 298 /** @defgroup I2S_Clock_Polarity 299 * @{ 300 */ 301 302 #define I2S_CPOL_Low ((uint16_t)0x0000) 303 #define I2S_CPOL_High ((uint16_t)0x0008) 304 #define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || \ 305 ((CPOL) == I2S_CPOL_High)) 306 /** 307 * @} 308 */ 309 310 /** @defgroup SPI_I2S_DMA_transfer_requests 311 * @{ 312 */ 313 314 #define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002) 315 #define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001) 316 #define IS_SPI_I2S_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFFFC) == 0x00) && ((DMAREQ) != 0x00)) 317 /** 318 * @} 319 */ 320 321 /** @defgroup SPI_NSS_internal_software_management 322 * @{ 323 */ 324 325 #define SPI_NSSInternalSoft_Set ((uint16_t)0x0100) 326 #define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF) 327 #define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \ 328 ((INTERNAL) == SPI_NSSInternalSoft_Reset)) 329 /** 330 * @} 331 */ 332 333 /** @defgroup SPI_CRC_Transmit_Receive 334 * @{ 335 */ 336 337 #define SPI_CRC_Tx ((uint8_t)0x00) 338 #define SPI_CRC_Rx ((uint8_t)0x01) 339 #define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx)) 340 /** 341 * @} 342 */ 343 344 /** @defgroup SPI_direction_transmit_receive 345 * @{ 346 */ 347 348 #define SPI_Direction_Rx ((uint16_t)0xBFFF) 349 #define SPI_Direction_Tx ((uint16_t)0x4000) 350 #define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \ 351 ((DIRECTION) == SPI_Direction_Tx)) 352 /** 353 * @} 354 */ 355 356 /** @defgroup SPI_I2S_interrupts_definition 357 * @{ 358 */ 359 360 #define SPI_I2S_IT_TXE ((uint8_t)0x71) 361 #define SPI_I2S_IT_RXNE ((uint8_t)0x60) 362 #define SPI_I2S_IT_ERR ((uint8_t)0x50) 363 #define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \ 364 ((IT) == SPI_I2S_IT_RXNE) || \ 365 ((IT) == SPI_I2S_IT_ERR)) 366 #define SPI_I2S_IT_OVR ((uint8_t)0x56) 367 #define SPI_IT_MODF ((uint8_t)0x55) 368 #define SPI_IT_CRCERR ((uint8_t)0x54) 369 #define I2S_IT_UDR ((uint8_t)0x53) 370 #define IS_SPI_I2S_CLEAR_IT(IT) (((IT) == SPI_IT_CRCERR)) 371 #define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE) || ((IT) == SPI_I2S_IT_TXE) || \ 372 ((IT) == I2S_IT_UDR) || ((IT) == SPI_IT_CRCERR) || \ 373 ((IT) == SPI_IT_MODF) || ((IT) == SPI_I2S_IT_OVR)) 374 /** 375 * @} 376 */ 377 378 /** @defgroup SPI_I2S_flags_definition 379 * @{ 380 */ 381 382 #define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001) 383 #define SPI_I2S_FLAG_TXE ((uint16_t)0x0002) 384 #define I2S_FLAG_CHSIDE ((uint16_t)0x0004) 385 #define I2S_FLAG_UDR ((uint16_t)0x0008) 386 #define SPI_FLAG_CRCERR ((uint16_t)0x0010) 387 #define SPI_FLAG_MODF ((uint16_t)0x0020) 388 #define SPI_I2S_FLAG_OVR ((uint16_t)0x0040) 389 #define SPI_I2S_FLAG_BSY ((uint16_t)0x0080) 390 #define IS_SPI_I2S_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR)) 391 #define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \ 392 ((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \ 393 ((FLAG) == I2S_FLAG_UDR) || ((FLAG) == I2S_FLAG_CHSIDE) || \ 394 ((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE)) 395 /** 396 * @} 397 */ 398 399 /** @defgroup SPI_CRC_polynomial 400 * @{ 401 */ 402 403 #define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1) 404 /** 405 * @} 406 */ 407 408 /** 409 * @} 410 */ 411 412 /** @defgroup SPI_Exported_Macros 413 * @{ 414 */ 415 416 /** 417 * @} 418 */ 419 420 /** @defgroup SPI_Exported_Functions 421 * @{ 422 */ 423 424 void SPI_I2S_DeInit(SPI_TypeDef* SPIx); 425 void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct); 426 void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct); 427 void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct); 428 void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct); 429 void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); 430 void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); 431 void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState); 432 void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState); 433 void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data); 434 uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx); 435 void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft); 436 void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState); 437 void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize); 438 void SPI_TransmitCRC(SPI_TypeDef* SPIx); 439 void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState); 440 uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC); 441 uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx); 442 void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction); 443 FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); 444 void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); 445 ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); 446 void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); 447 448 #ifdef __cplusplus 449 } 450 #endif 451 452 #endif /*__AIR32F10x_SPI_H */ 453 /** 454 * @} 455 */ 456 457 /** 458 * @} 459 */ 460 461 /** 462 * @} 463 */ 464 465