1 /* Includes ------------------------------------------------------------------*/
2 #include "air32f10x_dma.h"
3 #include "air32f10x_rcc.h"
4
5
6 /** @defgroup DMA
7 * @brief DMA driver modules
8 * @{
9 */
10
11 /** @defgroup DMA_Private_TypesDefinitions
12 * @{
13 */
14 /**
15 * @}
16 */
17
18 /** @defgroup DMA_Private_Defines
19 * @{
20 */
21
22
23 /* DMA1 Channelx interrupt pending bit masks */
24 #define DMA1_Channel1_IT_Mask ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1))
25 #define DMA1_Channel2_IT_Mask ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2))
26 #define DMA1_Channel3_IT_Mask ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3))
27 #define DMA1_Channel4_IT_Mask ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4))
28 #define DMA1_Channel5_IT_Mask ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5))
29 #define DMA1_Channel6_IT_Mask ((uint32_t)(DMA_ISR_GIF6 | DMA_ISR_TCIF6 | DMA_ISR_HTIF6 | DMA_ISR_TEIF6))
30 #define DMA1_Channel7_IT_Mask ((uint32_t)(DMA_ISR_GIF7 | DMA_ISR_TCIF7 | DMA_ISR_HTIF7 | DMA_ISR_TEIF7))
31
32 /* DMA2 Channelx interrupt pending bit masks */
33 #define DMA2_Channel1_IT_Mask ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1))
34 #define DMA2_Channel2_IT_Mask ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2))
35 #define DMA2_Channel3_IT_Mask ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3))
36 #define DMA2_Channel4_IT_Mask ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4))
37 #define DMA2_Channel5_IT_Mask ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5))
38
39 /* DMA2 FLAG mask */
40 #define FLAG_Mask ((uint32_t)0x10000000)
41
42 /* DMA registers Masks */
43 #define CCR_CLEAR_Mask ((uint32_t)0xFFFF800F)
44
45 /**
46 * @}
47 */
48
49 /** @defgroup DMA_Private_Macros
50 * @{
51 */
52
53 /**
54 * @}
55 */
56
57 /** @defgroup DMA_Private_Variables
58 * @{
59 */
60
61 /**
62 * @}
63 */
64
65 /** @defgroup DMA_Private_FunctionPrototypes
66 * @{
67 */
68
69 /**
70 * @}
71 */
72
73 /** @defgroup DMA_Private_Functions
74 * @{
75 */
76
77 /**
78 * @brief Deinitializes the DMAy Channelx registers to their default reset
79 * values.
80 * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
81 * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
82 * @retval None
83 */
DMA_DeInit(DMA_Channel_TypeDef * DMAy_Channelx)84 void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx)
85 {
86 /* Check the parameters */
87 assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
88
89 /* Disable the selected DMAy Channelx */
90 DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN);
91
92 /* Reset DMAy Channelx control register */
93 DMAy_Channelx->CCR = 0;
94
95 /* Reset DMAy Channelx remaining bytes register */
96 DMAy_Channelx->CNDTR = 0;
97
98 /* Reset DMAy Channelx peripheral address register */
99 DMAy_Channelx->CPAR = 0;
100
101 /* Reset DMAy Channelx memory address register */
102 DMAy_Channelx->CMAR = 0;
103
104 if (DMAy_Channelx == DMA1_Channel1)
105 {
106 /* Reset interrupt pending bits for DMA1 Channel1 */
107 DMA1->IFCR |= DMA1_Channel1_IT_Mask;
108 }
109 else if (DMAy_Channelx == DMA1_Channel2)
110 {
111 /* Reset interrupt pending bits for DMA1 Channel2 */
112 DMA1->IFCR |= DMA1_Channel2_IT_Mask;
113 }
114 else if (DMAy_Channelx == DMA1_Channel3)
115 {
116 /* Reset interrupt pending bits for DMA1 Channel3 */
117 DMA1->IFCR |= DMA1_Channel3_IT_Mask;
118 }
119 else if (DMAy_Channelx == DMA1_Channel4)
120 {
121 /* Reset interrupt pending bits for DMA1 Channel4 */
122 DMA1->IFCR |= DMA1_Channel4_IT_Mask;
123 }
124 else if (DMAy_Channelx == DMA1_Channel5)
125 {
126 /* Reset interrupt pending bits for DMA1 Channel5 */
127 DMA1->IFCR |= DMA1_Channel5_IT_Mask;
128 }
129 else if (DMAy_Channelx == DMA1_Channel6)
130 {
131 /* Reset interrupt pending bits for DMA1 Channel6 */
132 DMA1->IFCR |= DMA1_Channel6_IT_Mask;
133 }
134 else if (DMAy_Channelx == DMA1_Channel7)
135 {
136 /* Reset interrupt pending bits for DMA1 Channel7 */
137 DMA1->IFCR |= DMA1_Channel7_IT_Mask;
138 }
139 else if (DMAy_Channelx == DMA2_Channel1)
140 {
141 /* Reset interrupt pending bits for DMA2 Channel1 */
142 DMA2->IFCR |= DMA2_Channel1_IT_Mask;
143 }
144 else if (DMAy_Channelx == DMA2_Channel2)
145 {
146 /* Reset interrupt pending bits for DMA2 Channel2 */
147 DMA2->IFCR |= DMA2_Channel2_IT_Mask;
148 }
149 else if (DMAy_Channelx == DMA2_Channel3)
150 {
151 /* Reset interrupt pending bits for DMA2 Channel3 */
152 DMA2->IFCR |= DMA2_Channel3_IT_Mask;
153 }
154 else if (DMAy_Channelx == DMA2_Channel4)
155 {
156 /* Reset interrupt pending bits for DMA2 Channel4 */
157 DMA2->IFCR |= DMA2_Channel4_IT_Mask;
158 }
159 else
160 {
161 if (DMAy_Channelx == DMA2_Channel5)
162 {
163 /* Reset interrupt pending bits for DMA2 Channel5 */
164 DMA2->IFCR |= DMA2_Channel5_IT_Mask;
165 }
166 }
167 }
168
169 /**
170 * @brief Initializes the DMAy Channelx according to the specified
171 * parameters in the DMA_InitStruct.
172 * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
173 * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
174 * @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure that
175 * contains the configuration information for the specified DMA Channel.
176 * @retval None
177 */
DMA_Init(DMA_Channel_TypeDef * DMAy_Channelx,DMA_InitTypeDef * DMA_InitStruct)178 void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct)
179 {
180 uint32_t tmpreg = 0;
181
182 /* Check the parameters */
183 assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
184 assert_param(IS_DMA_DIR(DMA_InitStruct->DMA_DIR));
185 assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize));
186 assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc));
187 assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc));
188 assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize));
189 assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize));
190 assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode));
191 assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority));
192 assert_param(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M));
193
194 /*--------------------------- DMAy Channelx CCR Configuration -----------------*/
195 /* Get the DMAy_Channelx CCR value */
196 tmpreg = DMAy_Channelx->CCR;
197 /* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */
198 tmpreg &= CCR_CLEAR_Mask;
199 /* Configure DMAy Channelx: data transfer, data size, priority level and mode */
200 /* Set DIR bit according to DMA_DIR value */
201 /* Set CIRC bit according to DMA_Mode value */
202 /* Set PINC bit according to DMA_PeripheralInc value */
203 /* Set MINC bit according to DMA_MemoryInc value */
204 /* Set PSIZE bits according to DMA_PeripheralDataSize value */
205 /* Set MSIZE bits according to DMA_MemoryDataSize value */
206 /* Set PL bits according to DMA_Priority value */
207 /* Set the MEM2MEM bit according to DMA_M2M value */
208 tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode |
209 DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc |
210 DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize |
211 DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M;
212
213 /* Write to DMAy Channelx CCR */
214 DMAy_Channelx->CCR = tmpreg;
215
216 /*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/
217 /* Write to DMAy Channelx CNDTR */
218 DMAy_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize;
219
220 /*--------------------------- DMAy Channelx CPAR Configuration ----------------*/
221 /* Write to DMAy Channelx CPAR */
222 DMAy_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr;
223
224 /*--------------------------- DMAy Channelx CMAR Configuration ----------------*/
225 /* Write to DMAy Channelx CMAR */
226 DMAy_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr;
227 }
228
229 /**
230 * @brief Fills each DMA_InitStruct member with its default value.
231 * @param DMA_InitStruct : pointer to a DMA_InitTypeDef structure which will
232 * be initialized.
233 * @retval None
234 */
DMA_StructInit(DMA_InitTypeDef * DMA_InitStruct)235 void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct)
236 {
237 /*-------------- Reset DMA init structure parameters values ------------------*/
238 /* Initialize the DMA_PeripheralBaseAddr member */
239 DMA_InitStruct->DMA_PeripheralBaseAddr = 0;
240 /* Initialize the DMA_MemoryBaseAddr member */
241 DMA_InitStruct->DMA_MemoryBaseAddr = 0;
242 /* Initialize the DMA_DIR member */
243 DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC;
244 /* Initialize the DMA_BufferSize member */
245 DMA_InitStruct->DMA_BufferSize = 0;
246 /* Initialize the DMA_PeripheralInc member */
247 DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable;
248 /* Initialize the DMA_MemoryInc member */
249 DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable;
250 /* Initialize the DMA_PeripheralDataSize member */
251 DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
252 /* Initialize the DMA_MemoryDataSize member */
253 DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
254 /* Initialize the DMA_Mode member */
255 DMA_InitStruct->DMA_Mode = DMA_Mode_Normal;
256 /* Initialize the DMA_Priority member */
257 DMA_InitStruct->DMA_Priority = DMA_Priority_Low;
258 /* Initialize the DMA_M2M member */
259 DMA_InitStruct->DMA_M2M = DMA_M2M_Disable;
260 }
261
262 /**
263 * @brief Enables or disables the specified DMAy Channelx.
264 * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
265 * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
266 * @param NewState: new state of the DMAy Channelx.
267 * This parameter can be: ENABLE or DISABLE.
268 * @retval None
269 */
DMA_Cmd(DMA_Channel_TypeDef * DMAy_Channelx,FunctionalState NewState)270 void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState)
271 {
272 /* Check the parameters */
273 assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
274 assert_param(IS_FUNCTIONAL_STATE(NewState));
275
276 if (NewState != DISABLE)
277 {
278 /* Enable the selected DMAy Channelx */
279 DMAy_Channelx->CCR |= DMA_CCR1_EN;
280 }
281 else
282 {
283 /* Disable the selected DMAy Channelx */
284 DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN);
285 }
286 }
287
288 /**
289 * @brief Enables or disables the specified DMAy Channelx interrupts.
290 * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
291 * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
292 * @param DMA_IT: specifies the DMA interrupts sources to be enabled
293 * or disabled.
294 * This parameter can be any combination of the following values:
295 * @arg DMA_IT_TC: Transfer complete interrupt mask
296 * @arg DMA_IT_HT: Half transfer interrupt mask
297 * @arg DMA_IT_TE: Transfer error interrupt mask
298 * @param NewState: new state of the specified DMA interrupts.
299 * This parameter can be: ENABLE or DISABLE.
300 * @retval None
301 */
DMA_ITConfig(DMA_Channel_TypeDef * DMAy_Channelx,uint32_t DMA_IT,FunctionalState NewState)302 void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState)
303 {
304 /* Check the parameters */
305 assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
306 assert_param(IS_DMA_CONFIG_IT(DMA_IT));
307 assert_param(IS_FUNCTIONAL_STATE(NewState));
308 if (NewState != DISABLE)
309 {
310 /* Enable the selected DMA interrupts */
311 DMAy_Channelx->CCR |= DMA_IT;
312 }
313 else
314 {
315 /* Disable the selected DMA interrupts */
316 DMAy_Channelx->CCR &= ~DMA_IT;
317 }
318 }
319
320 /**
321 * @brief Sets the number of data units in the current DMAy Channelx transfer.
322 * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
323 * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
324 * @param DataNumber: The number of data units in the current DMAy Channelx
325 * transfer.
326 * @note This function can only be used when the DMAy_Channelx is disabled.
327 * @retval None.
328 */
DMA_SetCurrDataCounter(DMA_Channel_TypeDef * DMAy_Channelx,uint16_t DataNumber)329 void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber)
330 {
331 /* Check the parameters */
332 assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
333
334 /*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/
335 /* Write to DMAy Channelx CNDTR */
336 DMAy_Channelx->CNDTR = DataNumber;
337 }
338
339 /**
340 * @brief Returns the number of remaining data units in the current
341 * DMAy Channelx transfer.
342 * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
343 * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
344 * @retval The number of remaining data units in the current DMAy Channelx
345 * transfer.
346 */
DMA_GetCurrDataCounter(DMA_Channel_TypeDef * DMAy_Channelx)347 uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx)
348 {
349 /* Check the parameters */
350 assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
351 /* Return the number of remaining data units for DMAy Channelx */
352 return ((uint16_t)(DMAy_Channelx->CNDTR));
353 }
354
355 /**
356 * @brief Checks whether the specified DMAy Channelx flag is set or not.
357 * @param DMAy_FLAG: specifies the flag to check.
358 * This parameter can be one of the following values:
359 * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.
360 * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
361 * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
362 * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
363 * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.
364 * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
365 * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
366 * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
367 * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.
368 * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
369 * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
370 * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
371 * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.
372 * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
373 * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
374 * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
375 * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.
376 * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
377 * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
378 * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
379 * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag.
380 * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
381 * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
382 * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.
383 * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag.
384 * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
385 * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
386 * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.
387 * @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag.
388 * @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.
389 * @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.
390 * @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag.
391 * @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag.
392 * @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.
393 * @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.
394 * @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag.
395 * @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag.
396 * @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.
397 * @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.
398 * @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag.
399 * @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag.
400 * @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.
401 * @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.
402 * @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag.
403 * @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag.
404 * @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.
405 * @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.
406 * @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag.
407 * @retval The new state of DMAy_FLAG (SET or RESET).
408 */
DMA_GetFlagStatus(uint32_t DMAy_FLAG)409 FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG)
410 {
411 FlagStatus bitstatus = RESET;
412 uint32_t tmpreg = 0;
413
414 /* Check the parameters */
415 assert_param(IS_DMA_GET_FLAG(DMAy_FLAG));
416
417 /* Calculate the used DMAy */
418 if ((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET)
419 {
420 /* Get DMA2 ISR register value */
421 tmpreg = DMA2->ISR ;
422 }
423 else
424 {
425 /* Get DMA1 ISR register value */
426 tmpreg = DMA1->ISR ;
427 }
428
429 /* Check the status of the specified DMAy flag */
430 if ((tmpreg & DMAy_FLAG) != (uint32_t)RESET)
431 {
432 /* DMAy_FLAG is set */
433 bitstatus = SET;
434 }
435 else
436 {
437 /* DMAy_FLAG is reset */
438 bitstatus = RESET;
439 }
440
441 /* Return the DMAy_FLAG status */
442 return bitstatus;
443 }
444
445 /**
446 * @brief Clears the DMAy Channelx's pending flags.
447 * @param DMAy_FLAG: specifies the flag to clear.
448 * This parameter can be any combination (for the same DMA) of the following values:
449 * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.
450 * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
451 * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
452 * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
453 * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.
454 * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
455 * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
456 * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
457 * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.
458 * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
459 * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
460 * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
461 * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.
462 * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
463 * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
464 * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
465 * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.
466 * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
467 * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
468 * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
469 * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag.
470 * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
471 * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
472 * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.
473 * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag.
474 * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
475 * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
476 * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.
477 * @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag.
478 * @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.
479 * @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.
480 * @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag.
481 * @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag.
482 * @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.
483 * @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.
484 * @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag.
485 * @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag.
486 * @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.
487 * @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.
488 * @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag.
489 * @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag.
490 * @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.
491 * @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.
492 * @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag.
493 * @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag.
494 * @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.
495 * @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.
496 * @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag.
497 * @retval None
498 */
DMA_ClearFlag(uint32_t DMAy_FLAG)499 void DMA_ClearFlag(uint32_t DMAy_FLAG)
500 {
501 /* Check the parameters */
502 assert_param(IS_DMA_CLEAR_FLAG(DMAy_FLAG));
503
504 /* Calculate the used DMAy */
505 if ((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET)
506 {
507 /* Clear the selected DMAy flags */
508 DMA2->IFCR = DMAy_FLAG;
509 }
510 else
511 {
512 /* Clear the selected DMAy flags */
513 DMA1->IFCR = DMAy_FLAG;
514 }
515 }
516
517 /**
518 * @brief Checks whether the specified DMAy Channelx interrupt has occurred or not.
519 * @param DMAy_IT: specifies the DMAy interrupt source to check.
520 * This parameter can be one of the following values:
521 * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.
522 * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
523 * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
524 * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
525 * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.
526 * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
527 * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
528 * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
529 * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.
530 * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
531 * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
532 * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
533 * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.
534 * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
535 * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
536 * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
537 * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.
538 * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
539 * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
540 * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
541 * @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt.
542 * @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.
543 * @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.
544 * @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.
545 * @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt.
546 * @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.
547 * @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.
548 * @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.
549 * @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt.
550 * @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt.
551 * @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt.
552 * @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt.
553 * @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt.
554 * @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt.
555 * @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt.
556 * @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt.
557 * @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt.
558 * @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt.
559 * @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt.
560 * @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt.
561 * @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt.
562 * @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt.
563 * @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt.
564 * @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt.
565 * @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt.
566 * @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt.
567 * @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt.
568 * @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt.
569 * @retval The new state of DMAy_IT (SET or RESET).
570 */
DMA_GetITStatus(uint32_t DMAy_IT)571 ITStatus DMA_GetITStatus(uint32_t DMAy_IT)
572 {
573 ITStatus bitstatus = RESET;
574 uint32_t tmpreg = 0;
575
576 /* Check the parameters */
577 assert_param(IS_DMA_GET_IT(DMAy_IT));
578
579 /* Calculate the used DMA */
580 if ((DMAy_IT & FLAG_Mask) != (uint32_t)RESET)
581 {
582 /* Get DMA2 ISR register value */
583 tmpreg = DMA2->ISR;
584 }
585 else
586 {
587 /* Get DMA1 ISR register value */
588 tmpreg = DMA1->ISR;
589 }
590
591 /* Check the status of the specified DMAy interrupt */
592 if ((tmpreg & DMAy_IT) != (uint32_t)RESET)
593 {
594 /* DMAy_IT is set */
595 bitstatus = SET;
596 }
597 else
598 {
599 /* DMAy_IT is reset */
600 bitstatus = RESET;
601 }
602 /* Return the DMA_IT status */
603 return bitstatus;
604 }
605
606 /**
607 * @brief Clears the DMAy Channelx's interrupt pending bits.
608 * @param DMAy_IT: specifies the DMAy interrupt pending bit to clear.
609 * This parameter can be any combination (for the same DMA) of the following values:
610 * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.
611 * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
612 * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
613 * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
614 * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.
615 * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
616 * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
617 * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
618 * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.
619 * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
620 * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
621 * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
622 * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.
623 * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
624 * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
625 * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
626 * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.
627 * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
628 * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
629 * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
630 * @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt.
631 * @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.
632 * @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.
633 * @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.
634 * @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt.
635 * @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.
636 * @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.
637 * @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.
638 * @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt.
639 * @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt.
640 * @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt.
641 * @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt.
642 * @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt.
643 * @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt.
644 * @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt.
645 * @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt.
646 * @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt.
647 * @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt.
648 * @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt.
649 * @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt.
650 * @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt.
651 * @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt.
652 * @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt.
653 * @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt.
654 * @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt.
655 * @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt.
656 * @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt.
657 * @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt.
658 * @retval None
659 */
DMA_ClearITPendingBit(uint32_t DMAy_IT)660 void DMA_ClearITPendingBit(uint32_t DMAy_IT)
661 {
662 /* Check the parameters */
663 assert_param(IS_DMA_CLEAR_IT(DMAy_IT));
664
665 /* Calculate the used DMAy */
666 if ((DMAy_IT & FLAG_Mask) != (uint32_t)RESET)
667 {
668 /* Clear the selected DMAy interrupt pending bits */
669 DMA2->IFCR = DMAy_IT;
670 }
671 else
672 {
673 /* Clear the selected DMAy interrupt pending bits */
674 DMA1->IFCR = DMAy_IT;
675 }
676 }
677
678 /**
679 * @}
680 */
681
682 /**
683 * @}
684 */
685
686 /**
687 * @}
688 */
689
690