1 /* Includes ------------------------------------------------------------------*/
2 #include "air32f10x_fsmc.h"
3 #include "air32f10x_rcc.h"
4
5 /** @addtogroup STM32F10x_StdPeriph_Driver
6 * @{
7 */
8
9 /** @defgroup FSMC
10 * @brief FSMC driver modules
11 * @{
12 */
13
14 /** @defgroup FSMC_Private_TypesDefinitions
15 * @{
16 */
17 /**
18 * @}
19 */
20
21 /** @defgroup FSMC_Private_Defines
22 * @{
23 */
24
25 /* --------------------- FSMC registers bit mask ---------------------------- */
26
27 /* FSMC BCRx Mask */
28 #define BCR_MBKEN_Set ((uint32_t)0x00000001)
29 #define BCR_MBKEN_Reset ((uint32_t)0x000FFFFE)
30 #define BCR_FACCEN_Set ((uint32_t)0x00000040)
31
32 /* FSMC PCRx Mask */
33 #define PCR_PBKEN_Set ((uint32_t)0x00000004)
34 #define PCR_PBKEN_Reset ((uint32_t)0x000FFFFB)
35 #define PCR_ECCEN_Set ((uint32_t)0x00000040)
36 #define PCR_ECCEN_Reset ((uint32_t)0x000FFFBF)
37 #define PCR_MemoryType_NAND ((uint32_t)0x00000008)
38 /**
39 * @}
40 */
41
42 /** @defgroup FSMC_Private_Macros
43 * @{
44 */
45
46 /**
47 * @}
48 */
49
50 /** @defgroup FSMC_Private_Variables
51 * @{
52 */
53
54 /**
55 * @}
56 */
57
58 /** @defgroup FSMC_Private_FunctionPrototypes
59 * @{
60 */
61
62 /**
63 * @}
64 */
65
66 /** @defgroup FSMC_Private_Functions
67 * @{
68 */
69
70 /**
71 * @brief Deinitializes the FSMC NOR/SRAM Banks registers to their default
72 * reset values.
73 * @param FSMC_Bank: specifies the FSMC Bank to be used
74 * This parameter can be one of the following values:
75 * @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1
76 * @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2
77 * @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3
78 * @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4
79 * @retval None
80 */
FSMC_NORSRAMDeInit(uint32_t FSMC_Bank)81 void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank)
82 {
83 /* Check the parameter */
84 assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));
85
86 /* FSMC_Bank1_NORSRAM1 */
87 if(FSMC_Bank == FSMC_Bank1_NORSRAM1)
88 {
89 FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030DB;
90 }
91 /* FSMC_Bank1_NORSRAM2, FSMC_Bank1_NORSRAM3 or FSMC_Bank1_NORSRAM4 */
92 else
93 {
94 FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030D2;
95 }
96 FSMC_Bank1->BTCR[FSMC_Bank + 1] = 0x0FFFFFFF;
97 FSMC_Bank1E->BWTR[FSMC_Bank] = 0x0FFFFFFF;
98 }
99
100 /**
101 * @brief Deinitializes the FSMC NAND Banks registers to their default reset values.
102 * @param FSMC_Bank: specifies the FSMC Bank to be used
103 * This parameter can be one of the following values:
104 * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
105 * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
106 * @retval None
107 */
FSMC_NANDDeInit(uint32_t FSMC_Bank)108 void FSMC_NANDDeInit(uint32_t FSMC_Bank)
109 {
110 /* Check the parameter */
111 assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
112
113 if(FSMC_Bank == FSMC_Bank2_NAND)
114 {
115 /* Set the FSMC_Bank2 registers to their reset values */
116 FSMC_Bank2->PCR2 = 0x00000018;
117 FSMC_Bank2->SR2 = 0x00000040;
118 FSMC_Bank2->PMEM2 = 0xFCFCFCFC;
119 FSMC_Bank2->PATT2 = 0xFCFCFCFC;
120 }
121 /* FSMC_Bank3_NAND */
122 else
123 {
124 /* Set the FSMC_Bank3 registers to their reset values */
125 FSMC_Bank3->PCR3 = 0x00000018;
126 FSMC_Bank3->SR3 = 0x00000040;
127 FSMC_Bank3->PMEM3 = 0xFCFCFCFC;
128 FSMC_Bank3->PATT3 = 0xFCFCFCFC;
129 }
130 }
131
132 /**
133 * @brief Deinitializes the FSMC PCCARD Bank registers to their default reset values.
134 * @param None
135 * @retval None
136 */
FSMC_PCCARDDeInit(void)137 void FSMC_PCCARDDeInit(void)
138 {
139 /* Set the FSMC_Bank4 registers to their reset values */
140 FSMC_Bank4->PCR4 = 0x00000018;
141 FSMC_Bank4->SR4 = 0x00000000;
142 FSMC_Bank4->PMEM4 = 0xFCFCFCFC;
143 FSMC_Bank4->PATT4 = 0xFCFCFCFC;
144 FSMC_Bank4->PIO4 = 0xFCFCFCFC;
145 }
146
147 /**
148 * @brief Initializes the FSMC NOR/SRAM Banks according to the specified
149 * parameters in the FSMC_NORSRAMInitStruct.
150 * @param FSMC_NORSRAMInitStruct : pointer to a FSMC_NORSRAMInitTypeDef
151 * structure that contains the configuration information for
152 * the FSMC NOR/SRAM specified Banks.
153 * @retval None
154 */
FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef * FSMC_NORSRAMInitStruct)155 void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
156 {
157 /* Check the parameters */
158 assert_param(IS_FSMC_NORSRAM_BANK(FSMC_NORSRAMInitStruct->FSMC_Bank));
159 assert_param(IS_FSMC_MUX(FSMC_NORSRAMInitStruct->FSMC_DataAddressMux));
160 assert_param(IS_FSMC_MEMORY(FSMC_NORSRAMInitStruct->FSMC_MemoryType));
161 assert_param(IS_FSMC_MEMORY_WIDTH(FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth));
162 assert_param(IS_FSMC_BURSTMODE(FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode));
163 assert_param(IS_FSMC_ASYNWAIT(FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait));
164 assert_param(IS_FSMC_WAIT_POLARITY(FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity));
165 assert_param(IS_FSMC_WRAP_MODE(FSMC_NORSRAMInitStruct->FSMC_WrapMode));
166 assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive));
167 assert_param(IS_FSMC_WRITE_OPERATION(FSMC_NORSRAMInitStruct->FSMC_WriteOperation));
168 assert_param(IS_FSMC_WAITE_SIGNAL(FSMC_NORSRAMInitStruct->FSMC_WaitSignal));
169 assert_param(IS_FSMC_EXTENDED_MODE(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode));
170 assert_param(IS_FSMC_WRITE_BURST(FSMC_NORSRAMInitStruct->FSMC_WriteBurst));
171 assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime));
172 assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime));
173 assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime));
174 assert_param(IS_FSMC_TURNAROUND_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration));
175 assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision));
176 assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency));
177 assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode));
178
179 /* Bank1 NOR/SRAM control register configuration */
180 FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] =
181 (uint32_t)FSMC_NORSRAMInitStruct->FSMC_DataAddressMux |
182 FSMC_NORSRAMInitStruct->FSMC_MemoryType |
183 FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth |
184 FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode |
185 FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait |
186 FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity |
187 FSMC_NORSRAMInitStruct->FSMC_WrapMode |
188 FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive |
189 FSMC_NORSRAMInitStruct->FSMC_WriteOperation |
190 FSMC_NORSRAMInitStruct->FSMC_WaitSignal |
191 FSMC_NORSRAMInitStruct->FSMC_ExtendedMode |
192 FSMC_NORSRAMInitStruct->FSMC_WriteBurst;
193
194 if(FSMC_NORSRAMInitStruct->FSMC_MemoryType == FSMC_MemoryType_NOR)
195 {
196 FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] |= (uint32_t)BCR_FACCEN_Set;
197 }
198
199 /* Bank1 NOR/SRAM timing register configuration */
200 FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank+1] =
201 (uint32_t)FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime |
202 (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime << 4) |
203 (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime << 8) |
204 (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration << 16) |
205 (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision << 20) |
206 (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency << 24) |
207 FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode;
208
209
210 /* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */
211 if(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode == FSMC_ExtendedMode_Enable)
212 {
213 assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime));
214 assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime));
215 assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime));
216 assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision));
217 assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency));
218 assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode));
219 FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] =
220 (uint32_t)FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime |
221 (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime << 4 )|
222 (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime << 8) |
223 (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision << 20) |
224 (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency << 24) |
225 FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode;
226 }
227 else
228 {
229 FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 0x0FFFFFFF;
230 }
231 }
232
233 /**
234 * @brief Initializes the FSMC NAND Banks according to the specified
235 * parameters in the FSMC_NANDInitStruct.
236 * @param FSMC_NANDInitStruct : pointer to a FSMC_NANDInitTypeDef
237 * structure that contains the configuration information for the FSMC
238 * NAND specified Banks.
239 * @retval None
240 */
FSMC_NANDInit(FSMC_NANDInitTypeDef * FSMC_NANDInitStruct)241 void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct)
242 {
243 uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000;
244
245 /* Check the parameters */
246 assert_param( IS_FSMC_NAND_BANK(FSMC_NANDInitStruct->FSMC_Bank));
247 assert_param( IS_FSMC_WAIT_FEATURE(FSMC_NANDInitStruct->FSMC_Waitfeature));
248 assert_param( IS_FSMC_MEMORY_WIDTH(FSMC_NANDInitStruct->FSMC_MemoryDataWidth));
249 assert_param( IS_FSMC_ECC_STATE(FSMC_NANDInitStruct->FSMC_ECC));
250 assert_param( IS_FSMC_ECCPAGE_SIZE(FSMC_NANDInitStruct->FSMC_ECCPageSize));
251 assert_param( IS_FSMC_TCLR_TIME(FSMC_NANDInitStruct->FSMC_TCLRSetupTime));
252 assert_param( IS_FSMC_TAR_TIME(FSMC_NANDInitStruct->FSMC_TARSetupTime));
253 assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime));
254 assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime));
255 assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime));
256 assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime));
257 assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime));
258 assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime));
259 assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime));
260 assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime));
261
262 /* Set the tmppcr value according to FSMC_NANDInitStruct parameters */
263 tmppcr = (uint32_t)FSMC_NANDInitStruct->FSMC_Waitfeature |
264 PCR_MemoryType_NAND |
265 FSMC_NANDInitStruct->FSMC_MemoryDataWidth |
266 FSMC_NANDInitStruct->FSMC_ECC |
267 FSMC_NANDInitStruct->FSMC_ECCPageSize |
268 (FSMC_NANDInitStruct->FSMC_TCLRSetupTime << 9 )|
269 (FSMC_NANDInitStruct->FSMC_TARSetupTime << 13);
270
271 /* Set tmppmem value according to FSMC_CommonSpaceTimingStructure parameters */
272 tmppmem = (uint32_t)FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |
273 (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
274 (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
275 (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24);
276
277 /* Set tmppatt value according to FSMC_AttributeSpaceTimingStructure parameters */
278 tmppatt = (uint32_t)FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime |
279 (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
280 (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
281 (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24);
282
283 if(FSMC_NANDInitStruct->FSMC_Bank == FSMC_Bank2_NAND)
284 {
285 /* FSMC_Bank2_NAND registers configuration */
286 FSMC_Bank2->PCR2 = tmppcr;
287 FSMC_Bank2->PMEM2 = tmppmem;
288 FSMC_Bank2->PATT2 = tmppatt;
289 }
290 else
291 {
292 /* FSMC_Bank3_NAND registers configuration */
293 FSMC_Bank3->PCR3 = tmppcr;
294 FSMC_Bank3->PMEM3 = tmppmem;
295 FSMC_Bank3->PATT3 = tmppatt;
296 }
297 }
298
299 /**
300 * @brief Initializes the FSMC PCCARD Bank according to the specified
301 * parameters in the FSMC_PCCARDInitStruct.
302 * @param FSMC_PCCARDInitStruct : pointer to a FSMC_PCCARDInitTypeDef
303 * structure that contains the configuration information for the FSMC
304 * PCCARD Bank.
305 * @retval None
306 */
FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef * FSMC_PCCARDInitStruct)307 void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct)
308 {
309 /* Check the parameters */
310 assert_param(IS_FSMC_WAIT_FEATURE(FSMC_PCCARDInitStruct->FSMC_Waitfeature));
311 assert_param(IS_FSMC_TCLR_TIME(FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime));
312 assert_param(IS_FSMC_TAR_TIME(FSMC_PCCARDInitStruct->FSMC_TARSetupTime));
313
314 assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime));
315 assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime));
316 assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime));
317 assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime));
318
319 assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime));
320 assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime));
321 assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime));
322 assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime));
323 assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime));
324 assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime));
325 assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime));
326 assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime));
327
328 /* Set the PCR4 register value according to FSMC_PCCARDInitStruct parameters */
329 FSMC_Bank4->PCR4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_Waitfeature |
330 FSMC_MemoryDataWidth_16b |
331 (FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime << 9) |
332 (FSMC_PCCARDInitStruct->FSMC_TARSetupTime << 13);
333
334 /* Set PMEM4 register value according to FSMC_CommonSpaceTimingStructure parameters */
335 FSMC_Bank4->PMEM4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |
336 (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
337 (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
338 (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24);
339
340 /* Set PATT4 register value according to FSMC_AttributeSpaceTimingStructure parameters */
341 FSMC_Bank4->PATT4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime |
342 (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
343 (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
344 (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24);
345
346 /* Set PIO4 register value according to FSMC_IOSpaceTimingStructure parameters */
347 FSMC_Bank4->PIO4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime |
348 (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
349 (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
350 (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime << 24);
351 }
352
353 /**
354 * @brief Fills each FSMC_NORSRAMInitStruct member with its default value.
355 * @param FSMC_NORSRAMInitStruct: pointer to a FSMC_NORSRAMInitTypeDef
356 * structure which will be initialized.
357 * @retval None
358 */
FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef * FSMC_NORSRAMInitStruct)359 void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
360 {
361 /* Reset NOR/SRAM Init structure parameters values */
362 FSMC_NORSRAMInitStruct->FSMC_Bank = FSMC_Bank1_NORSRAM1;
363 FSMC_NORSRAMInitStruct->FSMC_DataAddressMux = FSMC_DataAddressMux_Enable;
364 FSMC_NORSRAMInitStruct->FSMC_MemoryType = FSMC_MemoryType_SRAM;
365 FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
366 FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
367 FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
368 FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
369 FSMC_NORSRAMInitStruct->FSMC_WrapMode = FSMC_WrapMode_Disable;
370 FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
371 FSMC_NORSRAMInitStruct->FSMC_WriteOperation = FSMC_WriteOperation_Enable;
372 FSMC_NORSRAMInitStruct->FSMC_WaitSignal = FSMC_WaitSignal_Enable;
373 FSMC_NORSRAMInitStruct->FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
374 FSMC_NORSRAMInitStruct->FSMC_WriteBurst = FSMC_WriteBurst_Disable;
375 FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime = 0xF;
376 FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime = 0xF;
377 FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime = 0xFF;
378 FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;
379 FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision = 0xF;
380 FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency = 0xF;
381 FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A;
382 FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime = 0xF;
383 FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime = 0xF;
384 FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime = 0xFF;
385 FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;
386 FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision = 0xF;
387 FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency = 0xF;
388 FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A;
389 }
390
391 /**
392 * @brief Fills each FSMC_NANDInitStruct member with its default value.
393 * @param FSMC_NANDInitStruct: pointer to a FSMC_NANDInitTypeDef
394 * structure which will be initialized.
395 * @retval None
396 */
FSMC_NANDStructInit(FSMC_NANDInitTypeDef * FSMC_NANDInitStruct)397 void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct)
398 {
399 /* Reset NAND Init structure parameters values */
400 FSMC_NANDInitStruct->FSMC_Bank = FSMC_Bank2_NAND;
401 FSMC_NANDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable;
402 FSMC_NANDInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
403 FSMC_NANDInitStruct->FSMC_ECC = FSMC_ECC_Disable;
404 FSMC_NANDInitStruct->FSMC_ECCPageSize = FSMC_ECCPageSize_256Bytes;
405 FSMC_NANDInitStruct->FSMC_TCLRSetupTime = 0x0;
406 FSMC_NANDInitStruct->FSMC_TARSetupTime = 0x0;
407 FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC;
408 FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
409 FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
410 FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
411 FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC;
412 FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
413 FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
414 FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
415 }
416
417 /**
418 * @brief Fills each FSMC_PCCARDInitStruct member with its default value.
419 * @param FSMC_PCCARDInitStruct: pointer to a FSMC_PCCARDInitTypeDef
420 * structure which will be initialized.
421 * @retval None
422 */
FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef * FSMC_PCCARDInitStruct)423 void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct)
424 {
425 /* Reset PCCARD Init structure parameters values */
426 FSMC_PCCARDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable;
427 FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime = 0x0;
428 FSMC_PCCARDInitStruct->FSMC_TARSetupTime = 0x0;
429 FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC;
430 FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
431 FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
432 FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
433 FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC;
434 FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
435 FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
436 FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
437 FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime = 0xFC;
438 FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
439 FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
440 FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
441 }
442
443 /**
444 * @brief Enables or disables the specified NOR/SRAM Memory Bank.
445 * @param FSMC_Bank: specifies the FSMC Bank to be used
446 * This parameter can be one of the following values:
447 * @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1
448 * @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2
449 * @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3
450 * @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4
451 * @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE.
452 * @retval None
453 */
FSMC_NORSRAMCmd(uint32_t FSMC_Bank,FunctionalState NewState)454 void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState)
455 {
456 assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));
457 assert_param(IS_FUNCTIONAL_STATE(NewState));
458
459 if (NewState != DISABLE)
460 {
461 /* Enable the selected NOR/SRAM Bank by setting the PBKEN bit in the BCRx register */
462 FSMC_Bank1->BTCR[FSMC_Bank] |= BCR_MBKEN_Set;
463 }
464 else
465 {
466 /* Disable the selected NOR/SRAM Bank by clearing the PBKEN bit in the BCRx register */
467 FSMC_Bank1->BTCR[FSMC_Bank] &= BCR_MBKEN_Reset;
468 }
469 }
470
471 /**
472 * @brief Enables or disables the specified NAND Memory Bank.
473 * @param FSMC_Bank: specifies the FSMC Bank to be used
474 * This parameter can be one of the following values:
475 * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
476 * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
477 * @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE.
478 * @retval None
479 */
FSMC_NANDCmd(uint32_t FSMC_Bank,FunctionalState NewState)480 void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState)
481 {
482 assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
483 assert_param(IS_FUNCTIONAL_STATE(NewState));
484
485 if (NewState != DISABLE)
486 {
487 /* Enable the selected NAND Bank by setting the PBKEN bit in the PCRx register */
488 if(FSMC_Bank == FSMC_Bank2_NAND)
489 {
490 FSMC_Bank2->PCR2 |= PCR_PBKEN_Set;
491 }
492 else
493 {
494 FSMC_Bank3->PCR3 |= PCR_PBKEN_Set;
495 }
496 }
497 else
498 {
499 /* Disable the selected NAND Bank by clearing the PBKEN bit in the PCRx register */
500 if(FSMC_Bank == FSMC_Bank2_NAND)
501 {
502 FSMC_Bank2->PCR2 &= PCR_PBKEN_Reset;
503 }
504 else
505 {
506 FSMC_Bank3->PCR3 &= PCR_PBKEN_Reset;
507 }
508 }
509 }
510
511 /**
512 * @brief Enables or disables the PCCARD Memory Bank.
513 * @param NewState: new state of the PCCARD Memory Bank.
514 * This parameter can be: ENABLE or DISABLE.
515 * @retval None
516 */
FSMC_PCCARDCmd(FunctionalState NewState)517 void FSMC_PCCARDCmd(FunctionalState NewState)
518 {
519 assert_param(IS_FUNCTIONAL_STATE(NewState));
520
521 if (NewState != DISABLE)
522 {
523 /* Enable the PCCARD Bank by setting the PBKEN bit in the PCR4 register */
524 FSMC_Bank4->PCR4 |= PCR_PBKEN_Set;
525 }
526 else
527 {
528 /* Disable the PCCARD Bank by clearing the PBKEN bit in the PCR4 register */
529 FSMC_Bank4->PCR4 &= PCR_PBKEN_Reset;
530 }
531 }
532
533 /**
534 * @brief Enables or disables the FSMC NAND ECC feature.
535 * @param FSMC_Bank: specifies the FSMC Bank to be used
536 * This parameter can be one of the following values:
537 * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
538 * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
539 * @param NewState: new state of the FSMC NAND ECC feature.
540 * This parameter can be: ENABLE or DISABLE.
541 * @retval None
542 */
FSMC_NANDECCCmd(uint32_t FSMC_Bank,FunctionalState NewState)543 void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState)
544 {
545 assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
546 assert_param(IS_FUNCTIONAL_STATE(NewState));
547
548 if (NewState != DISABLE)
549 {
550 /* Enable the selected NAND Bank ECC function by setting the ECCEN bit in the PCRx register */
551 if(FSMC_Bank == FSMC_Bank2_NAND)
552 {
553 FSMC_Bank2->PCR2 |= PCR_ECCEN_Set;
554 }
555 else
556 {
557 FSMC_Bank3->PCR3 |= PCR_ECCEN_Set;
558 }
559 }
560 else
561 {
562 /* Disable the selected NAND Bank ECC function by clearing the ECCEN bit in the PCRx register */
563 if(FSMC_Bank == FSMC_Bank2_NAND)
564 {
565 FSMC_Bank2->PCR2 &= PCR_ECCEN_Reset;
566 }
567 else
568 {
569 FSMC_Bank3->PCR3 &= PCR_ECCEN_Reset;
570 }
571 }
572 }
573
574 /**
575 * @brief Returns the error correction code register value.
576 * @param FSMC_Bank: specifies the FSMC Bank to be used
577 * This parameter can be one of the following values:
578 * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
579 * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
580 * @retval The Error Correction Code (ECC) value.
581 */
FSMC_GetECC(uint32_t FSMC_Bank)582 uint32_t FSMC_GetECC(uint32_t FSMC_Bank)
583 {
584 uint32_t eccval = 0x00000000;
585
586 if(FSMC_Bank == FSMC_Bank2_NAND)
587 {
588 /* Get the ECCR2 register value */
589 eccval = FSMC_Bank2->ECCR2;
590 }
591 else
592 {
593 /* Get the ECCR3 register value */
594 eccval = FSMC_Bank3->ECCR3;
595 }
596 /* Return the error correction code value */
597 return(eccval);
598 }
599
600 /**
601 * @brief Enables or disables the specified FSMC interrupts.
602 * @param FSMC_Bank: specifies the FSMC Bank to be used
603 * This parameter can be one of the following values:
604 * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
605 * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
606 * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
607 * @param FSMC_IT: specifies the FSMC interrupt sources to be enabled or disabled.
608 * This parameter can be any combination of the following values:
609 * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt.
610 * @arg FSMC_IT_Level: Level edge detection interrupt.
611 * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt.
612 * @param NewState: new state of the specified FSMC interrupts.
613 * This parameter can be: ENABLE or DISABLE.
614 * @retval None
615 */
FSMC_ITConfig(uint32_t FSMC_Bank,uint32_t FSMC_IT,FunctionalState NewState)616 void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState)
617 {
618 assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
619 assert_param(IS_FSMC_IT(FSMC_IT));
620 assert_param(IS_FUNCTIONAL_STATE(NewState));
621
622 if (NewState != DISABLE)
623 {
624 /* Enable the selected FSMC_Bank2 interrupts */
625 if(FSMC_Bank == FSMC_Bank2_NAND)
626 {
627 FSMC_Bank2->SR2 |= FSMC_IT;
628 }
629 /* Enable the selected FSMC_Bank3 interrupts */
630 else if (FSMC_Bank == FSMC_Bank3_NAND)
631 {
632 FSMC_Bank3->SR3 |= FSMC_IT;
633 }
634 /* Enable the selected FSMC_Bank4 interrupts */
635 else
636 {
637 FSMC_Bank4->SR4 |= FSMC_IT;
638 }
639 }
640 else
641 {
642 /* Disable the selected FSMC_Bank2 interrupts */
643 if(FSMC_Bank == FSMC_Bank2_NAND)
644 {
645
646 FSMC_Bank2->SR2 &= (uint32_t)~FSMC_IT;
647 }
648 /* Disable the selected FSMC_Bank3 interrupts */
649 else if (FSMC_Bank == FSMC_Bank3_NAND)
650 {
651 FSMC_Bank3->SR3 &= (uint32_t)~FSMC_IT;
652 }
653 /* Disable the selected FSMC_Bank4 interrupts */
654 else
655 {
656 FSMC_Bank4->SR4 &= (uint32_t)~FSMC_IT;
657 }
658 }
659 }
660
661 /**
662 * @brief Checks whether the specified FSMC flag is set or not.
663 * @param FSMC_Bank: specifies the FSMC Bank to be used
664 * This parameter can be one of the following values:
665 * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
666 * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
667 * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
668 * @param FSMC_FLAG: specifies the flag to check.
669 * This parameter can be one of the following values:
670 * @arg FSMC_FLAG_RisingEdge: Rising egde detection Flag.
671 * @arg FSMC_FLAG_Level: Level detection Flag.
672 * @arg FSMC_FLAG_FallingEdge: Falling egde detection Flag.
673 * @arg FSMC_FLAG_FEMPT: Fifo empty Flag.
674 * @retval The new state of FSMC_FLAG (SET or RESET).
675 */
FSMC_GetFlagStatus(uint32_t FSMC_Bank,uint32_t FSMC_FLAG)676 FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG)
677 {
678 FlagStatus bitstatus = RESET;
679 uint32_t tmpsr = 0x00000000;
680
681 /* Check the parameters */
682 assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank));
683 assert_param(IS_FSMC_GET_FLAG(FSMC_FLAG));
684
685 if(FSMC_Bank == FSMC_Bank2_NAND)
686 {
687 tmpsr = FSMC_Bank2->SR2;
688 }
689 else if(FSMC_Bank == FSMC_Bank3_NAND)
690 {
691 tmpsr = FSMC_Bank3->SR3;
692 }
693 /* FSMC_Bank4_PCCARD*/
694 else
695 {
696 tmpsr = FSMC_Bank4->SR4;
697 }
698
699 /* Get the flag status */
700 if ((tmpsr & FSMC_FLAG) != (uint16_t)RESET )
701 {
702 bitstatus = SET;
703 }
704 else
705 {
706 bitstatus = RESET;
707 }
708 /* Return the flag status */
709 return bitstatus;
710 }
711
712 /**
713 * @brief Clears the FSMC's pending flags.
714 * @param FSMC_Bank: specifies the FSMC Bank to be used
715 * This parameter can be one of the following values:
716 * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
717 * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
718 * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
719 * @param FSMC_FLAG: specifies the flag to clear.
720 * This parameter can be any combination of the following values:
721 * @arg FSMC_FLAG_RisingEdge: Rising egde detection Flag.
722 * @arg FSMC_FLAG_Level: Level detection Flag.
723 * @arg FSMC_FLAG_FallingEdge: Falling egde detection Flag.
724 * @retval None
725 */
FSMC_ClearFlag(uint32_t FSMC_Bank,uint32_t FSMC_FLAG)726 void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG)
727 {
728 /* Check the parameters */
729 assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank));
730 assert_param(IS_FSMC_CLEAR_FLAG(FSMC_FLAG)) ;
731
732 if(FSMC_Bank == FSMC_Bank2_NAND)
733 {
734 FSMC_Bank2->SR2 &= ~FSMC_FLAG;
735 }
736 else if(FSMC_Bank == FSMC_Bank3_NAND)
737 {
738 FSMC_Bank3->SR3 &= ~FSMC_FLAG;
739 }
740 /* FSMC_Bank4_PCCARD*/
741 else
742 {
743 FSMC_Bank4->SR4 &= ~FSMC_FLAG;
744 }
745 }
746
747 /**
748 * @brief Checks whether the specified FSMC interrupt has occurred or not.
749 * @param FSMC_Bank: specifies the FSMC Bank to be used
750 * This parameter can be one of the following values:
751 * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
752 * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
753 * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
754 * @param FSMC_IT: specifies the FSMC interrupt source to check.
755 * This parameter can be one of the following values:
756 * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt.
757 * @arg FSMC_IT_Level: Level edge detection interrupt.
758 * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt.
759 * @retval The new state of FSMC_IT (SET or RESET).
760 */
FSMC_GetITStatus(uint32_t FSMC_Bank,uint32_t FSMC_IT)761 ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT)
762 {
763 ITStatus bitstatus = RESET;
764 uint32_t tmpsr = 0x0, itstatus = 0x0, itenable = 0x0;
765
766 /* Check the parameters */
767 assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
768 assert_param(IS_FSMC_GET_IT(FSMC_IT));
769
770 if(FSMC_Bank == FSMC_Bank2_NAND)
771 {
772 tmpsr = FSMC_Bank2->SR2;
773 }
774 else if(FSMC_Bank == FSMC_Bank3_NAND)
775 {
776 tmpsr = FSMC_Bank3->SR3;
777 }
778 /* FSMC_Bank4_PCCARD*/
779 else
780 {
781 tmpsr = FSMC_Bank4->SR4;
782 }
783
784 itstatus = tmpsr & FSMC_IT;
785
786 itenable = tmpsr & (FSMC_IT >> 3);
787 if ((itstatus != (uint32_t)RESET) && (itenable != (uint32_t)RESET))
788 {
789 bitstatus = SET;
790 }
791 else
792 {
793 bitstatus = RESET;
794 }
795 return bitstatus;
796 }
797
798 /**
799 * @brief Clears the FSMC's interrupt pending bits.
800 * @param FSMC_Bank: specifies the FSMC Bank to be used
801 * This parameter can be one of the following values:
802 * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
803 * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
804 * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
805 * @param FSMC_IT: specifies the interrupt pending bit to clear.
806 * This parameter can be any combination of the following values:
807 * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt.
808 * @arg FSMC_IT_Level: Level edge detection interrupt.
809 * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt.
810 * @retval None
811 */
FSMC_ClearITPendingBit(uint32_t FSMC_Bank,uint32_t FSMC_IT)812 void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT)
813 {
814 /* Check the parameters */
815 assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
816 assert_param(IS_FSMC_IT(FSMC_IT));
817
818 if(FSMC_Bank == FSMC_Bank2_NAND)
819 {
820 FSMC_Bank2->SR2 &= ~(FSMC_IT >> 3);
821 }
822 else if(FSMC_Bank == FSMC_Bank3_NAND)
823 {
824 FSMC_Bank3->SR3 &= ~(FSMC_IT >> 3);
825 }
826 /* FSMC_Bank4_PCCARD*/
827 else
828 {
829 FSMC_Bank4->SR4 &= ~(FSMC_IT >> 3);
830 }
831 }
832
833 /**
834 * @}
835 */
836
837 /**
838 * @}
839 */
840
841 /**
842 * @}
843 */
844