1 /* Includes ------------------------------------------------------------------*/ 2 #include "air32f10x_pwr.h" 3 #include "air32f10x_rcc.h" 4 5 /** @defgroup PWR 6 * @brief PWR driver modules 7 * @{ 8 */ 9 10 /** @defgroup PWR_Private_TypesDefinitions 11 * @{ 12 */ 13 14 /** 15 * @} 16 */ 17 18 /** @defgroup PWR_Private_Defines 19 * @{ 20 */ 21 22 /* --------- PWR registers bit address in the alias region ---------- */ 23 #define PWR_OFFSET (PWR_BASE - PERIPH_BASE) 24 25 /* --- CR Register ---*/ 26 27 /* Alias word address of DBP bit */ 28 #define CR_OFFSET (PWR_OFFSET + 0x00) 29 #define DBP_BitNumber 0x08 30 #define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4)) 31 32 /* Alias word address of PVDE bit */ 33 #define PVDE_BitNumber 0x04 34 #define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4)) 35 36 /* --- CSR Register ---*/ 37 38 /* Alias word address of EWUP bit */ 39 #define CSR_OFFSET (PWR_OFFSET + 0x04) 40 #define EWUP_BitNumber 0x08 41 #define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4)) 42 43 /* ------------------ PWR registers bit mask ------------------------ */ 44 45 /* CR register bit mask */ 46 #define CR_DS_MASK ((uint32_t)0xFFFFFFFC) 47 #define CR_PLS_MASK ((uint32_t)0xFFFFFF1F) 48 49 50 /** 51 * @} 52 */ 53 54 /** @defgroup PWR_Private_Macros 55 * @{ 56 */ 57 58 /** 59 * @} 60 */ 61 62 /** @defgroup PWR_Private_Variables 63 * @{ 64 */ 65 66 /** 67 * @} 68 */ 69 70 /** @defgroup PWR_Private_FunctionPrototypes 71 * @{ 72 */ 73 74 /** 75 * @} 76 */ 77 78 /** @defgroup PWR_Private_Functions 79 * @{ 80 */ 81 82 /** 83 * @brief Deinitializes the PWR peripheral registers to their default reset values. 84 * @param None 85 * @retval None 86 */ PWR_DeInit(void)87void PWR_DeInit(void) 88 { 89 RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE); 90 RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE); 91 } 92 93 /** 94 * @brief Enables or disables access to the RTC and backup registers. 95 * @param NewState: new state of the access to the RTC and backup registers. 96 * This parameter can be: ENABLE or DISABLE. 97 * @retval None 98 */ PWR_BackupAccessCmd(FunctionalState NewState)99void PWR_BackupAccessCmd(FunctionalState NewState) 100 { 101 /* Check the parameters */ 102 assert_param(IS_FUNCTIONAL_STATE(NewState)); 103 *(__IO uint32_t *) CR_DBP_BB = (uint32_t)NewState; 104 } 105 106 /** 107 * @brief Enables or disables the Power Voltage Detector(PVD). 108 * @param NewState: new state of the PVD. 109 * This parameter can be: ENABLE or DISABLE. 110 * @retval None 111 */ PWR_PVDCmd(FunctionalState NewState)112void PWR_PVDCmd(FunctionalState NewState) 113 { 114 /* Check the parameters */ 115 assert_param(IS_FUNCTIONAL_STATE(NewState)); 116 *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)NewState; 117 } 118 119 /** 120 * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD). 121 * @param PWR_PVDLevel: specifies the PVD detection level 122 * This parameter can be one of the following values: 123 * @arg PWR_PVDLevel_2V2: PVD detection level set to 2.2V 124 * @arg PWR_PVDLevel_2V3: PVD detection level set to 2.3V 125 * @arg PWR_PVDLevel_2V4: PVD detection level set to 2.4V 126 * @arg PWR_PVDLevel_2V5: PVD detection level set to 2.5V 127 * @arg PWR_PVDLevel_2V6: PVD detection level set to 2.6V 128 * @arg PWR_PVDLevel_2V7: PVD detection level set to 2.7V 129 * @arg PWR_PVDLevel_2V8: PVD detection level set to 2.8V 130 * @arg PWR_PVDLevel_2V9: PVD detection level set to 2.9V 131 * @retval None 132 */ PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)133void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel) 134 { 135 uint32_t tmpreg = 0; 136 /* Check the parameters */ 137 assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel)); 138 tmpreg = PWR->CR; 139 /* Clear PLS[7:5] bits */ 140 tmpreg &= CR_PLS_MASK; 141 /* Set PLS[7:5] bits according to PWR_PVDLevel value */ 142 tmpreg |= PWR_PVDLevel; 143 /* Store the new value */ 144 PWR->CR = tmpreg; 145 } 146 147 /** 148 * @brief Enables or disables the WakeUp Pin functionality. 149 * @param NewState: new state of the WakeUp Pin functionality. 150 * This parameter can be: ENABLE or DISABLE. 151 * @retval None 152 */ PWR_WakeUpPinCmd(FunctionalState NewState)153void PWR_WakeUpPinCmd(FunctionalState NewState) 154 { 155 /* Check the parameters */ 156 assert_param(IS_FUNCTIONAL_STATE(NewState)); 157 *(__IO uint32_t *) CSR_EWUP_BB = (uint32_t)NewState; 158 } 159 160 /** 161 * @brief Enters STOP mode. 162 * @param PWR_Regulator: specifies the regulator state in STOP mode. 163 * This parameter can be one of the following values: 164 * @arg PWR_Regulator_ON: STOP mode with regulator ON 165 * @arg PWR_Regulator_LowPower: STOP mode with regulator in low power mode 166 * @param PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction. 167 * This parameter can be one of the following values: 168 * @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction 169 * @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction 170 * @retval None 171 */ PWR_EnterSTOPMode(uint32_t PWR_Regulator,uint8_t PWR_STOPEntry)172void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry) 173 { 174 uint32_t tmpreg = 0; 175 /* Check the parameters */ 176 assert_param(IS_PWR_REGULATOR(PWR_Regulator)); 177 assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry)); 178 179 /* Select the regulator state in STOP mode ---------------------------------*/ 180 tmpreg = PWR->CR; 181 /* Clear PDDS and LPDS bits */ 182 tmpreg &= CR_DS_MASK; 183 /* Set LPDS bit according to PWR_Regulator value */ 184 tmpreg |= PWR_Regulator; 185 /* Store the new value */ 186 PWR->CR = tmpreg; 187 /* Set SLEEPDEEP bit of Cortex System Control Register */ 188 SCB->SCR |= SCB_SCR_SLEEPDEEP; 189 190 /* Select STOP mode entry --------------------------------------------------*/ 191 if(PWR_STOPEntry == PWR_STOPEntry_WFI) 192 { 193 /* Request Wait For Interrupt */ 194 __WFI(); 195 } 196 else 197 { 198 /* Request Wait For Event */ 199 __WFE(); 200 } 201 202 /* Reset SLEEPDEEP bit of Cortex System Control Register */ 203 SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP); 204 } 205 206 /** 207 * @brief Enters STANDBY mode. 208 * @param None 209 * @retval None 210 */ PWR_EnterSTANDBYMode(void)211void PWR_EnterSTANDBYMode(void) 212 { 213 /* Clear Wake-up flag */ 214 PWR->CR |= PWR_CR_CWUF; 215 /* Select STANDBY mode */ 216 PWR->CR |= PWR_CR_PDDS; 217 /* Set SLEEPDEEP bit of Cortex System Control Register */ 218 SCB->SCR |= SCB_SCR_SLEEPDEEP; 219 /* This option is used to ensure that store operations are completed */ 220 #if defined ( __CC_ARM ) 221 __force_stores(); 222 #endif 223 /* Request Wait For Interrupt */ 224 __WFI(); 225 } 226 227 /** 228 * @brief Checks whether the specified PWR flag is set or not. 229 * @param PWR_FLAG: specifies the flag to check. 230 * This parameter can be one of the following values: 231 * @arg PWR_FLAG_WU: Wake Up flag 232 * @arg PWR_FLAG_SB: StandBy flag 233 * @arg PWR_FLAG_PVDO: PVD Output 234 * @retval The new state of PWR_FLAG (SET or RESET). 235 */ PWR_GetFlagStatus(uint32_t PWR_FLAG)236FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG) 237 { 238 FlagStatus bitstatus = RESET; 239 /* Check the parameters */ 240 assert_param(IS_PWR_GET_FLAG(PWR_FLAG)); 241 242 if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET) 243 { 244 bitstatus = SET; 245 } 246 else 247 { 248 bitstatus = RESET; 249 } 250 /* Return the flag status */ 251 return bitstatus; 252 } 253 254 /** 255 * @brief Clears the PWR's pending flags. 256 * @param PWR_FLAG: specifies the flag to clear. 257 * This parameter can be one of the following values: 258 * @arg PWR_FLAG_WU: Wake Up flag 259 * @arg PWR_FLAG_SB: StandBy flag 260 * @retval None 261 */ PWR_ClearFlag(uint32_t PWR_FLAG)262void PWR_ClearFlag(uint32_t PWR_FLAG) 263 { 264 /* Check the parameters */ 265 assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG)); 266 267 PWR->CR |= PWR_FLAG << 2; 268 } 269 270 /** 271 * @} 272 */ 273 274 /** 275 * @} 276 */ 277 278 /** 279 * @} 280 */ 281 282