1 /* Includes ------------------------------------------------------------------*/
2 #include "air32f10x_rcc.h"
3
4 /** @addtogroup air32f10x_StdPeriph_Driver
5 * @{
6 */
7
8 /** @defgroup RCC
9 * @brief RCC driver modules
10 * @{
11 */
12
13 /** @defgroup RCC_Private_TypesDefinitions
14 * @{
15 */
16
17 /**
18 * @}
19 */
20
21 /** @defgroup RCC_Private_Defines
22 * @{
23 */
24
25 /* ------------ RCC registers bit address in the alias region ----------- */
26 #define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
27
28 /* --- CR Register ---*/
29
30 /* Alias word address of HSION bit */
31 #define CR_OFFSET (RCC_OFFSET + 0x00)
32 #define HSION_BitNumber 0x00
33 #define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4))
34
35 /* Alias word address of PLLON bit */
36 #define PLLON_BitNumber 0x18
37 #define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4))
38
39 /* Alias word address of CSSON bit */
40 #define CSSON_BitNumber 0x13
41 #define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4))
42
43 /* --- CFGR Register ---*/
44
45 /* Alias word address of USBPRE bit */
46 #define CFGR_OFFSET (RCC_OFFSET + 0x04)
47
48 #define USBPRE_BitNumber 0x16
49 #define CFGR_USBPRE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (USBPRE_BitNumber * 4))
50
51 /* --- BDCR Register ---*/
52
53 /* Alias word address of RTCEN bit */
54 #define BDCR_OFFSET (RCC_OFFSET + 0x20)
55 #define RTCEN_BitNumber 0x0F
56 #define BDCR_RTCEN_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4))
57
58 /* Alias word address of BDRST bit */
59 #define BDRST_BitNumber 0x10
60 #define BDCR_BDRST_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4))
61
62 /* --- CSR Register ---*/
63
64 /* Alias word address of LSION bit */
65 #define CSR_OFFSET (RCC_OFFSET + 0x24)
66 #define LSION_BitNumber 0x00
67 #define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4))
68
69 /* ---------------------- RCC registers bit mask ------------------------ */
70
71 /* CR register bit mask */
72 #define CR_HSEBYP_Reset ((uint32_t)0xFFFBFFFF)
73 #define CR_HSEBYP_Set ((uint32_t)0x00040000)
74 #define CR_HSEON_Reset ((uint32_t)0xFFFEFFFF)
75 #define CR_HSEON_Set ((uint32_t)0x00010000)
76 #define CR_HSITRIM_Mask ((uint32_t)0xFFFFFF07)
77
78 #define CFGR_PLL_Mask ((uint32_t)0xFFC0FFFF)
79
80 #define CFGR_PLLMull_Mask ((uint32_t)0x003C0000)
81 #define CFGR_PLLSRC_Mask ((uint32_t)0x00010000)
82 #define CFGR_PLLXTPRE_Mask ((uint32_t)0x00020000)
83 #define CFGR_SWS_Mask ((uint32_t)0x0000000C)
84 #define CFGR_SW_Mask ((uint32_t)0xFFFFFFFC)
85 #define CFGR_HPRE_Reset_Mask ((uint32_t)0xFFFFFF0F)
86 #define CFGR_HPRE_Set_Mask ((uint32_t)0x000000F0)
87 #define CFGR_PPRE1_Reset_Mask ((uint32_t)0xFFFFF8FF)
88 #define CFGR_PPRE1_Set_Mask ((uint32_t)0x00000700)
89 #define CFGR_PPRE2_Reset_Mask ((uint32_t)0xFFFFC7FF)
90 #define CFGR_PPRE2_Set_Mask ((uint32_t)0x00003800)
91 #define CFGR_ADCPRE_Reset_Mask ((uint32_t)0x9FFF3FFF)
92 #define CFGR_ADCPRE_Set_Mask ((uint32_t)0x6000C000)
93
94 /* CSR register bit mask */
95 #define CSR_RMVF_Set ((uint32_t)0x01000000)
96
97 /* RCC Flag Mask */
98 #define FLAG_Mask ((uint8_t)0x1F)
99
100 /* CIR register byte 2 (Bits[15:8]) base address */
101 #define CIR_BYTE2_ADDRESS ((uint32_t)0x40021009)
102
103 /* CIR register byte 3 (Bits[23:16]) base address */
104 #define CIR_BYTE3_ADDRESS ((uint32_t)0x4002100A)
105
106 /* CFGR register byte 4 (Bits[31:24]) base address */
107 #define CFGR_BYTE4_ADDRESS ((uint32_t)0x40021007)
108
109 /* BDCR register base address */
110 #define BDCR_ADDRESS (PERIPH_BASE + BDCR_OFFSET)
111
112 /**
113 * @}
114 */
115
116 /** @defgroup RCC_Private_Macros
117 * @{
118 */
119
120 /**
121 * @}
122 */
123
124 /** @defgroup RCC_Private_Variables
125 * @{
126 */
127
128 static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
129 static __I uint8_t ADCPrescTable[16] = {2, 4, 6, 8, 16, 32, 36, 48, 64, 72, 96, 120, 144, 168, 192 ,216};
130
131 /**
132 * @}
133 */
134
135 /** @defgroup RCC_Private_FunctionPrototypes
136 * @{
137 */
138
139 /**
140 * @}
141 */
142
143 /** @defgroup RCC_Private_Functions
144 * @{
145 */
146
147 /**
148 * @brief Resets the RCC clock configuration to the default reset state.
149 * @param None
150 * @retval None
151 */
RCC_DeInit(void)152 void RCC_DeInit(void)
153 {
154 /* Set HSION bit */
155 RCC->CR |= (uint32_t)0x00000001;
156
157 /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
158 RCC->CFGR &= (uint32_t)0xF8FF0000;
159
160 /* Reset HSEON, CSSON and PLLON bits */
161 RCC->CR &= (uint32_t)0xFEF6FFFF;
162
163 /* Reset HSEBYP bit */
164 RCC->CR &= (uint32_t)0xFFFBFFFF;
165
166 /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
167 RCC->CFGR &= (uint32_t)0xFF80FFFF;
168
169 /* Disable all interrupts and clear pending bits */
170 RCC->CIR = 0x009F0000;
171 }
172
173 /**
174 * @brief Configures the External High Speed oscillator (HSE).
175 * @note HSE can not be stopped if it is used directly or through the PLL as system clock.
176 * @param RCC_HSE: specifies the new state of the HSE.
177 * This parameter can be one of the following values:
178 * @arg RCC_HSE_OFF: HSE oscillator OFF
179 * @arg RCC_HSE_ON: HSE oscillator ON
180 * @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock
181 * @retval None
182 */
RCC_HSEConfig(uint32_t RCC_HSE)183 void RCC_HSEConfig(uint32_t RCC_HSE)
184 {
185 /* Check the parameters */
186 assert_param(IS_RCC_HSE(RCC_HSE));
187 /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/
188 /* Reset HSEON bit */
189 RCC->CR &= CR_HSEON_Reset;
190 /* Reset HSEBYP bit */
191 RCC->CR &= CR_HSEBYP_Reset;
192 /* Configure HSE (RCC_HSE_OFF is already covered by the code section above) */
193 switch(RCC_HSE)
194 {
195 case RCC_HSE_ON:
196 /* Set HSEON bit */
197 RCC->CR |= CR_HSEON_Set;
198 break;
199
200 case RCC_HSE_Bypass:
201 /* Set HSEBYP and HSEON bits */
202 RCC->CR |= CR_HSEBYP_Set | CR_HSEON_Set;
203 break;
204
205 default:
206 break;
207 }
208 }
209
210 /**
211 * @brief Waits for HSE start-up.
212 * @param None
213 * @retval An ErrorStatus enumuration value:
214 * - SUCCESS: HSE oscillator is stable and ready to use
215 * - ERROR: HSE oscillator not yet ready
216 */
RCC_WaitForHSEStartUp(void)217 ErrorStatus RCC_WaitForHSEStartUp(void)
218 {
219 __IO uint32_t StartUpCounter = 0;
220 ErrorStatus status = ERROR;
221 FlagStatus HSEStatus = RESET;
222
223 /* Wait till HSE is ready and if Time out is reached exit */
224 do
225 {
226 HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY);
227 StartUpCounter++;
228 } while((StartUpCounter != HSE_STARTUP_TIMEOUT) && (HSEStatus == RESET));
229
230 if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET)
231 {
232 status = SUCCESS;
233 }
234 else
235 {
236 status = ERROR;
237 }
238 return (status);
239 }
240
241 /**
242 * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value.
243 * @param HSICalibrationValue: specifies the calibration trimming value.
244 * This parameter must be a number between 0 and 0x1F.
245 * @retval None
246 */
RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue)247 void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue)
248 {
249 uint32_t tmpreg = 0;
250 /* Check the parameters */
251 assert_param(IS_RCC_CALIBRATION_VALUE(HSICalibrationValue));
252 tmpreg = RCC->CR;
253 /* Clear HSITRIM[4:0] bits */
254 tmpreg &= CR_HSITRIM_Mask;
255 /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */
256 tmpreg |= (uint32_t)HSICalibrationValue << 3;
257 /* Store the new value */
258 RCC->CR = tmpreg;
259 }
260
261 /**
262 * @brief Enables or disables the Internal High Speed oscillator (HSI).
263 * @note HSI can not be stopped if it is used directly or through the PLL as system clock.
264 * @param NewState: new state of the HSI. This parameter can be: ENABLE or DISABLE.
265 * @retval None
266 */
RCC_HSICmd(FunctionalState NewState)267 void RCC_HSICmd(FunctionalState NewState)
268 {
269 /* Check the parameters */
270 assert_param(IS_FUNCTIONAL_STATE(NewState));
271 *(__IO uint32_t *) CR_HSION_BB = (uint32_t)NewState;
272 }
273
274 /**
275 * @brief Configures the PLL clock source and multiplication factor.
276 * @note This function must be used only when the PLL is disabled.
277 * @param RCC_PLLSource: specifies the PLL entry clock source.
278 * For @b air32_Connectivity_line_devices or @b air32_Value_line_devices,
279 * this parameter can be one of the following values:
280 * @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock divided by 2 selected as PLL clock entry
281 * @arg RCC_PLLSource_PREDIV1: PREDIV1 clock selected as PLL clock entry
282 * For @b other_air32_devices, this parameter can be one of the following values:
283 * @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock divided by 2 selected as PLL clock entry
284 * @arg RCC_PLLSource_HSE_Div1: HSE oscillator clock selected as PLL clock entry
285 * @arg RCC_PLLSource_HSE_Div2: HSE oscillator clock divided by 2 selected as PLL clock entry
286 * @param RCC_PLLMul: specifies the PLL multiplication factor.
287 * For @b air32_Connectivity_line_devices, this parameter can be RCC_PLLMul_x where x:{[4,9], 6_5}
288 * For @b other_air32_devices, this parameter can be RCC_PLLMul_x where x:[2,16]
289 * @retval None
290 */
RCC_PLLConfig(uint32_t RCC_PLLSource,uint32_t RCC_PLLMul)291 void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul)
292 {
293 uint32_t tmpreg = 0;
294
295 /* Check the parameters */
296 assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource));
297 assert_param(IS_RCC_PLL_MUL(RCC_PLLMul));
298
299 tmpreg = RCC->CFGR;
300 /* Clear PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
301 tmpreg &= CFGR_PLL_Mask;
302 /* Set the PLL configuration bits */
303 tmpreg |= RCC_PLLSource | RCC_PLLMul;
304 /* Store the new value */
305 RCC->CFGR = tmpreg;
306 }
307
308 /**
309 * @brief Enables or disables the PLL.
310 * @note The PLL can not be disabled if it is used as system clock.
311 * @param NewState: new state of the PLL. This parameter can be: ENABLE or DISABLE.
312 * @retval None
313 */
RCC_PLLCmd(FunctionalState NewState)314 void RCC_PLLCmd(FunctionalState NewState)
315 {
316 /* Check the parameters */
317 assert_param(IS_FUNCTIONAL_STATE(NewState));
318
319 *(__IO uint32_t *) CR_PLLON_BB = (uint32_t)NewState;
320 }
321
322 /**
323 * @brief Configures the system clock (SYSCLK).
324 * @param RCC_SYSCLKSource: specifies the clock source used as system clock.
325 * This parameter can be one of the following values:
326 * @arg RCC_SYSCLKSource_HSI: HSI selected as system clock
327 * @arg RCC_SYSCLKSource_HSE: HSE selected as system clock
328 * @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock
329 * @retval None
330 */
RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)331 void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)
332 {
333 uint32_t tmpreg = 0;
334 /* Check the parameters */
335 assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource));
336 tmpreg = RCC->CFGR;
337 /* Clear SW[1:0] bits */
338 tmpreg &= CFGR_SW_Mask;
339 /* Set SW[1:0] bits according to RCC_SYSCLKSource value */
340 tmpreg |= RCC_SYSCLKSource;
341 /* Store the new value */
342 RCC->CFGR = tmpreg;
343 }
344
345 /**
346 * @brief Returns the clock source used as system clock.
347 * @param None
348 * @retval The clock source used as system clock. The returned value can
349 * be one of the following:
350 * - 0x00: HSI used as system clock
351 * - 0x04: HSE used as system clock
352 * - 0x08: PLL used as system clock
353 */
RCC_GetSYSCLKSource(void)354 uint8_t RCC_GetSYSCLKSource(void)
355 {
356 return ((uint8_t)(RCC->CFGR & CFGR_SWS_Mask));
357 }
358
359 /**
360 * @brief Configures the AHB clock (HCLK).
361 * @param RCC_SYSCLK: defines the AHB clock divider. This clock is derived from
362 * the system clock (SYSCLK).
363 * This parameter can be one of the following values:
364 * @arg RCC_SYSCLK_Div1: AHB clock = SYSCLK
365 * @arg RCC_SYSCLK_Div2: AHB clock = SYSCLK/2
366 * @arg RCC_SYSCLK_Div4: AHB clock = SYSCLK/4
367 * @arg RCC_SYSCLK_Div8: AHB clock = SYSCLK/8
368 * @arg RCC_SYSCLK_Div16: AHB clock = SYSCLK/16
369 * @arg RCC_SYSCLK_Div64: AHB clock = SYSCLK/64
370 * @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128
371 * @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256
372 * @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512
373 * @retval None
374 */
RCC_HCLKConfig(uint32_t RCC_SYSCLK)375 void RCC_HCLKConfig(uint32_t RCC_SYSCLK)
376 {
377 uint32_t tmpreg = 0;
378 /* Check the parameters */
379 assert_param(IS_RCC_HCLK(RCC_SYSCLK));
380 tmpreg = RCC->CFGR;
381 /* Clear HPRE[3:0] bits */
382 tmpreg &= CFGR_HPRE_Reset_Mask;
383 /* Set HPRE[3:0] bits according to RCC_SYSCLK value */
384 tmpreg |= RCC_SYSCLK;
385 /* Store the new value */
386 RCC->CFGR = tmpreg;
387 }
388
389 /**
390 * @brief Configures the Low Speed APB clock (PCLK1).
391 * @param RCC_HCLK: defines the APB1 clock divider. This clock is derived from
392 * the AHB clock (HCLK).
393 * This parameter can be one of the following values:
394 * @arg RCC_HCLK_Div1: APB1 clock = HCLK
395 * @arg RCC_HCLK_Div2: APB1 clock = HCLK/2
396 * @arg RCC_HCLK_Div4: APB1 clock = HCLK/4
397 * @arg RCC_HCLK_Div8: APB1 clock = HCLK/8
398 * @arg RCC_HCLK_Div16: APB1 clock = HCLK/16
399 * @retval None
400 */
RCC_PCLK1Config(uint32_t RCC_HCLK)401 void RCC_PCLK1Config(uint32_t RCC_HCLK)
402 {
403 uint32_t tmpreg = 0;
404 /* Check the parameters */
405 assert_param(IS_RCC_PCLK(RCC_HCLK));
406 tmpreg = RCC->CFGR;
407 /* Clear PPRE1[2:0] bits */
408 tmpreg &= CFGR_PPRE1_Reset_Mask;
409 /* Set PPRE1[2:0] bits according to RCC_HCLK value */
410 tmpreg |= RCC_HCLK;
411 /* Store the new value */
412 RCC->CFGR = tmpreg;
413 }
414
415 /**
416 * @brief Configures the High Speed APB clock (PCLK2).
417 * @param RCC_HCLK: defines the APB2 clock divider. This clock is derived from
418 * the AHB clock (HCLK).
419 * This parameter can be one of the following values:
420 * @arg RCC_HCLK_Div1: APB2 clock = HCLK
421 * @arg RCC_HCLK_Div2: APB2 clock = HCLK/2
422 * @arg RCC_HCLK_Div4: APB2 clock = HCLK/4
423 * @arg RCC_HCLK_Div8: APB2 clock = HCLK/8
424 * @arg RCC_HCLK_Div16: APB2 clock = HCLK/16
425 * @retval None
426 */
RCC_PCLK2Config(uint32_t RCC_HCLK)427 void RCC_PCLK2Config(uint32_t RCC_HCLK)
428 {
429 uint32_t tmpreg = 0;
430 /* Check the parameters */
431 assert_param(IS_RCC_PCLK(RCC_HCLK));
432 tmpreg = RCC->CFGR;
433 /* Clear PPRE2[2:0] bits */
434 tmpreg &= CFGR_PPRE2_Reset_Mask;
435 /* Set PPRE2[2:0] bits according to RCC_HCLK value */
436 tmpreg |= RCC_HCLK << 3;
437 /* Store the new value */
438 RCC->CFGR = tmpreg;
439 }
440
441 /**
442 * @brief Enables or disables the specified RCC interrupts.
443 * @param RCC_IT: specifies the RCC interrupt sources to be enabled or disabled.
444 *
445 * For @b air32_Connectivity_line_devices, this parameter can be any combination
446 * of the following values
447 * @arg RCC_IT_LSIRDY: LSI ready interrupt
448 * @arg RCC_IT_LSERDY: LSE ready interrupt
449 * @arg RCC_IT_HSIRDY: HSI ready interrupt
450 * @arg RCC_IT_HSERDY: HSE ready interrupt
451 * @arg RCC_IT_PLLRDY: PLL ready interrupt
452 * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt
453 * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt
454 *
455 * For @b other_air32_devices, this parameter can be any combination of the
456 * following values
457 * @arg RCC_IT_LSIRDY: LSI ready interrupt
458 * @arg RCC_IT_LSERDY: LSE ready interrupt
459 * @arg RCC_IT_HSIRDY: HSI ready interrupt
460 * @arg RCC_IT_HSERDY: HSE ready interrupt
461 * @arg RCC_IT_PLLRDY: PLL ready interrupt
462 *
463 * @param NewState: new state of the specified RCC interrupts.
464 * This parameter can be: ENABLE or DISABLE.
465 * @retval None
466 */
RCC_ITConfig(uint8_t RCC_IT,FunctionalState NewState)467 void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState)
468 {
469 /* Check the parameters */
470 assert_param(IS_RCC_IT(RCC_IT));
471 assert_param(IS_FUNCTIONAL_STATE(NewState));
472 if (NewState != DISABLE)
473 {
474 /* Perform Byte access to RCC_CIR bits to enable the selected interrupts */
475 *(__IO uint8_t *) CIR_BYTE2_ADDRESS |= RCC_IT;
476 }
477 else
478 {
479 /* Perform Byte access to RCC_CIR bits to disable the selected interrupts */
480 *(__IO uint8_t *) CIR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT;
481 }
482 }
483
RCC_USBCLKConfig(uint32_t RCC_USBCLKSource)484 void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource)
485 {
486 /* Check the parameters */
487 assert_param(IS_RCC_USBCLK_SOURCE(RCC_USBCLKSource));
488
489 RCC->CFGR &= ~(BIT(22)|BIT(23)|BIT(31));
490 RCC->CFGR |= RCC_USBCLKSource;
491 }
492
493
494 /**
495 * @brief Configures the ADC clock (ADCCLK).
496 * @param RCC_PCLK2: defines the ADC clock divider. This clock is derived from
497 * the APB2 clock (PCLK2).
498 * This parameter can be one of the following values:
499 * @arg RCC_PCLK2_Div2: ADC clock = PCLK2/2
500 * @arg RCC_PCLK2_Div4: ADC clock = PCLK2/4
501 * @arg RCC_PCLK2_Div6: ADC clock = PCLK2/6
502 * @arg RCC_PCLK2_Div8: ADC clock = PCLK2/8
503 * @retval None
504 */
RCC_ADCCLKConfig(uint32_t RCC_PCLK2)505 void RCC_ADCCLKConfig(uint32_t RCC_PCLK2)
506 {
507 uint32_t tmpreg = 0;
508 /* Check the parameters */
509 assert_param(IS_RCC_ADCCLK(RCC_PCLK2));
510 tmpreg = RCC->CFGR;
511 /* Clear ADCPRE[1:0] bits */
512 tmpreg &= CFGR_ADCPRE_Reset_Mask;
513 /* Set ADCPRE[1:0] bits according to RCC_PCLK2 value */
514 tmpreg |= RCC_PCLK2;
515 /* Store the new value */
516 RCC->CFGR = tmpreg;
517 }
518
519 /**
520 * @brief Configures the External Low Speed oscillator (LSE).
521 * @param RCC_LSE: specifies the new state of the LSE.
522 * This parameter can be one of the following values:
523 * @arg RCC_LSE_OFF: LSE oscillator OFF
524 * @arg RCC_LSE_ON: LSE oscillator ON
525 * @arg RCC_LSE_Bypass: LSE oscillator bypassed with external clock
526 * @retval None
527 */
RCC_LSEConfig(uint8_t RCC_LSE)528 void RCC_LSEConfig(uint8_t RCC_LSE)
529 {
530 /* Check the parameters */
531 assert_param(IS_RCC_LSE(RCC_LSE));
532 /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/
533 /* Reset LSEON bit */
534 *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF;
535 /* Reset LSEBYP bit */
536 *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF;
537 /* Configure LSE (RCC_LSE_OFF is already covered by the code section above) */
538 switch(RCC_LSE)
539 {
540 case RCC_LSE_ON:
541 /* Set LSEON bit */
542 *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_ON;
543 break;
544
545 case RCC_LSE_Bypass:
546 /* Set LSEBYP and LSEON bits */
547 *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_Bypass | RCC_LSE_ON;
548 break;
549
550 default:
551 break;
552 }
553 }
554
555 /**
556 * @brief Enables or disables the Internal Low Speed oscillator (LSI).
557 * @note LSI can not be disabled if the IWDG is running.
558 * @param NewState: new state of the LSI. This parameter can be: ENABLE or DISABLE.
559 * @retval None
560 */
RCC_LSICmd(FunctionalState NewState)561 void RCC_LSICmd(FunctionalState NewState)
562 {
563 /* Check the parameters */
564 assert_param(IS_FUNCTIONAL_STATE(NewState));
565 *(__IO uint32_t *) CSR_LSION_BB = (uint32_t)NewState;
566 }
567
568 /**
569 * @brief Configures the RTC clock (RTCCLK).
570 * @note Once the RTC clock is selected it can't be changed unless the Backup domain is reset.
571 * @param RCC_RTCCLKSource: specifies the RTC clock source.
572 * This parameter can be one of the following values:
573 * @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock
574 * @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock
575 * @arg RCC_RTCCLKSource_HSE_Div128: HSE clock divided by 128 selected as RTC clock
576 * @retval None
577 */
RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource)578 void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource)
579 {
580 /* Check the parameters */
581 assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource));
582 /* Select the RTC clock source */
583 RCC->BDCR |= RCC_RTCCLKSource;
584 }
585
586 /**
587 * @brief Enables or disables the RTC clock.
588 * @note This function must be used only after the RTC clock was selected using the RCC_RTCCLKConfig function.
589 * @param NewState: new state of the RTC clock. This parameter can be: ENABLE or DISABLE.
590 * @retval None
591 */
RCC_RTCCLKCmd(FunctionalState NewState)592 void RCC_RTCCLKCmd(FunctionalState NewState)
593 {
594 /* Check the parameters */
595 assert_param(IS_FUNCTIONAL_STATE(NewState));
596 *(__IO uint32_t *) BDCR_RTCEN_BB = (uint32_t)NewState;
597 }
598
599 /**
600 * @brief Returns the frequencies of different on chip clocks.
601 * @param RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold
602 * the clocks frequencies.
603 * @note The result of this function could be not correct when using
604 * fractional value for HSE crystal.
605 * @retval None
606 */
RCC_GetClocksFreq(RCC_ClocksTypeDef * RCC_Clocks)607 void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
608 {
609 uint32_t tmp = 0, pllmull = 0, pllsource = 0, presc = 0;
610 uint32_t i;
611
612 /* Get SYSCLK source -------------------------------------------------------*/
613 tmp = RCC->CFGR & CFGR_SWS_Mask;
614
615 switch (tmp)
616 {
617 case 0x00: /* HSI used as system clock */
618 RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
619 break;
620 case 0x04: /* HSE used as system clock */
621 RCC_Clocks->SYSCLK_Frequency = HSE_VALUE;
622 break;
623 case 0x08: /* PLL used as system clock */
624
625 /* Get PLL clock source and multiplication factor ----------------------*/
626 pllmull = RCC->CFGR & CFGR_PLLMull_Mask;
627 pllsource = RCC->CFGR & CFGR_PLLSRC_Mask;
628
629 if (RCC->CFGR >> 28 & 0x01)
630 {
631 i = 0x01;
632 pllmull = (i << 4 | ( pllmull >> 18)) + 1;
633 }
634 else
635 {
636 pllmull = ( pllmull >> 18) + 2 ;
637 }
638
639
640 if (pllsource == 0x00)
641 {/* HSI oscillator clock divided by 2 selected as PLL clock entry */
642 RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE >> 1) * pllmull;
643 }
644 else
645 {
646 /* HSE selected as PLL clock entry */
647 if ((RCC->CFGR & CFGR_PLLXTPRE_Mask) != (uint32_t)RESET)
648 {/* HSE oscillator clock divided by 2 */
649 RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE >> 1) * pllmull;
650 }
651 else
652 {
653 RCC_Clocks->SYSCLK_Frequency = HSE_VALUE * pllmull;
654 }
655
656 }
657 break;
658
659 default:
660 RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
661 break;
662 }
663
664 /* Compute HCLK, PCLK1, PCLK2 and ADCCLK clocks frequencies ----------------*/
665 /* Get HCLK prescaler */
666 tmp = RCC->CFGR & CFGR_HPRE_Set_Mask;
667 tmp = tmp >> 4;
668 presc = APBAHBPrescTable[tmp];
669 /* HCLK clock frequency */
670 RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;
671 /* Get PCLK1 prescaler */
672 tmp = RCC->CFGR & CFGR_PPRE1_Set_Mask;
673 tmp = tmp >> 8;
674 presc = APBAHBPrescTable[tmp];
675 /* PCLK1 clock frequency */
676 RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
677 /* Get PCLK2 prescaler */
678 tmp = RCC->CFGR & CFGR_PPRE2_Set_Mask;
679 tmp = tmp >> 11;
680 presc = APBAHBPrescTable[tmp];
681 /* PCLK2 clock frequency */
682 RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
683 /* Get ADCCLK prescaler */
684 tmp = RCC->CFGR & CFGR_ADCPRE_Set_Mask;
685 tmp = ((tmp >> 27) | (tmp >> 14)) & 0x0F;
686 presc = ADCPrescTable[tmp];
687 /* ADCCLK clock frequency */
688 RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency / presc;
689 }
690
691 /**
692 * @brief Enables or disables the AHB peripheral clock.
693 * @param RCC_AHBPeriph: specifies the AHB peripheral to gates its clock.
694 *
695 * For @b air32_Connectivity_line_devices, this parameter can be any combination
696 * of the following values:
697 * @arg RCC_AHBPeriph_DMA1
698 * @arg RCC_AHBPeriph_DMA2
699 * @arg RCC_AHBPeriph_SRAM
700 * @arg RCC_AHBPeriph_FLITF
701 * @arg RCC_AHBPeriph_CRC
702 * @arg RCC_AHBPeriph_OTG_FS
703 * @arg RCC_AHBPeriph_ETH_MAC
704 * @arg RCC_AHBPeriph_ETH_MAC_Tx
705 * @arg RCC_AHBPeriph_ETH_MAC_Rx
706 *
707 * For @b other_air32_devices, this parameter can be any combination of the
708 * following values:
709 * @arg RCC_AHBPeriph_DMA1
710 * @arg RCC_AHBPeriph_DMA2
711 * @arg RCC_AHBPeriph_SRAM
712 * @arg RCC_AHBPeriph_FLITF
713 * @arg RCC_AHBPeriph_CRC
714 * @arg RCC_AHBPeriph_FSMC
715 * @arg RCC_AHBPeriph_SDIO
716 *
717 * @note SRAM and FLITF clock can be disabled only during sleep mode.
718 * @param NewState: new state of the specified peripheral clock.
719 * This parameter can be: ENABLE or DISABLE.
720 * @retval None
721 */
RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph,FunctionalState NewState)722 void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
723 {
724 /* Check the parameters */
725 assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph));
726 assert_param(IS_FUNCTIONAL_STATE(NewState));
727
728 if (NewState != DISABLE)
729 {
730 RCC->AHBENR |= RCC_AHBPeriph;
731 }
732 else
733 {
734 RCC->AHBENR &= ~RCC_AHBPeriph;
735 }
736 }
737
738 /**
739 * @brief Enables or disables the High Speed APB (APB2) peripheral clock.
740 * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock.
741 * This parameter can be any combination of the following values:
742 * @arg RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB,
743 * RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE,
744 * RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, RCC_APB2Periph_ADC1,
745 * RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1, RCC_APB2Periph_SPI1,
746 * RCC_APB2Periph_TIM8, RCC_APB2Periph_USART1, RCC_APB2Periph_ADC3,
747 * RCC_APB2Periph_TIM15, RCC_APB2Periph_TIM16, RCC_APB2Periph_TIM17,
748 * RCC_APB2Periph_TIM9, RCC_APB2Periph_TIM10, RCC_APB2Periph_TIM11
749 * @param NewState: new state of the specified peripheral clock.
750 * This parameter can be: ENABLE or DISABLE.
751 * @retval None
752 */
RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph,FunctionalState NewState)753 void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
754 {
755 /* Check the parameters */
756 assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
757 assert_param(IS_FUNCTIONAL_STATE(NewState));
758 if (NewState != DISABLE)
759 {
760 RCC->APB2ENR |= RCC_APB2Periph;
761 }
762 else
763 {
764 RCC->APB2ENR &= ~RCC_APB2Periph;
765 }
766 }
767
768 /**
769 * @brief Enables or disables the Low Speed APB (APB1) peripheral clock.
770 * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock.
771 * This parameter can be any combination of the following values:
772 * @arg RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4,
773 * RCC_APB1Periph_TIM5, RCC_APB1Periph_TIM6, RCC_APB1Periph_TIM7,
774 * RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_SPI3,
775 * RCC_APB1Periph_USART2, RCC_APB1Periph_USART3, RCC_APB1Periph_USART4,
776 * RCC_APB1Periph_USART5, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2,
777 * RCC_APB1Periph_USB, RCC_APB1Periph_CAN1, RCC_APB1Periph_BKP,
778 * RCC_APB1Periph_PWR, RCC_APB1Periph_DAC, RCC_APB1Periph_CEC,
779 * RCC_APB1Periph_TIM12, RCC_APB1Periph_TIM13, RCC_APB1Periph_TIM14
780 * @param NewState: new state of the specified peripheral clock.
781 * This parameter can be: ENABLE or DISABLE.
782 * @retval None
783 */
RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph,FunctionalState NewState)784 void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
785 {
786 /* Check the parameters */
787 assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
788 assert_param(IS_FUNCTIONAL_STATE(NewState));
789 if (NewState != DISABLE)
790 {
791 RCC->APB1ENR |= RCC_APB1Periph;
792 }
793 else
794 {
795 RCC->APB1ENR &= ~RCC_APB1Periph;
796 }
797 }
798
799 /**
800 * @brief Forces or releases High Speed APB (APB2) peripheral reset.
801 * @param RCC_APB2Periph: specifies the APB2 peripheral to reset.
802 * This parameter can be any combination of the following values:
803 * @arg RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB,
804 * RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE,
805 * RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, RCC_APB2Periph_ADC1,
806 * RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1, RCC_APB2Periph_SPI1,
807 * RCC_APB2Periph_TIM8, RCC_APB2Periph_USART1, RCC_APB2Periph_ADC3,
808 * RCC_APB2Periph_TIM15, RCC_APB2Periph_TIM16, RCC_APB2Periph_TIM17,
809 * RCC_APB2Periph_TIM9, RCC_APB2Periph_TIM10, RCC_APB2Periph_TIM11
810 * @param NewState: new state of the specified peripheral reset.
811 * This parameter can be: ENABLE or DISABLE.
812 * @retval None
813 */
RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph,FunctionalState NewState)814 void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
815 {
816 /* Check the parameters */
817 assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
818 assert_param(IS_FUNCTIONAL_STATE(NewState));
819 if (NewState != DISABLE)
820 {
821 RCC->APB2RSTR |= RCC_APB2Periph;
822 }
823 else
824 {
825 RCC->APB2RSTR &= ~RCC_APB2Periph;
826 }
827 }
828
829 /**
830 * @brief Forces or releases Low Speed APB (APB1) peripheral reset.
831 * @param RCC_APB1Periph: specifies the APB1 peripheral to reset.
832 * This parameter can be any combination of the following values:
833 * @arg RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4,
834 * RCC_APB1Periph_TIM5, RCC_APB1Periph_TIM6, RCC_APB1Periph_TIM7,
835 * RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_SPI3,
836 * RCC_APB1Periph_USART2, RCC_APB1Periph_USART3, RCC_APB1Periph_USART4,
837 * RCC_APB1Periph_USART5, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2,
838 * RCC_APB1Periph_USB, RCC_APB1Periph_CAN1, RCC_APB1Periph_BKP,
839 * RCC_APB1Periph_PWR, RCC_APB1Periph_DAC, RCC_APB1Periph_CEC,
840 * RCC_APB1Periph_TIM12, RCC_APB1Periph_TIM13, RCC_APB1Periph_TIM14
841 * @param NewState: new state of the specified peripheral clock.
842 * This parameter can be: ENABLE or DISABLE.
843 * @retval None
844 */
RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph,FunctionalState NewState)845 void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
846 {
847 /* Check the parameters */
848 assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
849 assert_param(IS_FUNCTIONAL_STATE(NewState));
850 if (NewState != DISABLE)
851 {
852 RCC->APB1RSTR |= RCC_APB1Periph;
853 }
854 else
855 {
856 RCC->APB1RSTR &= ~RCC_APB1Periph;
857 }
858 }
859
860 /**
861 * @brief Forces or releases the Backup domain reset.
862 * @param NewState: new state of the Backup domain reset.
863 * This parameter can be: ENABLE or DISABLE.
864 * @retval None
865 */
RCC_BackupResetCmd(FunctionalState NewState)866 void RCC_BackupResetCmd(FunctionalState NewState)
867 {
868 /* Check the parameters */
869 assert_param(IS_FUNCTIONAL_STATE(NewState));
870 *(__IO uint32_t *) BDCR_BDRST_BB = (uint32_t)NewState;
871 }
872
873 /**
874 * @brief Enables or disables the Clock Security System.
875 * @param NewState: new state of the Clock Security System..
876 * This parameter can be: ENABLE or DISABLE.
877 * @retval None
878 */
RCC_ClockSecuritySystemCmd(FunctionalState NewState)879 void RCC_ClockSecuritySystemCmd(FunctionalState NewState)
880 {
881 /* Check the parameters */
882 assert_param(IS_FUNCTIONAL_STATE(NewState));
883 *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)NewState;
884 }
885
886 /**
887 * @brief Selects the clock source to output on MCO pin.
888 * @param RCC_MCO: specifies the clock source to output.
889 *
890 * For @b air32_Connectivity_line_devices, this parameter can be one of the
891 * following values:
892 * @arg RCC_MCO_NoClock: No clock selected
893 * @arg RCC_MCO_SYSCLK: System clock selected
894 * @arg RCC_MCO_HSI: HSI oscillator clock selected
895 * @arg RCC_MCO_HSE: HSE oscillator clock selected
896 * @arg RCC_MCO_PLLCLK_Div2: PLL clock divided by 2 selected
897 * @arg RCC_MCO_PLL2CLK: PLL2 clock selected
898 * @arg RCC_MCO_PLL3CLK_Div2: PLL3 clock divided by 2 selected
899 * @arg RCC_MCO_XT1: External 3-25 MHz oscillator clock selected
900 * @arg RCC_MCO_PLL3CLK: PLL3 clock selected
901 *
902 * For @b other_air32_devices, this parameter can be one of the following values:
903 * @arg RCC_MCO_NoClock: No clock selected
904 * @arg RCC_MCO_SYSCLK: System clock selected
905 * @arg RCC_MCO_HSI: HSI oscillator clock selected
906 * @arg RCC_MCO_HSE: HSE oscillator clock selected
907 * @arg RCC_MCO_PLLCLK_Div2: PLL clock divided by 2 selected
908 *
909 * @retval None
910 */
RCC_MCOConfig(uint8_t RCC_MCO)911 void RCC_MCOConfig(uint8_t RCC_MCO)
912 {
913 /* Check the parameters */
914 assert_param(IS_RCC_MCO(RCC_MCO));
915
916 if(RCC_MCO <= RCC_MCO_PLLCLK_Div2)
917 {
918 /* Perform Byte access to MCO bits to select the MCO source */
919 *(__IO uint8_t *) CFGR_BYTE4_ADDRESS = RCC_MCO;
920 }
921 else
922 {
923 *(__IO uint8_t *) CFGR_BYTE4_ADDRESS = RCC_MCO_PLLCLK_Div2;
924 }
925 RCC->RCC_MCO_VAL = RCC_MCO - 6;
926 }
927
928 /**
929 * @brief Checks whether the specified RCC flag is set or not.
930 * @param RCC_FLAG: specifies the flag to check.
931 *
932 * For @b air32_Connectivity_line_devices, this parameter can be one of the
933 * following values:
934 * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
935 * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
936 * @arg RCC_FLAG_PLLRDY: PLL clock ready
937 * @arg RCC_FLAG_PLL2RDY: PLL2 clock ready
938 * @arg RCC_FLAG_PLL3RDY: PLL3 clock ready
939 * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
940 * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
941 * @arg RCC_FLAG_PINRST: Pin reset
942 * @arg RCC_FLAG_PORRST: POR/PDR reset
943 * @arg RCC_FLAG_SFTRST: Software reset
944 * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset
945 * @arg RCC_FLAG_WWDGRST: Window Watchdog reset
946 * @arg RCC_FLAG_LPWRRST: Low Power reset
947 *
948 * For @b other_air32_devices, this parameter can be one of the following values:
949 * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
950 * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
951 * @arg RCC_FLAG_PLLRDY: PLL clock ready
952 * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
953 * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
954 * @arg RCC_FLAG_PINRST: Pin reset
955 * @arg RCC_FLAG_PORRST: POR/PDR reset
956 * @arg RCC_FLAG_SFTRST: Software reset
957 * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset
958 * @arg RCC_FLAG_WWDGRST: Window Watchdog reset
959 * @arg RCC_FLAG_LPWRRST: Low Power reset
960 *
961 * @retval The new state of RCC_FLAG (SET or RESET).
962 */
RCC_GetFlagStatus(uint8_t RCC_FLAG)963 FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG)
964 {
965 uint32_t tmp = 0;
966 uint32_t statusreg = 0;
967 FlagStatus bitstatus = RESET;
968 /* Check the parameters */
969 assert_param(IS_RCC_FLAG(RCC_FLAG));
970
971 /* Get the RCC register index */
972 tmp = RCC_FLAG >> 5;
973 if (tmp == 1) /* The flag to check is in CR register */
974 {
975 statusreg = RCC->CR;
976 }
977 else if (tmp == 2) /* The flag to check is in BDCR register */
978 {
979 statusreg = RCC->BDCR;
980 }
981 else /* The flag to check is in CSR register */
982 {
983 statusreg = RCC->CSR;
984 }
985
986 /* Get the flag position */
987 tmp = RCC_FLAG & FLAG_Mask;
988 if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET)
989 {
990 bitstatus = SET;
991 }
992 else
993 {
994 bitstatus = RESET;
995 }
996
997 /* Return the flag status */
998 return bitstatus;
999 }
1000
1001 /**
1002 * @brief Clears the RCC reset flags.
1003 * @note The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST,
1004 * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
1005 * @param None
1006 * @retval None
1007 */
RCC_ClearFlag(void)1008 void RCC_ClearFlag(void)
1009 {
1010 /* Set RMVF bit to clear the reset flags */
1011 RCC->CSR |= CSR_RMVF_Set;
1012 }
1013
1014 /**
1015 * @brief Checks whether the specified RCC interrupt has occurred or not.
1016 * @param RCC_IT: specifies the RCC interrupt source to check.
1017 *
1018 * For @b air32_Connectivity_line_devices, this parameter can be one of the
1019 * following values:
1020 * @arg RCC_IT_LSIRDY: LSI ready interrupt
1021 * @arg RCC_IT_LSERDY: LSE ready interrupt
1022 * @arg RCC_IT_HSIRDY: HSI ready interrupt
1023 * @arg RCC_IT_HSERDY: HSE ready interrupt
1024 * @arg RCC_IT_PLLRDY: PLL ready interrupt
1025 * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt
1026 * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt
1027 * @arg RCC_IT_CSS: Clock Security System interrupt
1028 *
1029 * For @b other_air32_devices, this parameter can be one of the following values:
1030 * @arg RCC_IT_LSIRDY: LSI ready interrupt
1031 * @arg RCC_IT_LSERDY: LSE ready interrupt
1032 * @arg RCC_IT_HSIRDY: HSI ready interrupt
1033 * @arg RCC_IT_HSERDY: HSE ready interrupt
1034 * @arg RCC_IT_PLLRDY: PLL ready interrupt
1035 * @arg RCC_IT_CSS: Clock Security System interrupt
1036 *
1037 * @retval The new state of RCC_IT (SET or RESET).
1038 */
RCC_GetITStatus(uint8_t RCC_IT)1039 ITStatus RCC_GetITStatus(uint8_t RCC_IT)
1040 {
1041 ITStatus bitstatus = RESET;
1042 /* Check the parameters */
1043 assert_param(IS_RCC_GET_IT(RCC_IT));
1044
1045 /* Check the status of the specified RCC interrupt */
1046 if ((RCC->CIR & RCC_IT) != (uint32_t)RESET)
1047 {
1048 bitstatus = SET;
1049 }
1050 else
1051 {
1052 bitstatus = RESET;
1053 }
1054
1055 /* Return the RCC_IT status */
1056 return bitstatus;
1057 }
1058
1059 /**
1060 * @brief Clears the RCC's interrupt pending bits.
1061 * @param RCC_IT: specifies the interrupt pending bit to clear.
1062 *
1063 * For @b air32_Connectivity_line_devices, this parameter can be any combination
1064 * of the following values:
1065 * @arg RCC_IT_LSIRDY: LSI ready interrupt
1066 * @arg RCC_IT_LSERDY: LSE ready interrupt
1067 * @arg RCC_IT_HSIRDY: HSI ready interrupt
1068 * @arg RCC_IT_HSERDY: HSE ready interrupt
1069 * @arg RCC_IT_PLLRDY: PLL ready interrupt
1070 * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt
1071 * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt
1072 * @arg RCC_IT_CSS: Clock Security System interrupt
1073 *
1074 * For @b other_air32_devices, this parameter can be any combination of the
1075 * following values:
1076 * @arg RCC_IT_LSIRDY: LSI ready interrupt
1077 * @arg RCC_IT_LSERDY: LSE ready interrupt
1078 * @arg RCC_IT_HSIRDY: HSI ready interrupt
1079 * @arg RCC_IT_HSERDY: HSE ready interrupt
1080 * @arg RCC_IT_PLLRDY: PLL ready interrupt
1081 *
1082 * @arg RCC_IT_CSS: Clock Security System interrupt
1083 * @retval None
1084 */
RCC_ClearITPendingBit(uint8_t RCC_IT)1085 void RCC_ClearITPendingBit(uint8_t RCC_IT)
1086 {
1087 /* Check the parameters */
1088 assert_param(IS_RCC_CLEAR_IT(RCC_IT));
1089
1090 /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt
1091 pending bits */
1092 *(__IO uint8_t *) CIR_BYTE3_ADDRESS = RCC_IT;
1093 }
1094
1095 /**
1096 * @}
1097 */
1098
1099 /**
1100 * @}
1101 */
1102
1103 /**
1104 * @}
1105 */
1106
1107