1 #include <stdlib.h>
2 #include <string.h>
3 #include <stdio.h>
4 #include <stdint.h>
5 #include "air32f10x.h"
6 #include "air32f10x_rcc_ex.h"
7 
8 /* ------------ RCC registers bit address in the alias region ----------- */
9 #define RCC_OFFSET                (RCC_BASE - PERIPH_BASE)
10 
11 /* --- CR Register ---*/
12 
13 /* Alias word address of HSION bit */
14 #define CR_OFFSET                 (RCC_OFFSET + 0x00)
15 #define HSION_BitNumber           0x00
16 #define CR_HSION_BB               (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4))
17 
18 /* Alias word address of PLLON bit */
19 #define PLLON_BitNumber           0x18
20 #define CR_PLLON_BB               (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4))
21 
22 #ifdef air32F10X_CL
23  /* Alias word address of PLL2ON bit */
24  #define PLL2ON_BitNumber          0x1A
25  #define CR_PLL2ON_BB              (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLL2ON_BitNumber * 4))
26 
27  /* Alias word address of PLL3ON bit */
28  #define PLL3ON_BitNumber          0x1C
29  #define CR_PLL3ON_BB              (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLL3ON_BitNumber * 4))
30 #endif /* air32F10X_CL */
31 
32 /* Alias word address of CSSON bit */
33 #define CSSON_BitNumber           0x13
34 #define CR_CSSON_BB               (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4))
35 
36 /* --- CFGR Register ---*/
37 
38 /* Alias word address of USBPRE bit */
39 #define CFGR_OFFSET               (RCC_OFFSET + 0x04)
40 
41 #ifndef air32F10X_CL
42  #define USBPRE_BitNumber          0x16
43  #define CFGR_USBPRE_BB            (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (USBPRE_BitNumber * 4))
44 #else
45  #define OTGFSPRE_BitNumber        0x16
46  #define CFGR_OTGFSPRE_BB          (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (OTGFSPRE_BitNumber * 4))
47 #endif /* air32F10X_CL */
48 
49 /* --- BDCR Register ---*/
50 
51 /* Alias word address of RTCEN bit */
52 #define BDCR_OFFSET               (RCC_OFFSET + 0x20)
53 #define RTCEN_BitNumber           0x0F
54 #define BDCR_RTCEN_BB             (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4))
55 
56 /* Alias word address of BDRST bit */
57 #define BDRST_BitNumber           0x10
58 #define BDCR_BDRST_BB             (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4))
59 
60 /* --- CSR Register ---*/
61 
62 /* Alias word address of LSION bit */
63 #define CSR_OFFSET                (RCC_OFFSET + 0x24)
64 #define LSION_BitNumber           0x00
65 #define CSR_LSION_BB              (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4))
66 
67 #ifdef air32F10X_CL
68 /* --- CFGR2 Register ---*/
69 
70  /* Alias word address of I2S2SRC bit */
71  #define CFGR2_OFFSET              (RCC_OFFSET + 0x2C)
72  #define I2S2SRC_BitNumber         0x11
73  #define CFGR2_I2S2SRC_BB          (PERIPH_BB_BASE + (CFGR2_OFFSET * 32) + (I2S2SRC_BitNumber * 4))
74 
75  /* Alias word address of I2S3SRC bit */
76  #define I2S3SRC_BitNumber         0x12
77  #define CFGR2_I2S3SRC_BB          (PERIPH_BB_BASE + (CFGR2_OFFSET * 32) + (I2S3SRC_BitNumber * 4))
78 #endif /* air32F10X_CL */
79 
80 /* ---------------------- RCC registers bit mask ------------------------ */
81 
82 /* CR register bit mask */
83 #define CR_HSEBYP_Reset           ((volatile uint32_t)0xFFFBFFFF)
84 #define CR_HSEBYP_Set             ((volatile uint32_t)0x00040000)
85 #define CR_HSEON_Reset            ((volatile uint32_t)0xFFFEFFFF)
86 #define CR_HSEON_Set              ((volatile uint32_t)0x00010000)
87 #define CR_HSITRIM_Mask           ((volatile uint32_t)0xFFFFFF07)
88 
89 /* CFGR register bit mask */
90 #if defined (air32F10X_LD_VL) || defined (air32F10X_MD_VL) || defined (air32F10X_HD_VL) || defined (air32F10X_CL)
91  #define CFGR_PLL_Mask            ((volatile uint32_t)0xFFC2FFFF)
92 #else
93  #define CFGR_PLL_Mask            ((volatile uint32_t)0xFFC0FFFF)
94 #endif /* air32F10X_CL */
95 
96 #define CFGR_PLLMull_Mask         ((volatile uint32_t)0x003C0000)
97 #define CFGR_PLLSRC_Mask          ((volatile uint32_t)0x00010000)
98 #define CFGR_PLLXTPRE_Mask        ((volatile uint32_t)0x00020000)
99 #define CFGR_SWS_Mask             ((volatile uint32_t)0x0000000C)
100 #define CFGR_SW_Mask              ((volatile uint32_t)0xFFFFFFFC)
101 #define CFGR_HPRE_Reset_Mask      ((volatile uint32_t)0xFFFFFF0F)
102 #define CFGR_HPRE_Set_Mask        ((volatile uint32_t)0x000000F0)
103 #define CFGR_PPRE1_Reset_Mask     ((volatile uint32_t)0xFFFFF8FF)
104 #define CFGR_PPRE1_Set_Mask       ((volatile uint32_t)0x00000700)
105 #define CFGR_PPRE2_Reset_Mask     ((volatile uint32_t)0xFFFFC7FF)
106 #define CFGR_PPRE2_Set_Mask       ((volatile uint32_t)0x00003800)
107 #define CFGR_ADCPRE_Reset_Mask    ((volatile uint32_t)0x9FFF3FFF)
108 #define CFGR_ADCPRE_Set_Mask      ((volatile uint32_t)0x0000C000)
109 
110 /* CSR register bit mask */
111 #define CSR_RMVF_Set              ((volatile uint32_t)0x01000000)
112 
113 #if defined (air32F10X_LD_VL) || defined (air32F10X_MD_VL) || defined (air32F10X_HD_VL) || defined (air32F10X_CL)
114 /* CFGR2 register bit mask */
115  #define CFGR2_PREDIV1SRC         ((volatile uint32_t)0x00010000)
116  #define CFGR2_PREDIV1            ((volatile uint32_t)0x0000000F)
117 #endif
118 #ifdef air32F10X_CL
119  #define CFGR2_PREDIV2            ((volatile uint32_t)0x000000F0)
120  #define CFGR2_PLL2MUL            ((volatile uint32_t)0x00000F00)
121  #define CFGR2_PLL3MUL            ((volatile uint32_t)0x0000F000)
122 #endif /* air32F10X_CL */
123 
124 /* RCC Flag Mask */
125 #define FLAG_Mask                 ((volatile uint8_t)0x1F)
126 
127 /* CIR register byte 2 (Bits[15:8]) base address */
128 #define CIR_BYTE2_ADDRESS         ((volatile uint32_t)0x40021009)
129 
130 /* CIR register byte 3 (Bits[23:16]) base address */
131 #define CIR_BYTE3_ADDRESS         ((volatile uint32_t)0x4002100A)
132 
133 /* CFGR register byte 4 (Bits[31:24]) base address */
134 #define CFGR_BYTE4_ADDRESS        ((volatile uint32_t)0x40021007)
135 
136 /* BDCR register base address */
137 #define BDCR_ADDRESS              (PERIPH_BASE + BDCR_OFFSET)
138 
139 /**
140   * @}
141   */
142 
143 /** @defgroup RCC_Private_Macros
144   * @{
145   */
146 
147 /**
148   * @}
149   */
150 
151 /** @defgroup RCC_Private_Variables
152   * @{
153   */
154 
155 static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
156 static __I uint8_t ADCPrescTable[4] = {2, 4, 6, 8};
157 
158 #define SysFreq_Set     (*((void (*)(uint32_t, FlashClkDiv , uint8_t, uint8_t))(*(uint32_t *)0x1FFFD00C)))
159 
AIR_RCC_PLLConfig(uint32_t RCC_PLLSource,uint32_t RCC_PLLMul,FlashClkDiv Latency)160 uint32_t AIR_RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul, FlashClkDiv Latency)
161 {
162     // uint32_t pllmul = 0;
163     // FunctionalState pwr_gating_state = 0;
164     /* Check the parameters */
165     assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource));
166     assert_param(IS_RCC_PLL_MUL(RCC_PLLMul));
167 
168     *(volatile uint32_t *)(0x400210F0) = BIT(0);//开启sys_cfg门控
169     *(volatile uint32_t *)(0x40016C00) = 0xa7d93a86;//解一、二、三级锁
170     *(volatile uint32_t *)(0x40016C00) = 0xab12dfcd;
171     *(volatile uint32_t *)(0x40016C00) = 0xcded3526;
172     *(volatile uint32_t *)(0x4002228C) = 0xa5a5a5a5;//QSPI解锁
173 
174     SysFreq_Set(RCC_PLLMul,Latency ,0,1);
175     RCC->CFGR = (RCC->CFGR & ~0x00030000) | RCC_PLLSource;
176 
177     //恢复配置前状态
178     *(volatile uint32_t *)(0x400210F0) = 0;//开启sys_cfg门控
179     *(volatile uint32_t *)(0x40016C00) = ~0xa7d93a86;//加一、二、三级锁
180     *(volatile uint32_t *)(0x40016C00) = ~0xab12dfcd;
181     *(volatile uint32_t *)(0x40016C00) = ~0xcded3526;
182     *(volatile uint32_t *)(0x4002228C) = ~0xa5a5a5a5;//QSPI解锁
183 
184 
185     return 1;
186 }
187