1 /* Copyright (c) 2019-2025 Allwinner Technology Co., Ltd. ALL rights reserved.
2 *
3 * Allwinner is a trademark of Allwinner Technology Co.,Ltd., registered in
4 *the the People's Republic of China and other countries.
5 * All Allwinner Technology Co.,Ltd. trademarks are used with permission.
6 *
7 * DISCLAIMER
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13 * COVERED UNDER ANY REQUIRED THIRD PARTY LICENSE.
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30 */
31
32 #include <hal_clk.h>
33
hal_clock_init(void)34 void hal_clock_init(void)
35 {
36 CCMU_TRACE();
37 clk_init();
38 }
39
hal_clock_get(hal_clk_type_t type,hal_clk_id_t id)40 hal_clk_t hal_clock_get(hal_clk_type_t type, hal_clk_id_t id)
41 {
42 CCMU_TRACE();
43 return clk_get(type, id);
44 }
45
hal_clock_put(hal_clk_t clk)46 hal_clk_status_t hal_clock_put(hal_clk_t clk)
47 {
48 CCMU_TRACE();
49 return clk_put(clk);
50 }
51
hal_clk_set_parent(hal_clk_t clk,hal_clk_t parent)52 hal_clk_status_t hal_clk_set_parent(hal_clk_t clk, hal_clk_t parent)
53 {
54 CCMU_TRACE();
55 return clk_set_parent(clk, parent);
56 }
57
hal_clk_get_parent(hal_clk_t clk)58 hal_clk_t hal_clk_get_parent(hal_clk_t clk)
59 {
60 CCMU_TRACE();
61 return clk_get_parent(clk);
62 }
63
hal_clk_recalc_rate(hal_clk_t clk)64 u32 hal_clk_recalc_rate(hal_clk_t clk)
65 {
66 u32 rate = 0;
67
68 CCMU_TRACE();
69 clk_recalc_rate(clk, &rate);
70
71 return rate;
72 }
73
hal_clk_round_rate(hal_clk_t clk,u32 rate)74 u32 hal_clk_round_rate(hal_clk_t clk, u32 rate)
75 {
76 u32 round_rate = 0;
77
78 CCMU_TRACE();
79 clk_round_rate(clk, rate, &round_rate);
80
81 return round_rate;
82 }
83
hal_clk_get_rate(hal_clk_t clk)84 u32 hal_clk_get_rate(hal_clk_t clk)
85 {
86 u32 rate;
87
88 CCMU_TRACE();
89 clk_get_rate(clk, &rate);
90
91 return rate;
92 }
93
hal_clk_set_rate(hal_clk_t clk,u32 rate)94 hal_clk_status_t hal_clk_set_rate(hal_clk_t clk, u32 rate)
95 {
96 hal_clk_status_t ret;
97
98 CCMU_TRACE();
99 ret = clk_set_rate(clk, rate);
100
101 return ret;
102 }
103
hal_clock_is_enabled(hal_clk_t clk)104 hal_clk_status_t hal_clock_is_enabled(hal_clk_t clk)
105 {
106 CCMU_TRACE();
107 return clk_is_enabled(clk);
108 }
109
hal_clock_enable(hal_clk_t clk)110 hal_clk_status_t hal_clock_enable(hal_clk_t clk)
111 {
112 hal_clk_status_t ret;
113
114 CCMU_TRACE();
115 ret = clk_prepare_enable(clk);
116
117 return ret;
118 }
119
120
hal_clock_disable(hal_clk_t clk)121 hal_clk_status_t hal_clock_disable(hal_clk_t clk)
122 {
123 hal_clk_status_t ret;
124
125 CCMU_TRACE();
126 ret = clk_disable_unprepare(clk);
127
128 return ret;
129 }
130