1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2020 huangzhenwei@allwinnertech.com
4 */
5 #include "ccu.h"
6 #include "ccu_common.h"
7 #include "ccu_reset.h"
8
9 #include "ccu_div.h"
10 #include "ccu_gate.h"
11 #include "ccu_mp.h"
12 #include "ccu_nm.h"
13
14 #include "ccu-sun8iw20-r.h"
15
16 static const char *const ahbs_apbs0_parents[] = { "dcxo24M", "osc32k",
17 "iosc", "pll-periph0-div3"
18 };
19
20 static SUNXI_CCU_MP_WITH_MUX(r_ahb_clk, "r-ahb",
21 ahbs_apbs0_parents, 0x000,
22 0, 5,
23 8, 2,
24 24, 3,
25 0);
26
27 static SUNXI_CCU_MP_WITH_MUX(r_apb0_clk, "r-apb0",
28 ahbs_apbs0_parents, 0x00c,
29 0, 5,
30 8, 2,
31 24, 3,
32 0);
33
34 static SUNXI_CCU_GATE(r_apb0_timer_clk, "r-apb0-timer", "r-apb0",
35 0x11c, BIT(0), 0);
36
37 static SUNXI_CCU_GATE(r_apb0_twd_clk, "r-apb0-twd", "r-apb0",
38 0x12c, BIT(0), 0);
39
40 static SUNXI_CCU_GATE(r_ppu_clk, "r-ppu", "r-apb0",
41 0x1ac, BIT(0), 0);
42
43 static const char *const r_apb0_ir_rx_parents[] = { "osc32k", "dcxo24M" };
44 static SUNXI_CCU_MP_WITH_MUX_GATE(r_apb0_ir_rx_clk, "r-apb0-ir-rx",
45 r_apb0_ir_rx_parents, 0x1c0,
46 0, 5, /* M */
47 8, 2, /* P */
48 24, 2, /* mux */
49 BIT(31), /* gate */
50 0);
51
52 static SUNXI_CCU_GATE(r_apb0_bus_ir_rx_clk, "r-apb0-bus-ir-rx", "r-apb0",
53 0x1cc, BIT(0), 0);
54
55 static SUNXI_CCU_GATE(r_ahb_bus_rtc_clk, "r-ahb-rtc", "r-ahb",
56 0x20c, BIT(0), 0);
57
58 static SUNXI_CCU_GATE(r_apb0_cpucfg_clk, "r-apb0-cpucfg", "r-apb0",
59 0x22c, BIT(0), 0);
60
61 static struct ccu_common *sun8iw20_r_ccu_clks[] =
62 {
63 &r_ahb_clk.common,
64 &r_apb0_clk.common,
65 &r_apb0_timer_clk.common,
66 &r_apb0_twd_clk.common,
67 &r_ppu_clk.common,
68 &r_apb0_ir_rx_clk.common,
69 &r_apb0_bus_ir_rx_clk.common,
70 &r_ahb_bus_rtc_clk.common,
71 &r_apb0_cpucfg_clk.common,
72 };
73
74 static struct clk_hw_onecell_data sun8iw20_r_hw_clks =
75 {
76 .hws = {
77 [CLK_R_AHB] = &r_ahb_clk.common.hw,
78 [CLK_R_APB0] = &r_apb0_clk.common.hw,
79 [CLK_R_APB0_TIMER] = &r_apb0_timer_clk.common.hw,
80 [CLK_R_APB0_TWD] = &r_apb0_twd_clk.common.hw,
81 [CLK_R_PPU] = &r_ppu_clk.common.hw,
82 [CLK_R_APB0_IRRX] = &r_apb0_ir_rx_clk.common.hw,
83 [CLK_R_APB0_BUS_IRRX] = &r_apb0_bus_ir_rx_clk.common.hw,
84 [CLK_R_AHB_BUS_RTC] = &r_ahb_bus_rtc_clk.common.hw,
85 [CLK_R_APB0_CPUCFG] = &r_apb0_cpucfg_clk.common.hw,
86 },
87 .num = CLK_R_NUMBER,
88 };
89
90 static struct ccu_reset_map sun8iw20_r_ccu_resets[] =
91 {
92 [RST_R_APB0_TIMER] = { 0x11c, BIT(16) },
93 [RST_R_APB0_TWD] = { 0x12c, BIT(16) },
94 [RST_R_PPU] = { 0x1ac, BIT(16) },
95 [RST_R_APB0_BUS_IRRX] = { 0x1cc, BIT(16) },
96 [RST_R_AHB_BUS_RTC] = { 0x20c, BIT(16) },
97 [RST_R_APB0_CPUCFG] = { 0x22c, BIT(16) },
98 };
99
100 static const struct sunxi_ccu_desc sun8iw20_r_ccu_desc =
101 {
102 .ccu_clks = sun8iw20_r_ccu_clks,
103 .num_ccu_clks = ARRAY_SIZE(sun8iw20_r_ccu_clks),
104
105 .hw_clks = &sun8iw20_r_hw_clks,
106 .clk_type = HAL_SUNXI_R_CCU,
107
108 .resets = sun8iw20_r_ccu_resets,
109 .reset_type = HAL_SUNXI_R_RESET,
110 .num_resets = ARRAY_SIZE(sun8iw20_r_ccu_resets),
111 };
112
sunxi_r_ccu_init(void)113 int sunxi_r_ccu_init(void)
114 {
115 unsigned long reg = (unsigned long)SUNXI_R_CCU_BASE;
116
117 return ccu_common_init(reg, &sun8iw20_r_ccu_desc);
118 }
119
120