1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * Copyright (C) 2016 Maxime Ripard
4  * Maxime Ripard <maxime.ripard@free-electrons.com>
5  */
6 #include "ccu.h"
7 #include "ccu_gate.h"
8 #include "ccu_div.h"
9 
ccu_div_round_rate(struct ccu_mux_internal * mux,struct clk_hw * parent,unsigned long * parent_rate,unsigned long rate,void * data)10 static unsigned long ccu_div_round_rate(struct ccu_mux_internal *mux,
11                                         struct clk_hw *parent,
12                                         unsigned long *parent_rate,
13                                         unsigned long rate,
14                                         void *data)
15 {
16     struct ccu_div *cd = data;
17 
18     if (cd->common.features & CCU_FEATURE_FIXED_POSTDIV)
19     {
20         rate *= cd->fixed_post_div;
21     }
22 
23     rate = divider_round_rate_parent(&cd->common.hw, parent,
24                                      rate, parent_rate,
25                                      cd->div.table, cd->div.width,
26                                      cd->div.flags);
27 
28     if (cd->common.features & CCU_FEATURE_FIXED_POSTDIV)
29     {
30         rate /= cd->fixed_post_div;
31     }
32 
33     return rate;
34 }
35 
ccu_div_disable(struct clk_hw * hw)36 static void ccu_div_disable(struct clk_hw *hw)
37 {
38     struct ccu_div *cd = hw_to_ccu_div(hw);
39 
40     return ccu_gate_helper_disable(&cd->common, cd->enable);
41 }
42 
ccu_div_enable(struct clk_hw * hw)43 static int ccu_div_enable(struct clk_hw *hw)
44 {
45     struct ccu_div *cd = hw_to_ccu_div(hw);
46 
47     return ccu_gate_helper_enable(&cd->common, cd->enable);
48 }
49 
ccu_div_is_enabled(struct clk_hw * hw)50 static int ccu_div_is_enabled(struct clk_hw *hw)
51 {
52     struct ccu_div *cd = hw_to_ccu_div(hw);
53 
54     return ccu_gate_helper_is_enabled(&cd->common, cd->enable);
55 }
56 
ccu_div_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)57 static unsigned long ccu_div_recalc_rate(struct clk_hw *hw,
58         unsigned long parent_rate)
59 {
60     struct ccu_div *cd = hw_to_ccu_div(hw);
61     unsigned long val;
62     u32 reg;
63 
64     reg = readl(cd->common.base + cd->common.reg);
65     val = reg >> cd->div.shift;
66     val &= (1 << cd->div.width) - 1;
67 
68     parent_rate = ccu_mux_helper_apply_prediv(&cd->common, &cd->mux, -1,
69                   parent_rate);
70 
71     val = divider_recalc_rate(hw, parent_rate, val, cd->div.table,
72                               cd->div.flags, cd->div.width);
73 
74     if (cd->common.features & CCU_FEATURE_FIXED_POSTDIV)
75     {
76         val /= cd->fixed_post_div;
77     }
78 
79     return val;
80 }
81 
ccu_div_determine_rate(struct clk_hw * hw,struct clk_rate_request * req)82 static int ccu_div_determine_rate(struct clk_hw *hw,
83                                   struct clk_rate_request *req)
84 {
85     struct ccu_div *cd = hw_to_ccu_div(hw);
86 
87     return ccu_mux_helper_determine_rate(&cd->common, &cd->mux,
88                                          req, ccu_div_round_rate, cd);
89 }
90 
ccu_div_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)91 static int ccu_div_set_rate(struct clk_hw *hw, unsigned long rate,
92                             unsigned long parent_rate)
93 {
94     struct ccu_div *cd = hw_to_ccu_div(hw);
95     unsigned long val = 0;
96     u32 reg;
97     u32 __cspr;
98 
99     parent_rate = ccu_mux_helper_apply_prediv(&cd->common, &cd->mux, -1,
100                   parent_rate);
101 
102     if (cd->common.features & CCU_FEATURE_FIXED_POSTDIV)
103     {
104         rate *= cd->fixed_post_div;
105     }
106 
107     val = divider_get_val(rate, parent_rate, cd->div.table, cd->div.width,
108                           cd->div.flags);
109 
110     __cspr = hal_spin_lock_irqsave(&cd->common.lock);
111 
112     reg = readl(cd->common.base + cd->common.reg);
113     reg &= ~GENMASK(cd->div.width + cd->div.shift - 1, cd->div.shift);
114 
115     writel(reg | (val << cd->div.shift),
116            cd->common.base + cd->common.reg);
117 
118     hal_spin_unlock_irqrestore(&cd->common.lock, __cspr);
119 
120     return 0;
121 }
122 
ccu_div_get_parent(struct clk_hw * hw)123 static u8 ccu_div_get_parent(struct clk_hw *hw)
124 {
125     struct ccu_div *cd = hw_to_ccu_div(hw);
126 
127     return ccu_mux_helper_get_parent(&cd->common, &cd->mux);
128 }
129 
ccu_div_set_parent(struct clk_hw * hw,u8 index)130 static int ccu_div_set_parent(struct clk_hw *hw, u8 index)
131 {
132     struct ccu_div *cd = hw_to_ccu_div(hw);
133 
134     return ccu_mux_helper_set_parent(&cd->common, &cd->mux, index);
135 }
136 
137 const struct clk_ops ccu_div_ops =
138 {
139     .disable    = ccu_div_disable,
140     .enable     = ccu_div_enable,
141     .is_enabled = ccu_div_is_enabled,
142 
143     .get_parent = ccu_div_get_parent,
144     .set_parent = ccu_div_set_parent,
145 
146     .determine_rate = ccu_div_determine_rate,
147     .recalc_rate    = ccu_div_recalc_rate,
148     .set_rate   = ccu_div_set_rate,
149 };
150