1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * Copyright (C) 2016 Maxime Ripard
4  * Maxime Ripard <maxime.ripard@free-electrons.com>
5  */
6 
7 #include "ccu.h"
8 #include "ccu_phase.h"
9 
ccu_phase_get_phase(struct clk_hw * hw)10 static int ccu_phase_get_phase(struct clk_hw *hw)
11 {
12     struct ccu_phase *phase = hw_to_ccu_phase(hw);
13     struct clk_hw *parent, *grandparent;
14     unsigned int parent_rate, grandparent_rate;
15     u16 step, parent_div;
16     u32 reg;
17     u8 delay;
18 
19     reg = readl(phase->common.base + phase->common.reg);
20     delay = (reg >> phase->shift);
21     delay &= (1 << phase->width) - 1;
22 
23     if (!delay)
24     {
25         return 180;
26     }
27 
28     /* Get our parent clock, it's the one that can adjust its rate */
29     parent = clk_hw_get_parent(hw);
30     if (!parent)
31     {
32         return -EINVAL;
33     }
34 
35     /* And its rate */
36     parent_rate = clk_hw_get_rate(parent);
37     if (!parent_rate)
38     {
39         return -EINVAL;
40     }
41 
42     /* Now, get our parent's parent (most likely some PLL) */
43     grandparent = clk_hw_get_parent(parent);
44     if (!grandparent)
45     {
46         return -EINVAL;
47     }
48 
49     /* And its rate */
50     grandparent_rate = clk_hw_get_rate(grandparent);
51     if (!grandparent_rate)
52     {
53         return -EINVAL;
54     }
55 
56     /* Get our parent clock divider */
57     parent_div = grandparent_rate / parent_rate;
58 
59     step = DIV_ROUND_CLOSEST(360, parent_div);
60     return delay * step;
61 }
62 
ccu_phase_set_phase(struct clk_hw * hw,int degrees)63 static int ccu_phase_set_phase(struct clk_hw *hw, int degrees)
64 {
65     struct ccu_phase *phase = hw_to_ccu_phase(hw);
66     struct clk_hw *parent, *grandparent;
67     unsigned int parent_rate, grandparent_rate;
68     unsigned long flags;
69     u32 reg;
70     u8 delay;
71     u32 __cspr;
72 
73     /* Get our parent clock, it's the one that can adjust its rate */
74     parent = clk_hw_get_parent(hw);
75     if (!parent)
76     {
77         return -EINVAL;
78     }
79 
80     /* And its rate */
81     parent_rate = clk_hw_get_rate(parent);
82     if (!parent_rate)
83     {
84         return -EINVAL;
85     }
86 
87     /* Now, get our parent's parent (most likely some PLL) */
88     grandparent = clk_hw_get_parent(parent);
89     if (!grandparent)
90     {
91         return -EINVAL;
92     }
93 
94     /* And its rate */
95     grandparent_rate = clk_hw_get_rate(grandparent);
96     if (!grandparent_rate)
97     {
98         return -EINVAL;
99     }
100 
101     if (degrees != 180)
102     {
103         u16 step, parent_div;
104 
105         /* Get our parent divider */
106         parent_div = grandparent_rate / parent_rate;
107 
108         /*
109          * We can only outphase the clocks by multiple of the
110          * PLL's period.
111          *
112          * Since our parent clock is only a divider, and the
113          * formula to get the outphasing in degrees is deg =
114          * 360 * delta / period
115          *
116          * If we simplify this formula, we can see that the
117          * only thing that we're concerned about is the number
118          * of period we want to outphase our clock from, and
119          * the divider set by our parent clock.
120          */
121         step = DIV_ROUND_CLOSEST(360, parent_div);
122         delay = DIV_ROUND_CLOSEST(degrees, step);
123     }
124     else
125     {
126         delay = 0;
127     }
128 
129     __cspr = hal_spin_lock_irqsave(&phase->common.lock);
130     reg = readl(phase->common.base + phase->common.reg);
131     reg &= ~GENMASK(phase->width + phase->shift - 1, phase->shift);
132     writel(reg | (delay << phase->shift),
133            phase->common.base + phase->common.reg);
134     hal_spin_unlock_irqrestore(&phase->common.lock, __cspr);
135 
136     return 0;
137 }
138 
139 const struct clk_ops ccu_phase_ops =
140 {
141     .get_phase  = ccu_phase_get_phase,
142     .set_phase  = ccu_phase_set_phase,
143 };
144