1 /* Copyright (c) 2019-2025 Allwinner Technology Co., Ltd. ALL rights reserved. 2 * 3 * Allwinner is a trademark of Allwinner Technology Co.,Ltd., registered in 4 *the the People's Republic of China and other countries. 5 * All Allwinner Technology Co.,Ltd. trademarks are used with permission. 6 * 7 * DISCLAIMER 8 * THIRD PARTY LICENCES MAY BE REQUIRED TO IMPLEMENT THE SOLUTION/PRODUCT. 9 * IF YOU NEED TO INTEGRATE THIRD PARTY’S TECHNOLOGY (SONY, DTS, DOLBY, AVS OR MPEGLA, ETC.) 10 * IN ALLWINNERS’SDK OR PRODUCTS, YOU SHALL BE SOLELY RESPONSIBLE TO OBTAIN 11 * ALL APPROPRIATELY REQUIRED THIRD PARTY LICENCES. 12 * ALLWINNER SHALL HAVE NO WARRANTY, INDEMNITY OR OTHER OBLIGATIONS WITH RESPECT TO MATTERS 13 * COVERED UNDER ANY REQUIRED THIRD PARTY LICENSE. 14 * YOU ARE SOLELY RESPONSIBLE FOR YOUR USAGE OF THIRD PARTY’S TECHNOLOGY. 15 * 16 * 17 * THIS SOFTWARE IS PROVIDED BY ALLWINNER"AS IS" AND TO THE MAXIMUM EXTENT 18 * PERMITTED BY LAW, ALLWINNER EXPRESSLY DISCLAIMS ALL WARRANTIES OF ANY KIND, 19 * WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING WITHOUT LIMITATION REGARDING 20 * THE TITLE, NON-INFRINGEMENT, ACCURACY, CONDITION, COMPLETENESS, PERFORMANCE 21 * OR MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. 22 * IN NO EVENT SHALL ALLWINNER BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 23 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 25 * LOSS OF USE, DATA, OR PROFITS, OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 27 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED 29 * OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef __SUN8IW18P1_CLK_H__ 33 #define __SUN8IW18P1_CLK_H__ 34 35 #include <stdio.h> 36 #include <string.h> 37 #include <aw_types.h> 38 39 #include <hal_clk.h> 40 #include "../clk.h" 41 42 #define CLK_PARENT_MAX 6 43 // clk_fixed_factor_pt sunxi_clk_fixed_factor_arry[SUNXI_CLK_FIXED_FACTOR_MAX]; 44 #define SUNXI_CLK_FACTOR_CPU_MAX_FREQ (1200000000U) 45 #define SUNXI_CLK_FACTOR_DDR_MAX_FREQ (2160000000U) 46 #define SUNXI_CLK_FACTOR_PERI0_MAX_FREQ (636000000U) 47 48 /********************************************************************************/ 49 /* CCMU Register List */ 50 #define CCU_REG_BASE (0x03001000) 51 #define CLK_PLL_CPU (volatile uint32_t *)(CCU_REG_BASE + 0x0000) 52 #define CLK_PLL_DDR (volatile uint32_t *)(CCU_REG_BASE + 0x0010) 53 #define CLK_PLL_PERIPH0 (volatile uint32_t *)(CCU_REG_BASE + 0x0020) 54 #define CLK_PLL_PERIPH1 (volatile uint32_t *)(CCU_REG_BASE + 0x0028) 55 #define CLK_PLL_AUDIO (volatile uint32_t *)(CCU_REG_BASE + 0x0078) 56 #define CLK_PLL_32K (volatile uint32_t *)(CCU_REG_BASE + 0x00d8) 57 58 59 #define CLK_PLL_DDRPAT (volatile uint32_t *)(CCU_REG_BASE + 0x0110) 60 #define CLK_PLL_PERI0PAT0 (volatile uint32_t *)(CCU_REG_BASE + 0x0120) 61 #define CLK_PLL_PERI0PAT1 (volatile uint32_t *)(CCU_REG_BASE + 0x0124) 62 #define CLK_PLL_PERI1PAT0 (volatile uint32_t *)(CCU_REG_BASE + 0x0128) 63 #define CLK_PLL_PERI1PAT1 (volatile uint32_t *)(CCU_REG_BASE + 0x012C) 64 #define CLK_PLL_VIDEO0PAT0 (volatile uint32_t *)(CCU_REG_BASE + 0x0140) 65 #define CLK_PLL_VIDEO0PAT1 (volatile uint32_t *)(CCU_REG_BASE + 0x0144) 66 #define CLK_PLL_VIDEO1PAT0 (volatile uint32_t *)(CCU_REG_BASE + 0x0148) 67 #define CLK_PLL_VIDEO1PAT1 (volatile uint32_t *)(CCU_REG_BASE + 0x014C) 68 #define CLK_PLL_DEPAT0 (volatile uint32_t *)(CCU_REG_BASE + 0x0160) 69 #define CLK_PLL_AUDIOPAT0 (volatile uint32_t *)(CCU_REG_BASE + 0x0178) 70 #define CLK_PLL_AUDIOPAT1 (volatile uint32_t *)(CCU_REG_BASE + 0x017C) 71 72 73 #define CLK_CPU_CFG (volatile uint32_t *)(CCU_REG_BASE + 0x0500) 74 #define CLK_PSI_CFG (volatile uint32_t *)(CCU_REG_BASE + 0x0510) 75 #define CLK_AHB3_CFG (volatile uint32_t *)(CCU_REG_BASE + 0x051C) 76 #define CLK_APB1_CFG (volatile uint32_t *)(CCU_REG_BASE + 0x0520) 77 #define CLK_APB2_CFG (volatile uint32_t *)(CCU_REG_BASE + 0x0524) 78 79 /* Accelerator */ 80 #define CLK_CE_CFG (volatile uint32_t *)(CCU_REG_BASE + 0x0680) 81 #define CLK_CE_GATE (volatile uint32_t *)(CCU_REG_BASE + 0x068C) 82 83 /* SYS Resource */ 84 #define CLK_DMA_GATE (volatile uint32_t *)(CCU_REG_BASE + 0x070C) 85 #define CLK_HSTIMER_GATE (volatile uint32_t *)(CCU_REG_BASE + 0x073C) 86 #define CLK_AVS_CFG (volatile uint32_t *)(CCU_REG_BASE + 0x0740) 87 #define CLK_DBGSYS_GATE (volatile uint32_t *)(CCU_REG_BASE + 0x078C) 88 #define CLK_PSI_GATE (volatile uint32_t *)(CCU_REG_BASE + 0x079C) 89 #define CLK_PWM_GATE (volatile uint32_t *)(CCU_REG_BASE + 0x07AC) 90 91 /* Storage Medium */ 92 #define CLK_DRAM_CFG (volatile uint32_t *)(CCU_REG_BASE + 0x0800) 93 #define CLK_MBUS_GATE (volatile uint32_t *)(CCU_REG_BASE + 0x0804) 94 #define CLK_DRAM_GATE (volatile uint32_t *)(CCU_REG_BASE + 0x080C) 95 #define CLK_NAND0_CFG (volatile uint32_t *)(CCU_REG_BASE + 0x0810) 96 #define CLK_NAND1_CFG (volatile uint32_t *)(CCU_REG_BASE + 0x0814) 97 #define CLK_NAND_GATE (volatile uint32_t *)(CCU_REG_BASE + 0x082C) 98 #define CLK_SMHC1_CFG (volatile uint32_t *)(CCU_REG_BASE + 0x0834) 99 #define CLK_SMHC_GATE (volatile uint32_t *)(CCU_REG_BASE + 0x084C) 100 101 /* Common Interface */ 102 #define CLK_UART_GATE (volatile uint32_t *)(CCU_REG_BASE + 0x090C) 103 #define CLK_TWI_GATE (volatile uint32_t *)(CCU_REG_BASE + 0x091C) 104 #define CLK_SCR_GATE (volatile uint32_t *)(CCU_REG_BASE + 0x093C) 105 #define CLK_SPI0_CFG (volatile uint32_t *)(CCU_REG_BASE + 0x0940) 106 #define CLK_SPI1_CFG (volatile uint32_t *)(CCU_REG_BASE + 0x0944) 107 #define CLK_SPI_GATE (volatile uint32_t *)(CCU_REG_BASE + 0x096C) 108 #define CLK_GPADC_GATE (volatile uint32_t *)(CCU_REG_BASE + 0x09EC) 109 #define CLK_THS_GATE (volatile uint32_t *)(CCU_REG_BASE + 0x09FC) 110 #define CLK_I2S0_CFG (volatile uint32_t *)(CCU_REG_BASE + 0x0A10) 111 #define CLK_I2S1_CFG (volatile uint32_t *)(CCU_REG_BASE + 0x0A14) 112 #define CLK_I2S2_CFG (volatile uint32_t *)(CCU_REG_BASE + 0x0A18) 113 #define CLK_I2S_GATE (volatile uint32_t *)(CCU_REG_BASE + 0x0A1C) 114 #define CLK_SPDIF_CFG (volatile uint32_t *)(CCU_REG_BASE + 0x0A20) 115 #define CLK_SPDIF_GATE (volatile uint32_t *)(CCU_REG_BASE + 0x0A2C) 116 #define CLK_DMIC_CFG (volatile uint32_t *)(CCU_REG_BASE + 0x0A40) 117 #define CLK_DMIC_GATE (volatile uint32_t *)(CCU_REG_BASE + 0x0A4C) 118 #define CLK_CODEC_1X_CFG (volatile uint32_t *)(CCU_REG_BASE + 0x0A50) 119 #define CLK_CODEC_4X_CFG (volatile uint32_t *)(CCU_REG_BASE + 0x0A54) 120 #define CLK_CODEC_GATE (volatile uint32_t *)(CCU_REG_BASE + 0x0A5C) 121 #define CLK_USB0_CFG (volatile uint32_t *)(CCU_REG_BASE + 0x0A70) 122 #define CLK_USB1_CFG (volatile uint32_t *)(CCU_REG_BASE + 0x0A74) 123 #define CLK_USB_GATE (volatile uint32_t *)(CCU_REG_BASE + 0x0A8C) 124 #define CLK_MAD_GATE (volatile uint32_t *)(CCU_REG_BASE + 0x0ACC) 125 #define CLK_LPSD_CFG (volatile uint32_t *)(CCU_REG_BASE + 0x0AD0) 126 #define CLK_LPSD_GATE (volatile uint32_t *)(CCU_REG_BASE + 0x0ADC) 127 #define CLK_LEDC_CFG (volatile uint32_t *)(CCU_REG_BASE + 0x0BF0) 128 #define CLK_LEDC_GATE (volatile uint32_t *)(CCU_REG_BASE + 0x0BFC) 129 130 131 #endif /* __SUN8IW18P1_CLK_H__ */ 132