1 #ifndef __CE_PLATFORM_H
2 #define __CE_PLARFORM_H
3 
4 
5 #ifdef __cplusplus
6 extern "C"
7 {
8 #endif
9 
10 /*define CE version*/
11 #define CE_SUPPORT_CE_V3_1
12 
13 #define CE_NS_BASE_REG          (0x03040000)
14 #define CE_S_BASE_REG           (0x03040800)
15 
16 #ifdef CONFIG_SOC_SUN20IW1
17 #define SUNXI_IRQ_CE   69
18 #else
19 #define SUNXI_IRQ_CE   85
20 #endif
21 
22 #define SUNXI_CCM_BASE                      (0x02001000)
23 #define CCMU_CE_CLK_REG                     (SUNXI_CCM_BASE + 0x680)
24 #define CCMU_CE_BGR_REG                     (SUNXI_CCM_BASE + 0x68C)
25 #define MBUS_MAT_CLK_GATING_REG             (SUNXI_CCM_BASE + 0x804)
26 
27 #define CE_CLK_SRC_MASK                     (0x7)
28 #define CE_CLK_SRC_SEL_BIT                  (24)
29 #define CE_CLK_SRC                          (0x01)
30 #define CE_CLK_DIV_RATION_N_BIT             (8)
31 #define CE_CLK_DIV_RATION_N_MASK            (0x3)
32 #define CE_CLK_DIV_RATION_N                 (0)
33 
34 #define CE_CLK_DIV_RATION_M_BIT             (0)
35 #define CE_CLK_DIV_RATION_M_MASK            (0xF)
36 #define CE_CLK_DIV_RATION_M                 (3)
37 
38 #define CE_SCLK_ONOFF_BIT                   (31)
39 #define CE_SCLK_ON                          (1)
40 
41 #define CE_GATING_PASS                      (1)
42 #define CE_GATING_BIT                       (0)
43 #define CE_RST_BIT                          (16)
44 #define CE_DEASSERT                         (1)
45 
46 
47 #ifdef __cplusplus
48 }
49 #endif
50 
51 
52 #endif
53