1 /*
2 * Allwinner SoCs display driver.
3 *
4 * Copyright (C) 2016 Allwinner.
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11 #include "VVX07H005A10.h"
12 #include "../disp_sys_intf.h"
13
14 static void LCD_power_on(u32 sel);
15 static void LCD_power_off(u32 sel);
16 static void LCD_bl_open(u32 sel);
17 static void LCD_bl_close(u32 sel);
18
19 static void LCD_panel_init(u32 sel);
20 static void LCD_panel_exit(u32 sel);
21 static __s32 LCD_user_defined_func(__u32 sel, __u32 para1, __u32 para2, __u32 para3);
22
23 // #define LCD_DEBUG
24 #ifdef LCD_DEBUG
25 #define DEBUG(fmt, args...) printf("[DEBUG] %s, %s, %d " fmt "\n", __FILE__, __func__, __LINE__, ## args)
26 #else
27 #define DEBUG(fmt, args...)
28 #endif
29
30 #define dsi_dcs_wr_0para sunxi_lcd_dsi_dcs_write_0para
31 #define dsi_dcs_wr_1para sunxi_lcd_dsi_dcs_write_1para
32 #define dsi_dcs_wr_2para sunxi_lcd_dsi_dcs_write_2para
33 #define dsi_dcs_wr_3para sunxi_lcd_dsi_dcs_write_3para
34 #define dsi_dcs_wr_4para sunxi_lcd_dsi_dcs_write_4para
35 #define dsi_dcs_wr_5para sunxi_lcd_dsi_dcs_write_5para
36 #define dsi_dcs_wr_6para sunxi_lcd_dsi_dcs_write_6para
37 #define dsi_dcs_wr_longpara sunxi_lcd_dsi_dcs_write
38 #define delayms sunxi_lcd_delay_ms
39
tft7201280_init(__u32 sel,__u32 mode,__u32 lane,__u32 format)40 static void tft7201280_init(__u32 sel, __u32 mode, __u32 lane, __u32 format)
41 {
42 //-----------------------Initial Code--------------------------------------//
43 //Page0
44 dsi_dcs_wr_1para(sel,0xE0,0x00);
45
46 //--- PASSWORD ----//
47 dsi_dcs_wr_1para(sel,0xE1,0x93);
48 dsi_dcs_wr_1para(sel,0xE2,0x65);
49 dsi_dcs_wr_1para(sel,0xE3,0xF8);
50 dsi_dcs_wr_1para(sel,0x80,0x03);
51
52
53
54 //--- Page1 ----//
55 dsi_dcs_wr_1para(sel,0xE0,0x01);
56
57 //Set VCOM
58 dsi_dcs_wr_1para(sel,0x01,0x67);
59
60 //Set Gamma Power, VGMP,VGMN,VGSP,VGSN
61 dsi_dcs_wr_1para(sel,0x17,0x00);
62 dsi_dcs_wr_1para(sel,0x18,0xBF);//4.5V, D7=4.8V
63 dsi_dcs_wr_1para(sel,0x19,0x01);//0.0V
64 dsi_dcs_wr_1para(sel,0x1A,0x00);
65 dsi_dcs_wr_1para(sel,0x1B,0xBF);
66 dsi_dcs_wr_1para(sel,0x1C,0x01);
67 dsi_dcs_wr_1para(sel,0x0C,0x74);
68
69 //Set Gate Power
70 dsi_dcs_wr_1para(sel,0x1F,0x70); //VGH_REG=16.2V
71 dsi_dcs_wr_1para(sel,0x20,0x2D); //VGL_REG=-12V
72 dsi_dcs_wr_1para(sel,0x21,0x2D); //VGL_REG2=-12V
73 dsi_dcs_wr_1para(sel,0x22,0x7E);
74 dsi_dcs_wr_1para(sel,0x0C,0x74);
75
76
77 dsi_dcs_wr_1para(sel,0x35,0x28); //SAP
78
79 dsi_dcs_wr_1para(sel,0x37,0x19); //SS=1,BGR=1
80
81 //SET RGBCYC
82 dsi_dcs_wr_1para(sel,0x38,0x05); //JDT=101 zigzag inversion
83 dsi_dcs_wr_1para(sel,0x39,0x00);
84 dsi_dcs_wr_1para(sel,0x3A,0x01);
85 dsi_dcs_wr_1para(sel,0x3C,0x7C); //SET EQ3 for TE_H
86 dsi_dcs_wr_1para(sel,0x3D,0xFF); //SET CHGEN_ON, modify 20140806
87 dsi_dcs_wr_1para(sel,0x3E,0xFF); //SET CHGEN_OFF, modify 20140806
88 dsi_dcs_wr_1para(sel,0x3F,0x7F); //SET CHGEN_OFF2, modify 20140806
89
90
91 //Set TCON
92 dsi_dcs_wr_1para(sel,0x40,0x06); //RSO=
93 dsi_dcs_wr_1para(sel,0x41,0xA0); //LN=640->1280 line
94 dsi_dcs_wr_1para(sel,0x43,0x1E); //VFP=30
95 dsi_dcs_wr_1para(sel,0x44,0x0B); //VBP=12
96 dsi_dcs_wr_1para(sel,0x45,0x28); //HBP=40
97
98 //--- power voltage ----//
99 dsi_dcs_wr_1para(sel,0x55,0x01);
100 dsi_dcs_wr_1para(sel,0x57,0xA9);
101 //dsi_dcs_wr_1para(sel,0x58,0x0A);
102 dsi_dcs_wr_1para(sel,0x59,0x0A); //VCL = -2.5V
103 dsi_dcs_wr_1para(sel,0x5A,0x2E); //VGH = 16.2V
104 dsi_dcs_wr_1para(sel,0x5B,0x1A); //VGL = -12V
105 dsi_dcs_wr_1para(sel,0x5C,0x15); //pump clk
106
107
108 //--- Gamma ----//
109 dsi_dcs_wr_1para(sel,0x5D,0x7F);
110 dsi_dcs_wr_1para(sel,0x5E,0x64);
111 dsi_dcs_wr_1para(sel,0x5F,0x53);
112 dsi_dcs_wr_1para(sel,0x60,0x47);
113 dsi_dcs_wr_1para(sel,0x61,0x43);
114 dsi_dcs_wr_1para(sel,0x62,0x33);
115 dsi_dcs_wr_1para(sel,0x63,0x37);
116 dsi_dcs_wr_1para(sel,0x64,0x21);
117 dsi_dcs_wr_1para(sel,0x65,0x39);
118 dsi_dcs_wr_1para(sel,0x66,0x37);
119 dsi_dcs_wr_1para(sel,0x67,0x34);
120 dsi_dcs_wr_1para(sel,0x68,0x50);
121 dsi_dcs_wr_1para(sel,0x69,0x3D);
122 dsi_dcs_wr_1para(sel,0x6A,0x44);
123 dsi_dcs_wr_1para(sel,0x6B,0x36);
124 dsi_dcs_wr_1para(sel,0x6C,0x34);
125 dsi_dcs_wr_1para(sel,0x6D,0x25);
126 dsi_dcs_wr_1para(sel,0x6E,0x15);
127 dsi_dcs_wr_1para(sel,0x6F,0x02);
128 dsi_dcs_wr_1para(sel,0x70,0x7F);
129 dsi_dcs_wr_1para(sel,0x71,0x64);
130 dsi_dcs_wr_1para(sel,0x72,0x53);
131 dsi_dcs_wr_1para(sel,0x73,0x47);
132 dsi_dcs_wr_1para(sel,0x74,0x43);
133 dsi_dcs_wr_1para(sel,0x75,0x33);
134 dsi_dcs_wr_1para(sel,0x76,0x37);
135 dsi_dcs_wr_1para(sel,0x77,0x21);
136 dsi_dcs_wr_1para(sel,0x78,0x39);
137 dsi_dcs_wr_1para(sel,0x79,0x37);
138 dsi_dcs_wr_1para(sel,0x7A,0x34);
139 dsi_dcs_wr_1para(sel,0x7B,0x50);
140 dsi_dcs_wr_1para(sel,0x7C,0x3D);
141 dsi_dcs_wr_1para(sel,0x7D,0x44);
142 dsi_dcs_wr_1para(sel,0x7E,0x36);
143 dsi_dcs_wr_1para(sel,0x7F,0x34);
144 dsi_dcs_wr_1para(sel,0x80,0x25);
145 dsi_dcs_wr_1para(sel,0x81,0x15);
146 dsi_dcs_wr_1para(sel,0x82,0x02);
147
148
149 //Page2, for GIP
150 dsi_dcs_wr_1para(sel,0xE0,0x02);
151
152 //GIP_L Pin mapping
153 dsi_dcs_wr_1para(sel,0x00,0x52);//RESET_EVEN
154 dsi_dcs_wr_1para(sel,0x01,0x55);//VSSG_EVEN
155 dsi_dcs_wr_1para(sel,0x02,0x55);//VSSG_EVEN
156 dsi_dcs_wr_1para(sel,0x03,0x50);//STV2_ODD
157 dsi_dcs_wr_1para(sel,0x04,0x77);//VDD2_ODD
158 dsi_dcs_wr_1para(sel,0x05,0x57);//VDD1_ODD
159 dsi_dcs_wr_1para(sel,0x06,0x55);//x
160 dsi_dcs_wr_1para(sel,0x07,0x4E);//CK11
161 dsi_dcs_wr_1para(sel,0x08,0x4C);//CK9
162 dsi_dcs_wr_1para(sel,0x09,0x5F);//x
163 dsi_dcs_wr_1para(sel,0x0A,0x4A);//CK7
164 dsi_dcs_wr_1para(sel,0x0B,0x48);//CK5
165 dsi_dcs_wr_1para(sel,0x0C,0x55);//x
166 dsi_dcs_wr_1para(sel,0x0D,0x46);//CK3
167 dsi_dcs_wr_1para(sel,0x0E,0x44);//CK1
168 dsi_dcs_wr_1para(sel,0x0F,0x40);//STV1_ODD
169 dsi_dcs_wr_1para(sel,0x10,0x55);//x
170 dsi_dcs_wr_1para(sel,0x11,0x55);//x
171 dsi_dcs_wr_1para(sel,0x12,0x55);//x
172 dsi_dcs_wr_1para(sel,0x13,0x55);//x
173 dsi_dcs_wr_1para(sel,0x14,0x55);//x
174 dsi_dcs_wr_1para(sel,0x15,0x55);//x
175
176 //GIP_R Pin mapping
177 dsi_dcs_wr_1para(sel,0x16,0x53);//RESET__EVEN
178 dsi_dcs_wr_1para(sel,0x17,0x55);//VSSG_EVEN
179 dsi_dcs_wr_1para(sel,0x18,0x55);//VSSG_EVEN
180 dsi_dcs_wr_1para(sel,0x19,0x51);//STV2_EVEN
181 dsi_dcs_wr_1para(sel,0x1A,0x77);//VDD2_EVEN
182 dsi_dcs_wr_1para(sel,0x1B,0x57);//VDD1_EVEN
183 dsi_dcs_wr_1para(sel,0x1C,0x55);//x
184 dsi_dcs_wr_1para(sel,0x1D,0x4F);//CK12
185 dsi_dcs_wr_1para(sel,0x1E,0x4D);//CK10
186 dsi_dcs_wr_1para(sel,0x1F,0x5F);//x
187 dsi_dcs_wr_1para(sel,0x20,0x4B);//CK8
188 dsi_dcs_wr_1para(sel,0x21,0x49);//CK6
189 dsi_dcs_wr_1para(sel,0x22,0x55);//x
190 dsi_dcs_wr_1para(sel,0x23,0x47);//CK4
191 dsi_dcs_wr_1para(sel,0x24,0x45);//CK2
192 dsi_dcs_wr_1para(sel,0x25,0x41);//STV1_EVEN
193 dsi_dcs_wr_1para(sel,0x26,0x55);//x
194 dsi_dcs_wr_1para(sel,0x27,0x55);//x
195 dsi_dcs_wr_1para(sel,0x28,0x55);//x
196 dsi_dcs_wr_1para(sel,0x29,0x55);//x
197 dsi_dcs_wr_1para(sel,0x2A,0x55);//x
198 dsi_dcs_wr_1para(sel,0x2B,0x55);//x
199
200 //GIP_L_GS Pin mapping
201 dsi_dcs_wr_1para(sel,0x2C,0x13);//RESET_EVEN
202 dsi_dcs_wr_1para(sel,0x2D,0x15);//VSSG_EVEN
203 dsi_dcs_wr_1para(sel,0x2E,0x15);//VSSG_EVEN
204 dsi_dcs_wr_1para(sel,0x2F,0x01);//STV2_ODD
205 dsi_dcs_wr_1para(sel,0x30,0x37);//VDD2_ODD
206 dsi_dcs_wr_1para(sel,0x31,0x17);//VDD1_ODD
207 dsi_dcs_wr_1para(sel,0x32,0x15);//x
208 dsi_dcs_wr_1para(sel,0x33,0x0D);//CK11
209 dsi_dcs_wr_1para(sel,0x34,0x0F);//CK9
210 dsi_dcs_wr_1para(sel,0x35,0x15);//x
211 dsi_dcs_wr_1para(sel,0x36,0x05);//CK7
212 dsi_dcs_wr_1para(sel,0x37,0x07);//CK5
213 dsi_dcs_wr_1para(sel,0x38,0x15);//x
214 dsi_dcs_wr_1para(sel,0x39,0x09);//CK3
215 dsi_dcs_wr_1para(sel,0x3A,0x0B);//CK1
216 dsi_dcs_wr_1para(sel,0x3B,0x11);//STV1_ODD
217 dsi_dcs_wr_1para(sel,0x3C,0x15);//x
218 dsi_dcs_wr_1para(sel,0x3D,0x15);//x
219 dsi_dcs_wr_1para(sel,0x3E,0x15);//x
220 dsi_dcs_wr_1para(sel,0x3F,0x15);//x
221 dsi_dcs_wr_1para(sel,0x40,0x15);//x
222 dsi_dcs_wr_1para(sel,0x41,0x15);//x
223
224 //GIP_R_GS Pin mapping
225 dsi_dcs_wr_1para(sel,0x42,0x12);//RESET__EVEN
226 dsi_dcs_wr_1para(sel,0x43,0x15);//VSSG_EVEN
227 dsi_dcs_wr_1para(sel,0x44,0x15);//VSSG_EVEN
228 dsi_dcs_wr_1para(sel,0x45,0x00);//STV2_EVEN
229 dsi_dcs_wr_1para(sel,0x46,0x37);//VDD2_EVEN
230 dsi_dcs_wr_1para(sel,0x47,0x17);//VDD1_EVEN
231 dsi_dcs_wr_1para(sel,0x48,0x15);//x
232 dsi_dcs_wr_1para(sel,0x49,0x0C);//CK12
233 dsi_dcs_wr_1para(sel,0x4A,0x0E);//CK10
234 dsi_dcs_wr_1para(sel,0x4B,0x15);//x
235 dsi_dcs_wr_1para(sel,0x4C,0x04);//CK8
236 dsi_dcs_wr_1para(sel,0x4D,0x06);//CK6
237 dsi_dcs_wr_1para(sel,0x4E,0x15);//x
238 dsi_dcs_wr_1para(sel,0x4F,0x08);//CK4
239 dsi_dcs_wr_1para(sel,0x50,0x0A);//CK2
240 dsi_dcs_wr_1para(sel,0x51,0x10);//STV1_EVEN
241 dsi_dcs_wr_1para(sel,0x52,0x15);//x
242 dsi_dcs_wr_1para(sel,0x53,0x15);//x
243 dsi_dcs_wr_1para(sel,0x54,0x15);//x
244 dsi_dcs_wr_1para(sel,0x55,0x15);//x
245 dsi_dcs_wr_1para(sel,0x56,0x15);//x
246 dsi_dcs_wr_1para(sel,0x57,0x15);//x
247
248 //GIP Timing
249 dsi_dcs_wr_1para(sel,0x58,0x40);
250 dsi_dcs_wr_1para(sel,0x5B,0x10);
251 dsi_dcs_wr_1para(sel,0x5C,0x06);//STV_S0
252 dsi_dcs_wr_1para(sel,0x5D,0x40);
253 dsi_dcs_wr_1para(sel,0x5E,0x00);
254 dsi_dcs_wr_1para(sel,0x5F,0x00);
255 dsi_dcs_wr_1para(sel,0x60,0x40);//ETV_W
256 dsi_dcs_wr_1para(sel,0x61,0x03);
257 dsi_dcs_wr_1para(sel,0x62,0x04);
258 dsi_dcs_wr_1para(sel,0x63,0x6C);//CKV_ON
259 dsi_dcs_wr_1para(sel,0x64,0x6C);//CKV_OFF
260 dsi_dcs_wr_1para(sel,0x65,0x75);
261 dsi_dcs_wr_1para(sel,0x66,0x08);//ETV_S0
262 dsi_dcs_wr_1para(sel,0x67,0xB4); //ckv_num/ckv_w
263 dsi_dcs_wr_1para(sel,0x68,0x08); //CKV_S0
264 dsi_dcs_wr_1para(sel,0x69,0x6C);//CKV_ON
265 dsi_dcs_wr_1para(sel,0x6A,0x6C);//CKV_OFF
266 dsi_dcs_wr_1para(sel,0x6B,0x0C); //dummy
267 dsi_dcs_wr_1para(sel,0x6D,0x00);//GGND1
268 dsi_dcs_wr_1para(sel,0x6E,0x00);//GGND2
269 dsi_dcs_wr_1para(sel,0x6F,0x88);
270
271 dsi_dcs_wr_1para(sel,0x75,0xBB);//FLM_EN
272 dsi_dcs_wr_1para(sel,0x76,0x00);
273 dsi_dcs_wr_1para(sel,0x77,0x05);
274 dsi_dcs_wr_1para(sel,0x78,0x2A);//FLM_OFF
275
276 //Page4
277 dsi_dcs_wr_1para(sel,0xE0,0x04);
278 dsi_dcs_wr_1para(sel,0x09,0x11);
279 dsi_dcs_wr_1para(sel,0x0E,0x48); //Source EQ option
280 dsi_dcs_wr_1para(sel,0x2B,0x2B);
281 dsi_dcs_wr_1para(sel,0x2D,0x03);//defult 0x01
282 dsi_dcs_wr_1para(sel,0x2E,0x44);
283
284 //Page5
285 dsi_dcs_wr_1para(sel,0xE0,0x05);
286 dsi_dcs_wr_1para(sel,0x12,0x72);//VCI GAS detect voltage
287
288 //Page0
289 dsi_dcs_wr_1para(sel,0xE0,0x00);
290 dsi_dcs_wr_1para(sel,0xE6,0x02);//WD_Timer
291 dsi_dcs_wr_1para(sel,0xE7,0x0C);//WD_Timer
292
293 //SLP OUT
294 dsi_dcs_wr_0para(sel,0x01);
295 dsi_dcs_wr_0para(sel,0x11); // SLPOUT
296 delayms(120);
297
298
299 //DISP ON
300 dsi_dcs_wr_0para(sel,0x01);
301 dsi_dcs_wr_0para(sel,0x29); // DSPON
302 delayms(5);
303
304 }
305
tft7201280_init_s(__u32 sel,__u32 mode,__u32 lane,__u32 format)306 static void tft7201280_init_s(__u32 sel,__u32 mode,__u32 lane,__u32 format)
307 {
308 __u8 tmp1[15]={0x6c,0x12,0x12,0x34,0x04,0x11,0xF1,0x80,0xE5,0x95,0x23,0x80,0xc0,0xd2,0x58};
309 __u8 tmp2[12]={0x00,0xFF,0x01,0x5A,0x01,0x5A,0x01,0x5A,0x01,0x70,0x01,0x70};
310 __u8 tmp3[37]={0x00,0x06,0x00,0x01,0x07,0x00,0x00,0x32,0x10,0x08,0x00,0x08,0x52,0x15,0x0E,0x05,0x0E,0x32,0x10,0x00,0x00,0x00,0x37,0x33,0x0C,0x0C,0x37,0x0C,0x0C,0x47,0x08,0x00,0x00,0x00,0x0A,0x00,0x01};
311 __u8 tmp4[44]={0x1B,0x1B,0x1A,0x1A,0x06,0x07,0x02,0x03,0x04,0x05,0x00,0x01,0x20,0x21,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x19,0x18,0x24,0x19,0x18,0x25};
312 __u8 tmp5[44]={0x1B,0x1B,0x1A,0x1A,0x01,0x00,0x05,0x04,0x03,0x02,0x07,0x06,0x25,0x24,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x19,0x18,0x18,0x19,0x21,0x18,0x18,0x20};
313 __u8 tmp6[42]={0x00,0x06,0x17,0x0F,0x10,0x3f,0x2C,0x37,0x0A,0x0F,0x11,0x19,0x10,0x15,0x17,0x15,0x15,0x07,0x13,0x15,0x19,0x00,0x06,0x17,0x0F,0x10,0x3F,0x2C,0x37,0x0A,0x0F,0x11,0x19,0x10,0x15,0x17,0x15,0x15,0x07,0x13,0x15,0x19};
314 __u8 tmp7[42]={0x00,0x16,0x1E,0x0E,0x0C,0x39,0x2E,0x3B,0x09,0x0D,0x0F,0x19,0x11,0x14,0x17,0x15,0x15,0x08,0x14,0x15,0x16,0x00,0x12,0x1B,0x0E,0x0C,0x39,0x26,0x2E,0x08,0x0E,0x0F,0x18,0x10,0x14,0x17,0x15,0x16,0x08,0x14,0x15,0x16};
315
316 //-----------------------Initial Code--------------------------------------//
317 //password
318 dsi_dcs_wr_3para(sel,0xB9,0xFF,0x83,0x94);
319 delayms(1);
320
321 //setting mipi 4-lane
322 dsi_dcs_wr_2para(sel,0xBA,0x33,0x83);
323 delayms(1);
324
325 dsi_dcs_wr_longpara(sel,0xB1,tmp1,15);
326 delayms(1);
327
328 //set display
329 dsi_dcs_wr_6para(sel,0xB2,0x00,0x64,0x10,0x07,0x32,0x1C);
330 delayms(1);
331
332 //setting CYC
333 dsi_dcs_wr_longpara(sel,0xB4,tmp2,12);
334 delayms(1);
335
336 //set d3
337 dsi_dcs_wr_longpara(sel,0xD3,tmp3,37);
338 delayms(1);
339
340 //setting SCAN RGB
341 dsi_dcs_wr_1para(sel,0xCC,0x0B);
342 delayms(1);
343
344 //setting GIP
345 dsi_dcs_wr_longpara(sel,0xD5,tmp4,44);
346 delayms(1);
347
348 //set D6
349 dsi_dcs_wr_longpara(sel,0xD6,tmp5,44);
350 delayms(1);
351
352 //set VOCN option
353 dsi_dcs_wr_4para(sel,0xC7,0x00,0xC0,0x00,0xC0);
354 delayms(1);
355
356 dsi_dcs_wr_1para(sel,0xC6,0x1D);
357
358 //setting Gamma
359 dsi_dcs_wr_longpara(sel,0xE0,tmp6,42);
360
361 //dsi_dcs_wr_longpara(sel,0xE0,tmp7,42);
362 delayms(10);
363
364 //setting sleep out
365 dsi_dcs_wr_0para(sel,0x11);
366 delayms(20);
367
368 dsi_dcs_wr_2para(sel,0xB6,0x32,0x32);
369
370 //setting Display
371 dsi_dcs_wr_0para(sel,0x29); // DSPON
372 delayms(10);
373
374 }
375
376
LCD_cfg_panel_info(struct panel_extend_para * info)377 static void LCD_cfg_panel_info(struct panel_extend_para *info)
378 {
379 u32 i = 0, j = 0;
380 u32 items;
381 u8 lcd_gamma_tbl[][2] = {
382 /* {input value, corrected value} */
383 {0, 0},
384 {15, 15},
385 {30, 30},
386 {45, 45},
387 {60, 60},
388 {75, 75},
389 {90, 90},
390 {105, 105},
391 {120, 120},
392 {135, 135},
393 {150, 150},
394 {165, 165},
395 {180, 180},
396 {195, 195},
397 {210, 210},
398 {225, 225},
399 {240, 240},
400 {255, 255},
401 };
402
403 u32 lcd_cmap_tbl[2][3][4] = {
404 {
405 {LCD_CMAP_G0, LCD_CMAP_B1, LCD_CMAP_G2, LCD_CMAP_B3},
406 {LCD_CMAP_B0, LCD_CMAP_R1, LCD_CMAP_B2, LCD_CMAP_R3},
407 {LCD_CMAP_R0, LCD_CMAP_G1, LCD_CMAP_R2, LCD_CMAP_G3},
408 },
409 {
410 {LCD_CMAP_B3, LCD_CMAP_G2, LCD_CMAP_B1, LCD_CMAP_G0},
411 {LCD_CMAP_R3, LCD_CMAP_B2, LCD_CMAP_R1, LCD_CMAP_B0},
412 {LCD_CMAP_G3, LCD_CMAP_R2, LCD_CMAP_G1, LCD_CMAP_R0},
413 },
414 };
415
416 items = sizeof(lcd_gamma_tbl) / 2;
417 for (i = 0; i < items - 1; i++) {
418 u32 num = lcd_gamma_tbl[i + 1][0] - lcd_gamma_tbl[i][0];
419
420 for (j = 0; j < num; j++) {
421 u32 value = 0;
422
423 value =
424 lcd_gamma_tbl[i][1] +
425 ((lcd_gamma_tbl[i + 1][1] -
426 lcd_gamma_tbl[i][1]) * j) / num;
427 info->lcd_gamma_tbl[lcd_gamma_tbl[i][0] + j] =
428 (value << 16) + (value << 8) + value;
429 }
430 }
431 info->lcd_gamma_tbl[255] =
432 (lcd_gamma_tbl[items - 1][1] << 16) +
433 (lcd_gamma_tbl[items - 1][1] << 8) + lcd_gamma_tbl[items - 1][1];
434
435 memcpy(info->lcd_cmap_tbl, lcd_cmap_tbl, sizeof(lcd_cmap_tbl));
436
437 }
438
LCD_open_flow(u32 sel)439 static s32 LCD_open_flow(u32 sel)
440 {
441 LCD_OPEN_FUNC(sel, LCD_power_on, 15); //open lcd power, and delay 10ms
442 LCD_OPEN_FUNC(sel, LCD_panel_init, 30); //open lcd power, than delay 50ms
443 LCD_OPEN_FUNC(sel, sunxi_lcd_tcon_enable, 30); //open lcd controller, and delay 50ms
444 LCD_OPEN_FUNC(sel, LCD_bl_open, 0); //open lcd backlight, and delay 0ms
445
446 return 0;
447 }
448
LCD_close_flow(u32 sel)449 static s32 LCD_close_flow(u32 sel)
450 {
451 LCD_CLOSE_FUNC(sel, LCD_bl_close, 0); //close lcd backlight, and delay 0ms
452 LCD_CLOSE_FUNC(sel, sunxi_lcd_tcon_disable, 0); //close lcd controller, and delay 0ms
453 LCD_CLOSE_FUNC(sel, LCD_panel_exit, 20); //open lcd power, than delay 20ms
454 LCD_CLOSE_FUNC(sel, LCD_power_off, 50); //close lcd power, and delay 50ms
455 return 0;
456 }
457
LCD_power_on(u32 sel)458 static void LCD_power_on(u32 sel)
459 {
460 sunxi_lcd_power_enable(sel, 0);//config lcd_power pin to open lcd power0
461 sunxi_lcd_pin_cfg(sel, 1);
462 }
463
LCD_power_off(u32 sel)464 static void LCD_power_off(u32 sel)
465 {
466 sunxi_lcd_pin_cfg(sel, 0);
467 sunxi_lcd_power_disable(sel, 0);//config lcd_power pin to close lcd power0
468 sunxi_lcd_dsi_clk_disable(sel);
469 }
470
LCD_bl_open(u32 sel)471 static void LCD_bl_open(u32 sel)
472 {
473 sunxi_lcd_pwm_enable(sel);
474 sunxi_lcd_backlight_enable(sel);//config lcd_bl_en pin to open lcd backlight
475 }
476
LCD_bl_close(u32 sel)477 static void LCD_bl_close(u32 sel)
478 {
479 sunxi_lcd_backlight_disable(sel);//config lcd_bl_en pin to close lcd backlight
480 sunxi_lcd_pwm_disable(sel);
481 }
482
LCD_panel_init(u32 sel)483 static void LCD_panel_init(u32 sel)
484 {
485 #if 0
486 // 有的屏需要初始化，在这里添加。比如hv屏可能需要spi或则iic初始化，
487 // dsi屏，用LP_TX模式初始化
488 struct disp_panel_para *panel_info = malloc(sizeof(struct disp_panel_para));
489
490 bsp_disp_get_panel_info(sel, panel_info);
491 sunxi_lcd_dsi_clk_enable(sel);
492 tft7201280_init_s(sel, panel_info->lcd_dsi_if, panel_info->lcd_dsi_lane, panel_info->lcd_dsi_format);
493
494 disp_sys_free(panel_info);
495 #else
496 struct disp_panel_para *panel_info = malloc(sizeof(struct disp_panel_para));
497
498 bsp_disp_get_panel_info(sel, panel_info);
499 sunxi_lcd_dsi_clk_enable(sel);
500 //tft7201280_init(sel, panel_info->lcd_dsi_if, panel_info->lcd_dsi_lane, panel_info->lcd_dsi_format);
501
502 disp_sys_free(panel_info);
503 #endif
504 return;
505 }
506
LCD_panel_exit(u32 sel)507 static void LCD_panel_exit(u32 sel)
508 {
509 sunxi_lcd_dsi_dcs_write_0para(sel, DSI_DCS_SET_DISPLAY_OFF);
510 sunxi_lcd_delay_ms(50);
511 sunxi_lcd_dsi_dcs_write_0para(sel, DSI_DCS_ENTER_SLEEP_MODE);
512 sunxi_lcd_delay_ms(20);
513 }
514
515 /* sel: 0:lcd0; 1:lcd1 */
LCD_user_defined_func(u32 sel,u32 para1,u32 para2,u32 para3)516 static s32 LCD_user_defined_func(u32 sel, u32 para1, u32 para2, u32 para3)
517 {
518 return 0;
519 }
520
521 struct __lcd_panel VVX07H005A10_panel = {
522 /* panel driver name, must mach the lcd_drv_name in sys_config.fex */
523 .name = "VVX07H005A10",
524 .func = {
525 .cfg_panel_info = LCD_cfg_panel_info,
526 .cfg_open_flow = LCD_open_flow,
527 .cfg_close_flow = LCD_close_flow,
528 .lcd_user_defined_func = LCD_user_defined_func,
529 }
530 ,
531 };
532