1 /* 2 * Copyright (c) 2019-2025 Allwinner Technology Co., Ltd. ALL rights reserved. 3 * 4 * Allwinner is a trademark of Allwinner Technology Co.,Ltd., registered in 5 * the the People's Republic of China and other countries. 6 * All Allwinner Technology Co.,Ltd. trademarks are used with permission. 7 * 8 * DISCLAIMER 9 * THIRD PARTY LICENCES MAY BE REQUIRED TO IMPLEMENT THE SOLUTION/PRODUCT. 10 * IF YOU NEED TO INTEGRATE THIRD PARTY¡¯S TECHNOLOGY (SONY, DTS, DOLBY, AVS OR MPEGLA, ETC.) 11 * IN ALLWINNERS¡¯SDK OR PRODUCTS, YOU SHALL BE SOLELY RESPONSIBLE TO OBTAIN 12 * ALL APPROPRIATELY REQUIRED THIRD PARTY LICENCES. 13 * ALLWINNER SHALL HAVE NO WARRANTY, INDEMNITY OR OTHER OBLIGATIONS WITH RESPECT TO MATTERS 14 * COVERED UNDER ANY REQUIRED THIRD PARTY LICENSE. 15 * YOU ARE SOLELY RESPONSIBLE FOR YOUR USAGE OF THIRD PARTY¡¯S TECHNOLOGY. 16 * 17 * 18 * THIS SOFTWARE IS PROVIDED BY ALLWINNER"AS IS" AND TO THE MAXIMUM EXTENT 19 * PERMITTED BY LAW, ALLWINNER EXPRESSLY DISCLAIMS ALL WARRANTIES OF ANY KIND, 20 * WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING WITHOUT LIMITATION REGARDING 21 * THE TITLE, NON-INFRINGEMENT, ACCURACY, CONDITION, COMPLETENESS, PERFORMANCE 22 * OR MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. 23 * IN NO EVENT SHALL ALLWINNER BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 26 * LOSS OF USE, DATA, OR PROFITS, OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 28 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED 30 * OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 #ifndef __DMA_SUN8IW18_H__ 33 #define __DMA_SUN8IW18_H__ 34 35 #define SUNXI_DMAC_PBASE 0x03002000 36 37 #define DMA_IRQ_NUM 66 38 39 #define NR_MAX_CHAN 10 /* total of channels */ 40 #define START_CHAN_OFFSET 0 41 42 #define SUNXI_CLK_DMA HAL_CLK_PERIPH_DMA 43 #define SUNXI_CLK_MBUS_DMA (0) 44 #define SUNXI_RST_DMA (0) 45 46 47 /* 48 * The source DRQ type and port corresponding relation 49 */ 50 #define DRQSRC_SRAM 0 51 #define DRQSRC_SDRAM 0 52 #define DRQSRC_SPDIFRX 2 53 #define DRQSRC_DAUDIO_0_RX 3 54 #define DRQSRC_DAUDIO_1_RX 4 55 #define DRQSRC_DAUDIO_2_RX 5 56 #define DRQSRC_AUDIO_CODEC 6 57 #define DRQSRC_DMIC 7 58 /* #define DRQSRC_RESEVER 8 */ 59 /* #define DRQSRC_RESEVER 9 */ 60 #define DRQSRC_NAND0 10 61 /* #define DRQSRC_RESEVER 11 */ 62 #define DRQSRC_GPADC 12 63 /* #define DRQSRC_RESEVER 13 */ 64 #define DRQSRC_UART0_RX 14 65 #define DRQSRC_UART1_RX 15 66 #define DRQSRC_UART2_RX 16 67 #define DRQSRC_UART3_RX 17 68 #define DRQSRC_UART4_RX 18 69 /* #define DRQSRC_RESEVER 19 */ 70 /* #define DRQSRC_RESEVER 20 */ 71 /* #define DRQSRC_RESEVER 21 */ 72 #define DRQSRC_SPI0_RX 22 73 #define DRQSRC_SPI1_RX 23 74 /* #define DRQSRC_SPI2_RX 24 */ 75 /* #define DRQSRC_SPI3_RX 25 */ 76 /* #define DRQSRC_RESEVER 26 */ 77 /* #define DRQSRC_RESEVER 27 */ 78 /* #define DRQSRC_RESEVER 28 */ 79 /* #define DRQSRC_RESEVER 29 */ 80 #define DRQSRC_MAD_RX 44 81 #define DRQSRC_TWI0_RX 45 82 #define DRQSRC_TWI1_RX 46 83 84 /* 85 * The destination DRQ type and port corresponding relation 86 */ 87 #define DRQDST_SRAM 0 88 #define DRQDST_SDRAM 0 89 #define DRQDST_SPDIFTX 2 90 #define DRQDST_DAUDIO_0_TX 3 91 #define DRQDST_DAUDIO_1_TX 4 92 #define DRQDST_DAUDIO_2_TX 5 93 #define DRQDST_AUDIO_CODEC 6 94 /* #define DRQDST_RESEVER 7 */ 95 /* #define DRQDST_RESEVER 8 */ 96 /* #define DRQDST_RESEVER 9 */ 97 #define DRQDST_NAND0 10 98 /* #define DRQDST_RESEVER 11 */ 99 /* #define DRQDST_RESEVER 12 */ 100 /* #define DRQDST_IR_TX 13 */ 101 #define DRQDST_UART0_TX 14 102 #define DRQDST_UART1_TX 15 103 #define DRQDST_UART2_TX 16 104 #define DRQDST_UART3_TX 17 105 #define DRQDST_UART4_TX 18 106 /* #define DRQDST_RESEVER 19 */ 107 /* #define DRQDST_RESEVER 20 */ 108 /* #define DRQDST_RESEVER 21 */ 109 #define DRQDST_SPI0_TX 22 110 #define DRQDST_SPI1_TX 23 111 /* #define DRQDST_SPI2_TX 24 */ 112 /* #define DRQDST_SPI3_TX 25 */ 113 /* #define DRQDST_RESEVER 26 */ 114 /* #define DRQDST_RESEVER 27 */ 115 /* #define DRQDST_RESEVER 28 */ 116 /* #define DRQDST_RESEVER 29 */ 117 #define DRQDST_LEDC 43 118 #define DRQDST_MAD_TX 44 119 #define DRQDST_TWI0_TX 45 120 #define DRQDST_TWI1_TX 46 121 122 #endif /*__DMA_SUN8IW18_H__ */ 123