1 /* 2 * Copyright (c) 2019-2025 Allwinner Technology Co., Ltd. ALL rights reserved. 3 * 4 * Allwinner is a trademark of Allwinner Technology Co.,Ltd., registered in 5 * the the People's Republic of China and other countries. 6 * All Allwinner Technology Co.,Ltd. trademarks are used with permission. 7 * 8 * DISCLAIMER 9 * THIRD PARTY LICENCES MAY BE REQUIRED TO IMPLEMENT THE SOLUTION/PRODUCT. 10 * IF YOU NEED TO INTEGRATE THIRD PARTY'S TECHNOLOGY (SONY, DTS, DOLBY, AVS OR MPEGLA, ETC.) 11 * IN ALLWINNERS'SDK OR PRODUCTS, YOU SHALL BE SOLELY RESPONSIBLE TO OBTAIN 12 * ALL APPROPRIATELY REQUIRED THIRD PARTY LICENCES. 13 * ALLWINNER SHALL HAVE NO WARRANTY, INDEMNITY OR OTHER OBLIGATIONS WITH RESPECT TO MATTERS 14 * COVERED UNDER ANY REQUIRED THIRD PARTY LICENSE. 15 * YOU ARE SOLELY RESPONSIBLE FOR YOUR USAGE OF THIRD PARTY'S TECHNOLOGY. 16 * 17 * 18 * THIS SOFTWARE IS PROVIDED BY ALLWINNER"AS IS" AND TO THE MAXIMUM EXTENT 19 * PERMITTED BY LAW, ALLWINNER EXPRESSLY DISCLAIMS ALL WARRANTIES OF ANY KIND, 20 * WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING WITHOUT LIMITATION REGARDING 21 * THE TITLE, NON-INFRINGEMENT, ACCURACY, CONDITION, COMPLETENESS, PERFORMANCE 22 * OR MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. 23 * IN NO EVENT SHALL ALLWINNER BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 26 * LOSS OF USE, DATA, OR PROFITS, OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 28 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED 30 * OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #ifndef __DMA_SUN8IW20_H__ 34 #define __DMA_SUN8IW20_H__ 35 36 #define SUNXI_DMAC_PBASE (0x03002000ul) 37 38 #if defined(CONFIG_CORE_DSP0) 39 #define DMA_IRQ_NUM (8) /* DMA 8~15 channel irq non-secure */ 40 #define NR_MAX_CHAN 8 /* total of channels */ 41 #define START_CHAN_OFFSET 8 42 #else 43 /* CPUX */ 44 #define DMA_IRQ_NUM (66) /* DMA 0~7 channel irq non-secure */ 45 #define NR_MAX_CHAN 8 /* total of channels */ 46 #define START_CHAN_OFFSET 0 47 #endif /* CONFIG_CORE_DSP0 */ 48 49 #define SUNXI_CLK_DMA CLK_BUS_DMA 50 #define SUNXI_CLK_MBUS_DMA CLK_MBUS_DMA 51 #define SUNXI_RST_DMA RST_BUS_DMA 52 53 /* 54 * The source DRQ type and port corresponding relation 55 */ 56 #define DRQSRC_SRAM 0 57 #define DRQSRC_SDRAM 1 58 #define DRQSRC_SPDIF 2 59 #define DRQSRC_DAUDIO_0_RX 3 60 #define DRQSRC_DAUDIO_1_RX 4 61 #define DRQSRC_DAUDIO_2_RX 5 62 /* #define DRQSRC_RESEVER 6 */ 63 #define DRQSRC_AUDIO_CODEC 7 64 #define DRQSRC_DMIC 8 65 /* #define DRQSRC_RESEVER 9 */ 66 /*#define DRQSRC_NAND0 10 */ 67 /* #define DRQSRC_RESEVER 11 */ 68 #define DRQSRC_GPADC 12 69 #define DRQSRC_TPADC 12 70 #define DRQSRC_UART0_RX 14 71 #define DRQSRC_UART1_RX 15 72 #define DRQSRC_UART2_RX 16 73 #define DRQSRC_UART3_RX 17 74 #define DRQSRC_UART4_RX 18 75 #define DRQSRC_UART5_RX 19 76 /* #define DRQSRC_RESEVER 20 */ 77 /* #define DRQSRC_RESEVER 21 */ 78 #define DRQSRC_SPI0_RX 22 79 #define DRQSRC_SPI1_RX 23 80 #define DRQSRC_SPI2_RX 24 81 /*#define DRQSRC_SPI3_RX 25 */ 82 /* #define DRQSRC_RESEVER 26 */ 83 /* #define DRQSRC_RESEVER 27 */ 84 /* #define DRQSRC_RESEVER 28 */ 85 /* #define DRQSRC_RESEVER 29 */ 86 #define DRQSRC_OTG_EP1 30 87 #define DRQSRC_OTG_EP2 31 88 #define DRQSRC_OTG_EP3 32 89 #define DRQSRC_OTG_EP4 33 90 #define DRQSRC_OTG_EP5 34 91 #define DRQSRC_TWI0_RX 43 92 #define DRQSRC_TWI1_RX 44 93 #define DRQSRC_TWI2_RX 45 94 #define DRQSRC_TWI3_RX 46 95 #define DRQSRC_R_TWI0 48 96 97 /* 98 * The destination DRQ type and port corresponding relation 99 */ 100 #define DRQDST_SRAM 0 101 #define DRQDST_SDRAM 1 102 #define DRQDST_SPDIF 2 103 #define DRQDST_DAUDIO_0_TX 3 104 #define DRQDST_DAUDIO_1_TX 4 105 #define DRQDST_DAUDIO_2_TX 5 106 /* #define DRQSRC_RESEVER 6 */ 107 #define DRQDST_AUDIO_CODEC 7 108 /* #define DRQSRC_RESEVER 8 */ 109 /* #define DRQSRC_RESEVER 9 */ 110 /*#define DRQDST_NAND0 10 */ 111 /* #define DRQSRC_RESEVER 11*/ 112 /* #define DRQSRC_RESEVER 12 */ 113 #define DRQDST_IR_TX 13 114 #define DRQDST_UART0_TX 14 115 #define DRQDST_UART1_TX 15 116 #define DRQDST_UART2_TX 16 117 #define DRQDST_UART3_TX 17 118 #define DRQDST_UART4_TX 18 119 #define DRQDST_UART5_TX 19 120 /* #define DRQSRC_RESEVER 20 */ 121 /* #define DRQSRC_RESEVER 21 */ 122 #define DRQDST_SPI0_TX 22 123 #define DRQDST_SPI1_TX 23 124 #define DRQDST_SPI2_TX 24 125 /*#define DRQDST_SPI3_TX 25 */ 126 /* #define DRQSRC_RESEVER 26 */ 127 /* #define DRQSRC_RESEVER 27 */ 128 /* #define DRQSRC_RESEVER 28 */ 129 /* #define DRQSRC_RESEVER 29 */ 130 #define DRQDST_OTG_EP1 30 131 #define DRQDST_OTG_EP2 31 132 #define DRQDST_OTG_EP3 32 133 #define DRQDST_OTG_EP4 33 134 #define DRQDST_OTG_EP5 34 135 #define DRQDST_TWI0_TX 43 136 #define DRQDST_TWI1_TX 44 137 #define DRQDST_TWI2_TX 45 138 #define DRQDST_TWI3_TX 46 139 #define DRQDST_R_TWI0 48 140 #endif /*__DMA_SUN8IW20_H__ */ 141